Application Note 39 February 1990

Parasitic Capacitance Effects in Step-Up Transformer Design Brian Huffman

One of the most critical components in a step-up design Figure 2 shows the high frequency current paths of the like Figure 1 is the transformer. Transformers have para- parasitic capacitors. In the analysis of operation assume sitic components that can cause them to deviate from the input and output voltages are at AC ground. Thus, the their ideal characteristics, and the parasitic capacitance parasitic capacitors are all in parallel. The transformer’s associated with the secondary can cause large resonating secondary provides the AC current path for these capaci- current spikes on the leading edge of the switch current tors. The current flowing through the secondary produces waveform. These spikes can cause the regulator to exhibit N times the current in the primary. As the parasitic ca- erratic operating conditions that manifests itself as duty pacitance and turns ratio increase, the primary current cycle instability. This effect is exacerbated in very high becomes progressively larger. voltage designs. Attention to transformer design will cure this problem.

D1 MUR1100 V V OUT IN 330V 8V TO 15V L1 5A30 4 5 • 11 R1 50mA 3W + 6.8k** 100μF VIN MUR110 C1 ••8 7 2 200pF** VSW + D2 100μF LT1070 MBR360** 475k*

VFB

GND VC 1.82k*

1k

1μF AN39 F01

* = 1% FILM RESISTORS ** = OPTIONAL—SEE TEXT FOR DETAILS MBR360 = MOTOROLA MUR1100 = MOTOROLA L1 = COILTRONICS* CTX30203C04 Figure 1. High Voltage Power Supply

CPS CD

ID MUR1100 IPS • 4, 5 L1 11

IPRI = N(IPS + IS + ID) CS IS

7, 8 2 • VSW ISECONDARY

MUR1100 = MOTOROLA AN39 F02 L1 = COILTRONICS CPS = PRIMARY-TO-SECONDARY INTERWINDING CAPACITANCE CS = SECONDARY DISTRIBUTED CAPACITANCE CD = DIODE CAPACITANCE N = TURNS RATIO Figure 2. AC Current Paths for Parasitic Capacitors an39f

AN39-1 Application Note 39

The operation waveforms for this circuit are shown in reduced in magnitude by a factor of the turns ratio squared. Figure 3. When the switch (VSW pin—Trace A) is turned For example, if N = 10, then a 200Ω resistor looks like 2Ω “on” the primary is pulled to ground. The secondary and a 100pF capacitor looks like 0.01μF, so even a small cannot instantly follow this action because of the loading secondary capacitance can heavily load the primary. The effects of its parasitic capacitors. The effects of the para- series LC forms a self-resonating circuit that rings at the sitic capacitance can easily be seen in the leading edge resonant frequency of the transformer. of the switch current waveform (Trace B). This current The output switching diode, D1, can also cause narrow spike is caused by the loading effect of the secondary spikes on the current waveform. In this case, the reverse parasitic capacitances. The secondary output (Trace D) recovery time of the diode is the important parameter. swing can exceed 600V. As such, a large amount of charge Reverse recovery time occurs because the diode “stores” (Q = C • V) is needed to swing this node during the charge during its forward conducting cycle. This stored switching transients. charge causes the diode to act like a low impedance con- The secondary current is amplified by the turns ratio ductive element for a short period of time after reverse and produces a primary current; IPRI = N(IPS + IS + ID). drive is applied. This amplifying effect can be observed by comparing the There is a short period of time (blanking time) following secondary current (Trace C), which does not include the switch turn “on” during which the LT1070 ignores the effects of I , with the switch current (Trace B). The result S switch current waveform. This blanking time eliminates is a rather large current spike. premature termination of the “on” pulse caused by the The oscillatory nature of the response is formed by a se- leading edge current spike in the current waveform. Once ries combination of the leakage inductance and reflected this blanking time has elapsed the output switch will turn secondary capacitance (Figure 4). Any impedance placed “off” when the peak switch current reaches the threshold across the secondary appears at the primary terminals level established by the error amplifier output (VC pin).

VIN A = 50V/DIV VSW LLEAKAGE VIN N2 • (C + C + C ) VSW S PS D

B = 2A/DIV ISW LT1070

GND C = 0.5A/DIV ISECONDARY

AN39 F04

D = 200V/DIV VSECONDARY Figure 4. Simplified Primary Model During Transient Conditions

HORIZ = 5μs/DIV AN39 F03

Figure 3. Operating Waveforms for High Voltage Converter

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AN39-2 Application Note 39

This internally fixed blanking time, 400ns, is appropriate The substrate diode current can be eliminated by placing for typical applications. However, for high voltage appli- a Schottky diode, D2, between the VSW pin and ground cations the blanking time becomes a critical parameter. (Figure 1). The reverse primary current will flow through The effects of the transformer’s parasitic capacitance is to the Schottky diode instead of the LT1070. Another way to extend the “spike” width past the blanking time causing prevent the substrate diode from conducting is to place an the LT1070 to mistrigger, as shown in Figure 5. The duty RC snubber, R1-C1, on the secondary. This will attenuate cycle variations in the switch pin (Trace A) and switch cur- the ringing. rent (Trace B) waveforms are the result of this problem. Well known transformer winding techniques can be used Figure 6 details the interaction between blanking time and to minimize parasitic capacitance in step-up transformers. peak switch current. Notice that the switch is turned “off” The basic technique is to wind the secondary layers in a as soon as the LT1070 samples the switch current. For manner that minimizes the voltage difference between the LT1070 to function properly, the spike current must adjacent layers. A standard way of accomplishing this is be below the normal peak switch current before the 400ns to wind several separate secondary “stacks” on a split blanking period is over. bobbin. This and other techniques will cause a dramatic Another problem induced by the parasitic capacitance can reduction in secondary capacitance. also be seen in Figure 3. High reverse current can flow in For transformer information contact: the VSW pin (Trace B) due to the oscillatory nature of the transformer. This will forward bias the LT1070’s substrate Coiltronics diode, which is inherent in the output transistor (see Ap- 984 Southwest 13th Court pendix A). Unwanted current can flow almost anywhere Pompano Beach, FL 33069 within the IC’s circuitry when the substrate diode is forward 305-781-8900 biased, causing unpredictable duty cycle behavior.

A = 20V/DIV VSW A = 20V/DIV VSW

B = 1A/DIV ISW B = 2A/DIV ISW

HORIZ = 20μs/DIV HORIZ = 2μs/DIV

Figure 5. Duty Cycle Instability Due to Current Spike Figure 6. Detail Waveforms of Switch Current Spike

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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. AN39-3 Application Note 39

APPENDIX A If the vertical NPN output switch transistor is operating in In a junction isolated IC the monolithic transistors are its normal mode, either “on” or “off,” the parasitic transis- surrounded by an isolating P-N junction, as illustrated tor is off and will have no effect. The parasitic becomes in Figure A1. When this junction is reverse biased, it active when the vertical collector is pulled to a potential electrically isolates one device from another on the chip. below that of the substrate by the reverse switch current. However, this device structure also forms parasitic lateral This forward biases the collector substrate junction, which NPN transistors (see Figure A2). The P substrate is the is commonly called the substrate diode. As a result, the base, the N-epi region is the emitter and the collector is parasitic NPN draws current from other portions of the any other N-epi pocket. A simplified schematic diagram circuit. This current will add to the base drive of lateral of the NPN cell is shown in Figure A3. PNPs and to the collector current of NPNs, causing the IC to behave in mysterious and unpredictable ways (see Figure A2).

EMITTER BASE COLLECTOR

N+ N+ P PP N–

N+ AN39 FA1 P TIED TO SUBSTRATE GROUND PIN  OF LT1070

Figure A1. Junction Isolated NPN Structure

(LATERAL PNP) (VERTICAL NPN) (VERTICAL NPN) ISOLATION ISOLATION COLLECTOR EMITTER COLLECTORBASEWALL EMITTER BASE COLLECTOR WALL EMITTER BASE COLLECTOR

+ + + + + P P Q1 P Q1 PPPN N N P N PPN N– N– N–

N+ N+ N+ AN39 FA2

PARASITIC NPN PARASITIC NPN P SUBSTRATE

Figure A2. Locations Where the Lateral NPN Occur

VSW (LT1070 SWITCH PIN)

LT1070 OUTPUT ANY POCKET SWITCH IN THE CIRCUIT PARASITIC BASE LATERAL NPN SUBSTRATE LT1070 GROUND PIN

AN39 FA3

Figure A3. Schematic Diagram of LT1070’s Output Switch with Parasitic

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