Eindhoven University of Technology

MASTER

Miller effect tuned 60GHz VCO with large tuning range using 65nm CMOS process

Lont, M.

Award date: 2008

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Miller Effect Tuned 60GHz VCO with Large Tuning Range Using 65nm CMOS Process

Master Thesis

Maarten Lont Mixed-signal Microelectronics, Eindhoven University of Technology Contents

1 Introduction 1 1.1 60GHz Project description. 1 1.2 Master project description . 2 1.3 Related work . 2

2 VCO 3 2.1 Oscillation Criteria . 3 2.2 Kegative resistance oscillator . 4 2.2.1 Small Signal Negative Resistance 5 2.2.2 Large Signal Negative Resistance 6 2.3 Open Loop Gain ...... 8 2.3.1 Small Signal Open Loop Gain. 8 2.3.2 Large Signal Open Loop Gain. 9 2.4 Phase Noise . 10

3 RLC network and Quality Factors 12 3.1 LC network . 12 3.2 Quality Factor . 13 3.2.1 Quality Factor of an Inductor 13 3.2.2 Quality Factor of a Capacitor 14 3.2.3 Quality Factor of an RLC circuit 15 3.2.4 Quality Factor of a practical LC Circuit 15 3.3 TUning ... 17 3.4 Phase Noise .. 18

4 Oscillator Tuning 23 4.1 Second Order LC Network . 23 4.1.1 Quality Factor Second order LC ~etwork 25 4.1.2 TUning . 25 4.1.3 Comparison of First and Second Order LC network. 26 4.2 Variable Capacitance versus Variable Inductance 27 4.3 Transconductor Tuning . 27 4.3.1 Simulation Results 29 4.4 Varactors . 31 4.5 Miller Effect ...... 31 4.5.1 Purely Resistive Output Impedance 33 4.5.2 Inductive Output Impedance .... 34 4.5.3 Optimal inductance as function of gain 35 4.5.4 Optimize TUning Range 36 4.5.5 Optimal parameters . 36

I CONTENTS II

5 VCO design 37 5.1 VCO Core Design 37 5.1.1 Component Choice 40 .5.2 Design of Miller Tuning . 40 5.2.1 Effects of Noise in Current Mirror 42 5.3 Output Buffer . 47 5.3.1 Component Choice 49 5.4 Fringe Capacitance 51

6 Layout 53 6.1 Impact Of Interconnects On Circuit 53 6.2 VCO Core ... 55 6.3 Miller Tuning . 56 6.4 Output Buffer. 57 6.5 Complete VCO 57

7 Simulations 59 7.1 Decouple Capacitance 59 7.2 Negative Resistance . 60 7.3 Miller Tuning ..... 62 7.3.1 LC tuning circuit 62 7.4 VCO . 62 7.4.1 Target Specification Comparison with Simulation 64

8 ~easurement 65 8.1 De-embedding. 65 8.2 Test structures 66 8.3 VCO . 66 8.4 Comparison between simulations and measurements 68

9 Comparison with reported VCOs 70

10 Own Contribution 72

11 Conclusions and recommendations 73

12 References 74

A VCO circuits 77 A.1 VCO core . 77 A.2 Miller tuning circuit 78 A.3 Output buffer . 79

B Graduation paper 80 Acknowledgments

I would like to thank NXP for giving access to CMOS 65nm technology and especially Edwin van der Heijden and Anton de Graauw for there help. Also I would like to thank Reza Mahmoudi for his guidance.

III Abstract

Modern wireless systems aim for the license free 60GHz frequency band to meet today's ever increasing call for higher bit rates. Current wireless standards are less suited, because of bandwidth restrictions. The large tuning range and high oscillation frequency are the biggest challenges. Varactors are often used to tune the oscillation frequency, but at high frequencies the quality factor and tune-ability begin to decrease and varactors become less desirable. The presented VCO makes use of an actively tuned capacitor using the Miller effect using a standard NMOST transistor. Because the VCO is actively tuned the phase noise performance will be deteriorated. A CMOS technology is used to decrease the manufacturing costs and make it possible to integrate the digital circuits on the same chip. This paper presents a VCO operating in the frequency range from 59.5GHz to 66.1GHz. The phase noise performance is dependent on the oscillation frequency and is between -68dBc/Hz and -82dBc/Hz.

v Chapter 1

Introduction

Modern multimedia systems demand a wideband wireless transceiver architecture and standard. The 60GHz band was chosen because it is license-free. This band has a bandwidth of 6GHz, which is high enough for even the most demanding applications. The details of the standard are still under discussion. The 60GHz band is mainly suited for short distance communication since the oxygen in the air absorbs the 60GHz electro magnetic energy. This limitation is an advantage since it reduces the problems with interfering transmissions, increases frequency reuse and increases the security of the link. Because the attenuation is high the transmitters in the vicinity are not received and can't interfere with the local transmission. The transmissions are secure because only devices in close proximity can receive the signal.

1.1 60GHz Project description

A zero-IF architecture is chosen for the transceiver, the received 60GHz signal is directly demod­ ulated to obtain the baseband signal. This architecture is chosen because only one oscillator and mixer are required. The disadvantage is that the oscillator has to oscillate at 60GHz and has to span the entire frequency range and clock-feedthrough is possible. A diagram of the zero-IF architecture is shown in figure 1.1. The details of this architecture is outside the scope of this work.

TX Input signal

VCOI---....L..--, RX

Figure 1.1: Zero IF architecture

The project uses CMOS technology because digital and analog circuits can easier be integrated on a single chip using CMOS than using SiGe. SiGe has the advantages that it has a better noise performance and the transconductance of the transistors are higher for the same current.

1 CHAPTER 1. INTRODUCTION 2

1.2 Master project description

The target specifications of the VCO presented are summarized in table 1.1. The proposed VCO has a negative resistance architecture as will be explained in section 2.2, because it is a very robust architecture.

Specification Target Output power -13dBm with a lOOn differential output Frequency band 58GHz-64GHz Phase noise < -85dBc/Hz @ IMHz

Table 1.1: Target specifications

Most of todays negative resistance VCO designs use varactors to tune the frequency. This is fine for oscillator designs operating at lower frequencies where inductor losses dominate the tank losses. At higher frequencies the quality factor decreases and thus the losses of the varactors increases and begin to dominate the tank losses. To arrive at a stable oscillation these losses will have to be compensated. The losses should be minimized. The oscillation criteria are discussed in section 2.1. At high frequencies the tune-ability of varactors degrades. The tune-ability can be expressed as gmax, for varactors the factor at 60GHz is approximately 2.1. The proposed VCO makes use o¥,'ihe Miller effect for the tuning mechanism, see section 4.5. The maximal and minimal capacitance ratio is 2.6 at 60GHz. The main goal of this work is to demonstrate a 60GHz VCO with large tuning range using the Miller effect tuning. Therefore it is chosen to use a non-quadrature architecture to simplify the design.

1.3 Related work

There are not many publications on CMOS oscillators operating at 60GHz, most VCOs use SiGe technology. SiGe is usually chosen because it has a higher it, better l/f noise performance and higher Q of on chip passive components. The downside is that analog and digital integration is more difficult when SiGe is used. Negative resistance VCOs operating on very high frequencies using SiGe:C BiCMOS technology are reported in [22] [21] [10]. The core of the VCO presented in [21] operates at 41GHz and uses a push-push architecture to obtain a single ended output at 82GHz. The VCO described in [Il] also uses the push-push architecture and InGaP/GaAs technology. A 60GHz low power CMOS transceiver is described in [20] which uses a 60GHz VCO with a small tuning range. The transceiver in [3] uses a 30GHz CMOS VCO with a frequency doubler. Another VCO operating at 60GHz using CMOS technology is reported in [7] with a good phase noise performance but a very small tuning range of lOOMHz. There are no CMOS VCO's reported which operate at 60GHz and have a large tuning range. There are a couple of VCO designs that address the tuning problem. The Miller tuning used in this work is already demonstrated in [17] and [18] using 0.8jlm BiCMOS technology operating on 2GHz, but no measurement results were reported. A transconductor-tuned oscillator operating on 26GHz is demonstrated in [81 [9]. Chapter 2 veo

A Voltage Controlled Oscillator (VCO) has several important parameters: center frequency, tun­ ing, phase noise and power consumption. The center frequency and tuning range will be discussed in section 3.1 and 3.3. The phase noise will be modeled in section 2.4. It is difficult to compare different VCOs with each other. Because different technologies are used and the circuit topologies can differ. To compare different VCO designs Figure Of Merits (FOM) are used. FOMs make it easier to compare different circuits, but still some caution is needed when comparing different VCOs. The tuning range is expressed as a percentage of frequency shift of center frequency. The tuning range can easily be compared. It is more difficult to compare the phase noise performance. The FOM used is given by equation 3.85 it is copied here:

FOM = L (6.f) - 20 log (~~f ) + 10 log (Pdc) (2.1 )

The FOM removes the dependence on center frequency and offset frequency and it includes the dc power consumption Pdc , a lower FOM is better.

2.1 Oscillation Criteria

x (jw) Y(jw) x (jw) Y (jw)

x· (jw)

(a) Closed Loop Gain (b) Open Loop Gain

Figure 2.1: Feedback system

An oscillator can be seen as a feedback circuit as is depicted in figure 2.1(a). The H (jw) block is an amplifier and the (3 (jw) is the frequency dependent element. The input signal Xi (jw) is normally not present. For an oscillator to start oscillating an input signal is required. This usually is circuit noise. The noise is amplified and fed back to the input through the feedback circuit (3 (jw). If the open loop gain is high enough the oscillation amplitude will start to grow. There are two criteria, called the Barkhausen criteria, which must be met to have a stable oscillation. The first condition is the "gain condition" and is given by equation 2.2, the open loop gain 0: should be 1. This condition ensures that the output signal does not grow nor decreases. The second condition is called the "phase condition" and is given by equation 2.3. This condition

3 CHAPTER 2. VCO 4

0 states that the open loop phase shift should be k times 360 , which is needed for the positive feedback.

IH (jw) (3 (jw)1 (2.2) LH (jw) (3 (jw) (2.3) For an oscillator to start oscillating the open loop gain should be larger than one, this will increase noise until stable oscillation is reached. Equation 2.4 ensures that the signal power is limited, it holds in all practical oscillators. Psig is the signal power.

80: < 0 (2.4) 8Psig There are a number of frequently used oscillator topologies, the most often used are: ring oscillators, Colpitts oscillator, Hartley oscillator, Clapp oscillator and negative resistance oscillator. In this work we will analyze the negative resistance oscillator.

2.2 Negative resistance oscillator

Alternatively to the feedback approach, a negative resistance approach can be used for some oscillator topologies. This is the case when both Hand (3 can be written as impedances or admittances. The negative resistance model is shown in figure 2.2. The oscillator is a differential oscillator, to calculate the open loop gain both sides have to be opened. When opening both sides the two subsystems seem to be not connected anymore, this is not the case. Only the voltages are decoupled, the currents can still flow through the cuts.

Active Part

Y '---""--:--=--:---+---' neg LV

+ LV*

Passive Part

Figure 2.2: Negative Resistance Oscillator Model

The voltage L V* acts as the input signal, the current i is generated by the active part which leads to a voltage difference L V at the passive part. The relationships for the active and passive part are given by 2.5 and 2.6 respectively.

LV* x -Yneg (2.5)

LV (2.6) Yp

The open loop gain 0: is given by 2.7 substituting 2.5 in 2.6 leads to the open loop gain of the system given by 2.8. LV 0: (2.7) LV*

_Yneg 0: (2.8) Yp 5 2.2. NEGATIVE RESISTANCE OSCILLATOR

The amplitude is stable when the open loop gain is one, see the previous section. This leads to the relationship between the active and passive admittance given by 2.9.

Yp + Yneg = 0 (2.9) The conductances 1";, and Yneg are both complex admittances, their sum is zero when the sums of both the real and imaginary parts are zero,

~ {Yp} + ~{Yneg} o (2.10) 8' {Yp} + 8' {Yneg } o (2.11)

2.2.1 Small Signal Negative Resistance An implementation of negative conductance is given in figure 2.3(a). The two MaSTs implement the negative conductance and the current source is only necessary for biasing. The small signal

\7- t -

Tds

(a) Circuit (b) Small signal model

Figure 2.3: Cross Coupled Pair model is depicted in figure 2.3 (b), in the small signal model it is assumed that both MOST M1 and M2 are identical. The small signal capacitances can be moved to the feedback loop (3. And the negative resistance depends on the output resistance Tds and the trans-conductance gm. The small signal input conductance is calculated by solving the nodal equations and the real part is given in equation 2.16. The parasitic capacitances are given by equation 2.18. Since v,;+ and v,;- are connected i+ = -i-.

,.~s + sCgs + s2Cgd gm - S2Cgd gm - s2C --!.- sC s2C (2.12) gd T'ds + gs + gd [ 1 -1 i+ (2.13) 6V 1 - gmTds 2C C gs Yneg + S gd + s-2 (2.14) 2Tds Yneg Gneg + jBneg (2.15) 1 - gmTds (2.16) 2Tds

w 2Cgd + Cgs) (2.17) ( T 1 2Cgd + 2CgS (2.18) CHAPTER 2. VCO 6

The transconductance gm is given by equation 2.19. Note that this is only true for a very simple MOST model, not for a practical transistor. But the model still gives some useful insights.

gm (2.19)

2.2.2 Large Signal Negative Resistance

The analysis of the negative resistance in the previous section is only valid for small signals, since the linearized small signal model of the transistors are used. In this section the output resistance r ds and the parasitic capacitances Cpar are assumed to be constant and equal to the values in the small signal model. This assumption holds only when the transistors operate in the saturated region. In practise the drain current is an quadratic function of the gate source voltage. Note that this is still a simplified view. The model is given in equation 2.20, the output resistance is neglected for the moment.

W 2 K- (V S - v,t) (2.20) 2L 9

The parasitic capacitance Cpar given by 2.18 can be assumed to be the same for the large signal model as for the small signal model. The parasitic capacitance is not taken into account when calculating the large signal negative resistance, it is transferred to the feedback path (3. For the first analysis the output resistance rds is neglected, but it is added later. The nodal equations for the currents are given below,

(2.21 )

(2.22)

r (2.23) v+, - v-, (2.24) L,V (2.25)

Since Vsl = Vs2 the equation for L,V is,

L,V (2.26)

Rewriting equation 2.20 gives,

~sx (2.27)

Substituting 2.27 in equation 2.26 leads to,

L,V (2.28)

Squaring both sides gets rid of the square root, but note that squaring also removes the minus sign. Keep in mind that 1+ decreases as V/ increases. So the conductance seen at the input will 7 2.2. NEGATIYE RESISTANCE OSCILLATOR be negative.

KW 6y2 I++r-2VI+I- (2.29) 2L KW 6y2 Iss - Jr;s - 612 (2.30) 2L JI2 - 612 I _ KW 6y2 (2.31 ) ss ss 2L KW 12 - 612 12 + (KHl) 2 6y4 _ 2 6y2I (2.32) ss ss 2L 2L ss ~ 612 KW 6 y2I _ ( KW) 2 6 V4 (2.33) L ss 4 L

~6VKW ss 61 = J41 L _ 6V2 (2.34) 2 L KW When squaring both sides the minus sign was lost, therefore we have to introduce it again. The equation for 61 becomes:

_~6VKW ss 61 J4I L _ 6V2 (2.35) 2 L KW

The input admittance of the circuit without the resistance r ds for a certain input voltage is given in equation 2.38. The admittance is equal to the slope ofthe current vs voltage characteristic. fJI+ (2.36) Gin 86V 1861 Gin (2.37) 286V _ KW 4J!l'f - 26V 2 Gin (2.38) 4L J4I

The current 61 as function of 6V is given in figure 2.4(a). The input admittance as function of 6V is depicted in figure 2.4(b).

6V

(a) 61 as function of 6 V (b) Gin as function of 6V

Figure 2.4: Large signal I/V and Gin/V characteristics

As can be seen the input admittance is a function of the input signal. At a certain input voltage the negative conductance will drop to zero. This happens when one of the transistors (M1 or M2) turns of and the total bias current Iss goes through one transistor. This happens for the input voltage 6 Vil given by equation 2.39. Beyond this voltage the model no longer holds.

(2.39) CHAPTER 2. VCO 8

\Vhen the input voltage 6 V is zero the negative conductance becomes equal to the small signal negative conductance in equation 2.16. In practise the output resistance Tds can not be neglected. The input admittance can be seen as the admittance Gin from equation 2.38 parallel with 2Tds and parallel with Cpar . The complete input admittance is then given by 2.40.

KW 4k'v; - 26V 2 1 --- +-+sC (2.40) 4L 4T"L _ 6 V2 2Tds par VKW

The negative conductance is the real part of the input admittance and is given by equation 2.41. The large signal trans-conductance Grn can be written as in equation 2.42. This leads to the negative conductance given by 2.43. Which is the same as the small signal negative conductance in equation 2.16 except for the large signal Grn.

4I"L _ 26V 2 1 KW KW Gneg ----- (2.41 ) 2Tds 4L 4T

lim Grn (2.44) .6v--->o

2.3 Open Loop Gain

The Barkhausen loop gain criteria is important, since it must be met to get a stable oscillation. The open loop gain must be larger than one for an oscillator to start up and it must decrease to one to have a stable power.

2.3.1 Small Signal Open Loop Gain The open loop gain was already calculated in section 2.2. The open loop gain was given in equation 2.8 and is copied below,

(2.45)

Instead of the admittance Yp, the impedance Zp is usually used. The equation of the open loop gain is given in equation 2.47.

(2.46)

(2.47)

Note that the parasitic capacitance Cpar of the negative conductance is transfered to Zp and Zp is given by equation 2.48 when w = woo The negative conductance Yneg is the small signal conductance given by 2.16.

(2.48) 9 2.3. OPEN LOOP GAIN

The open loop gain at resonance is given in equation 2.49. The open loop gain can be written as 2.50. gmrds - 1R o (2.49) 2rds p o -RpGneg (2.50)

2.3.2 Large Signal Open Loop Gain The oscillation amplitude will be stable if the average open loop gain a is 1. The average open loop gain is given in equation 2.54. Vmax is the maximum voltage of the signal and is equal to the amplitude of the signal. In equation 2.52 it is assumed that the negative conductance G neg is negative, which is true if the oscillator oscillates.

(2.51 )

(2.52)

(2.53)

(2.54)

The signal amplitude where the average loop gain becomes 1 is given by equation 2.60. The relationship for Vmax only holds when Vmax is smaller than approximately the supply voltage Vdd. Because the cross coupled pair has an inductive load, the voltage will rise above Vdd. But the voltage will never be twice Vdd. 'When Vmax is larger the voltage swing will be limited by the supply.

a 1 (2.55)

p 4Iss L _ V 1 _ R +R KW 2 (2.56) 2rds p 4L KlV max 1 1 KW 4Iss L _ V2 -+- max (2.57) R p 2rds 4L KW 4L 4Iss L _ V 2 (2.58) KW max ( r(1 1r KW R p + 2rds

ss Vmax 4I L (4L r ( 1 1 r (2.59) KW - KW R p + 2rds

2L IssKW _ 4 ( _l-r Vmax 2- + (2.60) KH" LR p 2rds

As can be seen above the maximum amplitude depends on the losses (right hand half of the square root) and on the effective Gm (left hand side). 'Vhen the losses grow the amplitude will decrease and when the losses become to high the oscillator will stop oscillating. This happens at:

1 1 ~J -+- IssKHT (2.61 ) R p 2rds 2 L 1 1 gm -+- (2.62) R p 2rds 2 CHAPTER 2. VCO 10

Open Loop Gain Criteria For an oscillator to go from a loop gain higher than one to a loop gain equal to one equation 2.4 on page 4 should hold. The small signal open loop gain does not obey this criteria, the small signal loop gain does not predict that the signal power will be limited. The large signal open loop gain can explain the limited output power. The loop gain criteria is copied in 2.63. For positive values of 6 V equation 2.66. For negative values 6 V should be replaced with -6V.

80: < 0 (2.63) 8Fsig -Cneg 0: (2.64) Cp TdsCm -1 0: (2.65) 2TdsCp 80: 1 8Cm ----- (2.66) 86V 2Cp 86V 8Cm KW 1 41"L _ 26V 2) _6V KW (2.67) (4- 41ss L _ 6V2 86V 2L 41ssL _ 6V2 J KW KW 8Cm < 0 (2.68) 86V

As was stated before the voltage 6 V is limited, the upper limit is given by 2.39. Keeping in mind this upper limit, the right part between brackets of equation 2.67 lies between 3 and 4. The derivative of the open loop gain is smaller than zero. For a certain value of 6 V the open loop gain becomes 1.

2.4 Phase Noise

Phase noise is an important oscillator parameter. Phase noise will deteriorate the noise perfor­ mance of the whole circuit. In practice phase noise is non-linear and time dependent [12]. But it has been shown that the Linear Time Invariant (LTI) model of Leeson [13] gives a good approxi­ mation.

x (jw) Y (jw) H(jw)

Figure 2.5: Feedback system

An oscillator can be seen as a feedback circuit, see figure 2.5. The input X (jw) is the circuit noise. We are interested in the phase noise performance when the oscillator is stable. This is the case when the open loop gain is equal to one. Given the total circuit noise is i~ the amplified noise (i~ut) can be derived by multiplying the input noise by the square of the closed loop transfer function, see equation 2.69.

2 ~Zout = ""'2IHzn cl ('1)1J (2.69)

The output noise in 2.69 consists of both phase noise and amplitude noise. The equipartition theorem of thermodynamics tells us that, in equilibrium, the amplitude and phase noise power are 11 2.4. PHASE NOISE

equal[12]. The phase noise power is half that of i~ut. The phase noise is a noise to signal ratio and is given in equation 2.70. Usually the phase noise is given in dBc/Hz the corresponding equation for the phase noise is given by 2.71.

1 i~ut L (Lj) 2-.2-- (2.70) Zsignal

1 2 .2i~ L(Lj) 10 log (-2 IHcl (j [ia + Li]) 1 ) (2.71) Zstgnal

The phase noise for a practical oscillator with a LC load will be discussed in section 3.4. Chapter 3

RLC network and Quality Factors

In a normal cross coupled oscillator the feedback f3 consists of a single coil and capacitor as is depicted in figure 3.1. The LC circuit (tank) sets the frequency of oscillation of the oscillator. In practice there always will be some losses, their influence is examined in section 3.2.4.

3.1 LC network

Before examining the influence of the resistive losses of the RLC network an LC network is exam­ ined. The networkis depicted in 3.1.

LL

c 2

Figure 3.1: Single Order LC network

An important parameter ofthe LC network is its resonance frequency. To analyze the resonance frequency it is convenient to redraw the tank. The bottom of the tank in figure 3.1 is connected to the cross coupled active part of the oscillator. The capacitance !if can be redrawn as two capacitors C in series. Since it is a differential circuit, the connections in the middle can be seen as virtual ground for the fundamental frequency (not for the higher order harmonics). The new circuit is drawn in figure 3.2(a). When determining the impedance of the LC circuit the part below the dashed line can be removed leading to the single ended circuit in figure 3.2(b). Since the circuit is changed from differential to single ended, the differential impedance Zdiff is divided by 2, Zdiff = 2Zsingle' The input impedance Zsingle of the tank in figure 3.2(b) is given in equation 3.1.

sL (3.1 ) Zsingle 1 + s2LC jwL (3.2) Zsingle 1 - w2LC 1 Wo vrc (3.3)

12 13 3.2. QUALITY FACTOR

L --~-~-----

C

L

(a.) Differentia.l LC network (b) Single ended LC network

Figure 3.2: Single ended tank

At the resonance frequency the denominator of the impedance is zero leading to a theoretical infinite impedance. At this frequency the oscillator can oscillate because the output is "floating" and not short circuited to ground, the energy in the oscillator is not lost. The resonance frequency is given in equation 3.3. Note that this is the same for the single ended and differential tank.

3.2 Quality Factor

The LC circuit given so far is an ideal circuit, there is still no loss modeled. In any practical oscillator there is always loss in the tank. To get a stable oscillation the total loop gain should be one. In a world without any losses there is no need for an amplifying stage in an oscillator, since there is no loss. In real world oscillators there is always loss and an amplifying stage is needed to regain the lost energy. The loss should be kept as low as possible, because at high frequencies a large gain is difficult to achieve and a big loss also leads to large power consumption. The quality factor is a measure for loss. The bigger the quality factor the lower the loss. The quality factor for a system is given in equation 3.4. In an ideal capacitor or inductor there is no power lost leading to an infinite quality factor.

Q w---Estored (3.4) F10st

3.2.1 Quality Factor of an Inductor

The losses of the inductor can be modeled by a series resistance, as is depicted in figure 3.3. The energy lost in a lossy inductor is given in equation 3.5, the lost energy is dissipated by the resistance.

Figure 3.3: Lossy Inductor

The energy stored in an inductor is given by 3.6. The quality factor is given in 3.8. CHAPTER 3. RLC NETWORK AND QUALITY FACTORS 14

~12RL Plos (3.5) t 2 ~12L Estored (3.6) 2 1.12L QL w_2__ (3.7) ~12RL L QL w- (3.8) RL

The lossy inductor impedance is given by equation 3.9. It can be shown that the quality factor of an inductor is the imaginary part of the impedance divided by the real part.

RL + jwL (3.9) 8'{ZL} (3.10) R{ZL}

3.2.2 Quality Factor of a Capacitor The losses of a capacitance can be modeled using a resistance in parallel as is depicted in figure 3.4. The current through the capacitor and the resistor can be different, but the voltage over them is the same. Therefore it is more convenient to use the voltage then using the current for the stored and lost energy equations. The quality factor is given in equations 3.14. ----db- Rc

Figure 3.4: Lossy Capacitor

1 V 2 Plost (3.11) 2Rc ~CV2 Estored (3.12) 2 1.CV2 2 Qc wl"""""V2 (3.13) '2 Rc Qc wRcC (3.14)

The lossy capacitance admittance is given by equation 3.15. Complementary to the inductor, the quality factor of an capacitor is equal to the imaginary part of the admittance divided by the real part.

1 . Yc Rc +JwC (3.15) 8'{Yc} Qc (3.16) R{Yc} 15 3.2. QUALITY FACTOR

3.2.3 Quality Factor of an RLC circuit A parallel RLC circuit is drawn in figure 3.5. The admittance ofthe RLC circuit is given in 3.17. At resonance the imaginary part is zero, the inductor and capacitor cancel each other, the resonance frequency is given by 3.18.

R L

Figure 3.5: RLC network

1 1 -+sC+­ (3.17) R sL 1 Wo vrc (3.18) The quality factor can be expressed by the time averaged stored energy divided by the time averaged lost energy, see equation 3.19. At resonance the energy is "pumped around" between the inductor and the capacitance. The time averaged stored energy in the inductor is the same as for the capacitor. Using either the capacitor or inductor for the stored energy will do.

Estored Q w--- (3.19) ?Lost !CV2 (3.20) Estored 2 1 V 2 p/os (3.21 ) t 2 R lCV2 Q w!V'2""2 (3.22) 2R The energy is only pumped around when the oscillator oscillates, this is the case when w = woo The quality factor of the RLC circuit is given in equation 3.23.

Qlw=wo (3.23)

R (3.24)

3.2.4 Quality Factor of a practical LC Circuit The feedback part of the negative resistance oscillator is a LC circuit as was depicted in fig­ ure 3.2(b). The ideal capacitance and inductance from figure 3.2(b) are replaced by the non-ideal elements from figures 3.4 and 3.3 respectively, this gives the circuit shown in figure 3.6(a). To de-­ rive the quality factor it is easier to redraw the circuit as a RLC parallel circuit given by figure 3.5. To arrive at the RLC circuit the circuit needs to be transformed, which is shown in pictures 3.6(a) and 3.6(b).

The series circuit of Land RL is transformed to a parallel circuit of L I and R I . The admittance Y L of the series circuit is given in equation 3.26 and the admittance of the parallel circuit YLI is given in equation 3.27. CHAPTER 3. RLC NETWORK AND QUALITY FACTORS 16

C

(a) Tank with loss (b) RLe parallel circuit

Figure 3.6: Two equivalent RLC networks

1 YL (3.25) sL+RL R wL Y L (3.26) L R'i + w2£2 - J R'i + w2£2 1 1 YL1 --J- (3.27) R 1 wL 1

By equating the real parts R 1 is derived in equations 3.29.

1 R L - 2 (3.28) R 1 R'i + w £2 w2L2 R 1 R L +-- (3.29) R L R (3.30) 1 wL (~L + QL)

The same thing can be done for L 1 by equating the imaginary parts.

1 wL 2 (3.31 ) wL1 R'i + w L2 R2 L 1 L+ w/L (3.32)

L (3.33) 1 L (1 + ~'i)

The parallel resistors R 1 and Rc can be replaced by resistor R from figure 3.5. The inductor L 1 is approximately equal to L if QI » 1, which in practice is the case. After the transformation and substituting the resistors and the inductor the circuit in figure 3.6(a) is transfered to the RLC circuit given in figure 3.5.

The resistance Rc is derived from equation 3.14 and R 1 by 3.30. It is assumed that QL » 1, 17 3.3. TUNING

this simplifies equation 3.30 to 3.36.

RCRI R (3.34) Rc+Rl Qc (3.35) wC wQLL (3.36) QCQL~ R (3.37) ~c +wL1QL ~ L (3.38) (L QCQL Rlw=wo (3.39) VCQC+QL

The resistance in equation 3.39 should be equal to the resistance in equation 3.24 since the circuits are the same. The quality factor of the practical circuit depicted in figure 3.6(a) is equal to 3.40. The quality factor can be seen as a parallel system of the quality factors of the inductor and capacitor.

Q (3.40)

3.3 Tuning

The resonance frequency of the RLC circuit can be varied by changing the inductance value L or the capacitance value C. In practice the capacitance is used for tuning, because it is difficult to change the inductance value. Equation 3.41 gives the dependence of the resonance frequency on C.

1 Wo ex: (3.41 ) VC 1 Wo ex: ,;r;; (3.42)

The tuning range is given by 3.43. DW is the maximal frequency change and Wcenter is the center frequency. The tuning range is given as a percentage.

DW TR 100-- (3.43) Wcenter w+ -W- TR 100 w++w- (3.44) --2- + - TR 200W - W (3.45) w+ +W-

The minimum and maximum frequencies are given by 3.48 and 3.49 respectively. Where C+ and C- are the total maximal and minimal capacitances. The total capacitance can be seen as a parallel circuit of a fixed and a variable capacitance, see figure 3.7. The minimum capacitance value of a variable capacitor is given by C;;ar and is usually larger than O. In practice any circuit always has parasitic capacitances, because of the interconnects and parasitic capacitances of circuit elements. These parasitics are substituted in the fixed capacitance Cjixed. CHAPTER 3. RLC NETWORK AND QUALITY FACTORS 18

Cvar

Figure 3.7: Capacitance

C- Cjixed + C;;ar (3.46) C+ Cjixed + C;;ar (3.47) 1 w (3.48) VLC+ 1 w+ (3.49) VLC- [§i-I TR 200 c- (3.50) Iff- + 1

Given the fact that the maximum variable capacitance C;;ar is larger than the minimum vari­ able capacitance C;;ar' the tuning range is always positive. Substituting C± in 3.50 gives a new expression for the tuning range given in 3.52.

TR (3.51 )

TR (3.52)

To optimize the tuning range ~~:: should be maximized and C~'!a:d should be minimized.

3.4 Phase Noise

The phase noise is already discussed in section 2.4. The closed loop transfer function depends on the load of the negative conductance. The open loop gain H(jw) is the trance conductance gm multiplied with the load impedance Zp. The trans-conductance can be either the small signal trans-conductance or the large signal one. The impedance of the tank is given in equation 3.54. The RLC circuit from figure 3.5 is used.

1 1 -+jwC+­ (3.53) jwL R jwRL (3.54) R + jwL - w2 RLC

The load impedance Zp can be rewritten as 3.59 for more convenience. The oscillation frequency 19 3.4. PHASE NOISE is wo, see equation 3.3. jwRL Zp (3.55 ) R + jwL - w2RLC Zp R (3.56) 1 + j (wC - wlL) R 1 Wo (3.57) ,jLC Zp R (3.58) -"l- - ~ ) 1 + j ( Wo w R/£L R Zp (3.59) 1 +jvQ w Wo v --- (3.60) Wo w Q = Rji (3.61 ) The quality factor Q was calculated in 3.23. The closed loop gain He! is given by equation 3.65. The transfer function H (jw) is the trans-conductance multiplied by the load Zp. The input X (jw) is the circuit noise. H (jw) He! (jw) (3.62) 1 - H (jw) gm x rds -1 Z H (jw) (3.63) 2rds p gm x rds - 1 R H (jw) (3.64) 2rds 1 +jvQ gmxrds-l R He!(jw) = 2rds (3.65) l+jvQ - yR The frequency w can be written as Wo + 6w. For the phase noise we are only interested in frequencies close to the oscillation frequency, thus when 6 « Wo. In this case v can be rewritten as 3.68. w Wo v --- (3.66) Wo w (wo + 6w)2 - w5 v (3.67) Wo (wo + 6w) 26w vi (3.68) 6w«wo Wo We are interested in the phase noise performance when the oscillator is stable. This is the case when the open loop gain gm~;::-lR is equal to one. Using this and substituting 3.68 in 3.65 gives 3.69. 1 H cl (jw) (3.69) . (26W) Q J Wo 1 He! (jf) (3.70) j(~)Q

The closed loop gain from 3.69 can be substituted in the phase noise equation 2.71 on page 11, this leads to 3.71.

1 L(6f) 10 log 8Q2 (f)2"'2)6°f ~ (3.71) ( 7",gnal CHAPTER 3. RLC NETWORK AND QUALITY FACTORS 20

It can be seen that the phase noise model 2.70 predicts an slope of 6~2 in the phase noise. The phase noise should fall with -40(dBc/dec). At some point the phase noise hits the noise floor and will remain constant. In practice this is observed, but at low frequencies the phase noise should drop with a slope of -60(dBc/H z) (6~J)' This can be explained by the model by assuming that there is a t noise component in the circuit noise i~.

It is clear that the phase noise can be decreased by increasing the quality factor, increasing the signal power and decreasing the circuit noise i~. The model proposed by Leeson is given 1 by 3.72. The phase noise equation 2.70 can be rewritten as 3.72 , when the signal power Psignal is given by 3.73 and the factor D is given by 3.74. The total noise is the LC circuit noise times the parameter D, it is used as a noise fitting factor. The resistance R is the tank resistance.

L(6J) 1010Q" --1 (fo- ---DkT) (3.72) b e Psigna! 2 Q2 6fr ·2 R Psigna,l 2signal (3.73) ~ 2n D 4kT (3.74) Il

The circuit noise i~ is the sum of the noise in the tank due to the loss resistance R and the noise added by the active circuit. The biasing of the cross coupled pair also adds noise. The biasing noise of interest is low frequency noise. Since the biasing is on the common node of the differential cross coupled pair the noise should be only visible as common mode noise. But the current Iss including the noise current has influence on the negative resistance through Om. The current noise in Iss makes the effective negative resistance noisy and the low frequency noise is up converted to the band of interest through amplitude modulation. The biasing can also add noise this is investigated in section 5.2.1.

For now we only take into account the noise generated by LC circuit 3.75 and the thermal noise generated in the negative conductance 3.77. The noise generated by the cross coupled pair is twice the noise generated by one transistor since there are two transistors. But the effective noise of the cross coupled pair is half of that since the effective transconductance (gm) which generates the noise is half of the transconductance of one transistor.

Besides the noise generated in the VCO core and the LC circuit there are other thermal noise sources, for example the noise generated in the output buffers. Their contribution is modeled by the factor (31 in equation 3.79.

The transistors in the circuit also generate flicker noise which is proportional to t, at the frequency band of interest this noise can be neglected. The generated flicker noise is also partly up converted near the oscillation frequency, this noise is proportional to 1 ~10' The up converted flicker noise can not be neglected and is taken into account by the factor (3 which depends on the flicker noise sources and circuit specific properties, (3 is multiplied by 4~T to make it easier to simplify the expression for the total noise. The factors (3 and (31 can be used to fit the measured

lIn literature the constant F instead of 0 is used. since F is also used for the Noise Figure it is replaced by D to avoid confusion. 21 3.4. PHASE NOISE

or simulated phase noise with the model.

-'2­ 4kT ~RLC (3.75) R

-'2­ 2~ lcore (3.76) 2 4kT~(gm (3.77) 2 -/2- -'2- 1 4kT 4kT lRLC + ~core + f _ fo T(3 + T(31 (3.78)

i; ;;::; 4~ (1'00* + f ~ fo + (31 + 1) (3.79) gm 00* R (3.80) 2 The sum of the noise is given in 3.79. 00* is approximately the open loop gain of the VCO core. The parameter I' is approximately ~ for long channel devices, short channel devices have a larger f. There is still no theoretical basis for 1'. The minimum achievable phase noise given a lossy LC circuit and a noisy VCO core is given by equation 3.82. The phase noise is measured when the oscillator is stable, thus when the open loop gain 00* is 1.

2 4kj{ (,/00 + 11 + (31 + £ (6f) 1010g --1 (fo) 1) ) (3.81 ) (8Q2 6f i;ignal

2 kT (I' + 1 + (31 + £(6f) 1010g --1 (fo) 1 1) ) (3.82) (2Q2 6f Psignal The minimum achievable phase noise as function of the quality factor, for two different values for (3, is shown in figure 3.8(a), assuming that the signal power in the core is -32dB and I' is ~. The factor (31 is chosen to be zero because we are interested in the minimum obtainable phase noise only taking into account the phase noise generated by the VCO core and LC network. The phase noise, with a quality factor of 6, as function of the offset frequency (6f) is shown in figure 3.8(b). The phase noise with the flicker noise component starts with a -30dBc/dec slope which corresponds with a phase noise that is proportional to }3' After a certain offset frequency point the phase noise has a slope of -20dBc/dec which corresponds with a phase noise proportional to }2' When the flicker noise component is neglected by setting (3 to zero the slope is always -20dBc/H z. In practice the phase noise will never decrease endlessly with a slope of -20dBc/Hz, at a certain point the phase noise will hit a noise floor. The phase noise given by 2.70 is dependent on center frequency and the frequency offset. To compare the phase noise performance of different oscillators equation 3.83 is used.

£normalned (6f) 10 log [ (~:) 2 £ (6f)] (3.83)

1 1 £normalized (6f) 10100' ---~""2] (3.84) b [ 24Q2'2~s,gnal To compare the phase noise performance of different oscillators a FOM is used, the FOM is given by equation 3.85. The dissipated DC power is added to the normalized phase noise performance given by equation 3.83. The phase noise performance can be improved by consuming more power, because the output power will be higher, therefore the dissipated DC power is added. The more negative the FOM is, the better.

FOM = £(6f)-2010g (ij)+1010g (Pdc) (3.85) CHAPTER 3. RLC NETWORK AND QUALITY FACTORS 22

-75 --beta=O --beta=O _.- beta=106 , _. - bets=106 -80 -20

'N -a5 J: .,~ .,"il :2- :2- & & .! -90 .! z.0 z0 ~ -95 !! 0- ~ Q. -100

-100 -120

-1050'-----~----'--~-~-~,0--,~2--,-4-~,6--,a----.J20 -140 10' 10' 10' 10" 10 10' Q dl(Hz)

(a) Phase noise versus Quality factor (b) Phase noise versus offset frequency

Figure 3.8: Minimal phase noise Chapter 4

Oscillator Tuning

The oscillation frequency of a negative resistance oscillator is usually set by a LC circuit, which is also called the tank. In practice the LC circuit is lossy and can be replaced with a RLC circuit. Usually a variable capacitance is used as the tuning element. To compare the tuning capabilities of different oscillators the tuning range is expressed as a percentage of frequency variation with respect to center frequency as was discussed in section 3.3.

4.1 Second Order LC Network

A second order LC network consists of two cascaded first order networks. The second order circuit is depicted in figure 4.1. It was assumed that a second order LC network may increase the tuning range. Which is the main goal of the project. The tuning range could be larger because the oscillation frequency could be more dependent on the capacitances.

L 1 L 1

i2.l 2 L 2 L2

~ 2

Figure 4.1: Second order LC network

To make the calculations easier the differential circuit is transformed into a single ended LC circuit as was done in section 3.1. The final single ended circuit is shown in figure 4.2. The equation Zdiff = 2Zsingle still holds.

Considering only the parallel circuit of L 1 and C 1 the circuit is the same as the first order LC

23 CHAPTER 4. OSCILLATOR TUNING 24

Figure 4.2: Single ended second order LC network network from section 3.1. Zl is given by equation 3.1.

(4.1 ) 1+s2LlC l SLI SL 2 + --::---­ (4.2) 1 + s2LlC l

s3 L l L2C l + S (L l + L 2) (4.3) 1 + s2LlCl (4.4)

Adding inductor L 2 leads to equation 4.3. After adding C2,Y2 is derived in equation 4.6.

1 + s2LlCl SC 2 + -;;-=--=---=------;-=----::--:- (4.5) s3L l L 2C l + S (Ll + L 2)

s4L I L2C l C2 + s2 (CILI + C2 [L l + L 2]) + 1 (4.6) s3Ll L2C I +s(LI +L2)

For the differential network the equation Y dij j = ~ Ysingle holds. The circuit will resonate when Y2 becomes zero, thus when the numerator becomes zero. Using the abc formula x should be equal to 4.9.

x w2 (4.7) 2 o x L l L2C l C2 - X (CILI + C2 [L l + L2]) + 1 (4.8) C L + C (L + L ) J~(C--L--+-C--[L--+-L-]-)-2---4-L--L-C-C- l l 2 I 2 l l 2 I 2 l 2 l 2 Xl,2 ------'------'-±---'------(4.9) 2LI L 2C l C2 2LI L 2C I C2 There can be two possible resonance frequencies which is unwanted. The number of possible resonance frequencies depend on the discriminant of 4.9. The resonance frequency as function of X is visualized in figure 4.3. The variable X is given in equation 4.10. Below a certain value 2 for (CI L l + C2 [L I + L 2]) no oscillation is possible. At one value there is only one resonance frequency and from that value on there are two possible resonance frequencies. Which in practice leads to oscillations at two frequencies.

X (4.10)

Three possible situations are given in 4.11. If (ClLI + C2 [L l + L2])2 > 4L l L 2C I C2 there are two possible oscillation frequencies. In the first case the frequency difference is very large and one of the two frequencies can be filtered out. It is better to design for this case. Case 2 has only one possible frequency of oscillation, but when one of the parameters is not exactly right, which is very probable in practice, there is no oscillation, or two oscillations with almost the same frequency. 25 4.1. SECOND ORDER LC NETWORK

oE: t-<.----'L...------"'"" ~ t-< '"9 Cj '"

Figure 4.3: Wo as function of X

The oscillation frequency in case 1 seems to be an "average" of the oscillation frequency of the parallel network L2,G2 and the parallel network consisting of the parallel inductors L 1 , L2 and capacitance G1 .

o

Wo = (4.11 ) : (G1Ll + G2 [L 1 + L2])2 = 4L1L2G1G2

No Oscillation : (GILl + G2 [L 1 + L2])2 < 4L1L2G1G2

4.1.1 Quality Factor Second order LC Network

For a second order LC network it is more difficult to get a readable equation for the quality factor than it is for the first order network. Since for the first order LC network the describing polynomial is second order and for a second order network the polynomial is fourth order. But it can be quit simply seen that the quality factor for a second order network would be lower than for a first order network. Since a second order LC network has more components it has more losses. Thus the quality factor is lower for a second order network than it is for a first order network.

4.1.2 Tuning

The resonance frequency can be varied by varying G1 and G2 . The resonance frequency can be seen as a combination of the resonance frequencies of two LC networks, see 4.11. IfG1 » G2 or G2 » G1 the resonance frequency Wo becomes similar to that of a first order network, see 4.12 and 4.13. And the frequency is proportional to 4.14. CHAPTER 4. OSCILLATOR TUNING 26

1 (4.12) wio C,»C2 VL 2 C2 JL1 +L2 wol C2»c, (4.13) L j L 2C 1 1 Wo ex: ,;c; (4.14)

In the case only C 1 or C 2 is variable and neither C1 » C2 or C 2 » C 1 hold the frequency of oscillation is given by 4.15. Where the inductor Lx is given by 4.16 and Cx is either C 1 or C 2 . As can be seen the tuning range is degraded compared with a first order network. Since an factor 2 difference in Cx leads to a less than a factor V2 in frequency.

1 Wo (4.15)

: x = 1 (4.16) : x = 2

The third option is that both C 1 and C 2 are varied and neither C 1 » C2 or C2 » C 1 holds. C 1 can be expressed as C2 in that case the resonance frequency depends on 1 variable. This will not lead to a wrong calculation of the tuning range since C1 depends linear on C2 and any frequency with a combination of values of C 1 and C 2 will lie between the frequencies where both C 1 and C2 are minimal and where they are both maximal. The resonance frequency is calculated in 4.17.

1 Al L 2 L 1 + L 2 A 2 L 1L 2 C 1 aC2 + /3 1 1 Wo --+ (4.17) L 2C 2 ..!:..J.!:LC L, +L2 1

Wo JA1C1 + A 2 C2 C 1C 2

C2 (aAl + A 2 ) + A 1/3 Wo aC? + /3C2

The resonance frequency is proportional to k, which is the same as for the first order LC network.

4.1.3 Comparison of First and Second Order LC network The resonance frequency of a first order LC network is proportional to k and of a second order LC network is at best proportional to k. In practice a second order network will depend even less on the capacitances, thus the first order LC network will have a larger tuning range. A second order network can lead to two different oscillation frequencies and in practice will have oscillations at two different frequencies. A first order network can only oscillate on one frequency. The second order LC network also has a smaller quality factor than a first order network. It is preferable to have a first order LC network, a second order network also is more complex than a first order network. A second order network has a lower performance on all important parameters. 27 4.2. VARIABLE CAPACITANCE VERSUS VARIABLE INDUCTANCE

4.2 Variable Capacitance versus Variable Inductance

The oscillation frequency of a negative resistance oscillator is determined by the LC network. The LC network consists of an parallel circuit of inductor and capacitor. To vary the oscillation frequency the capacitor or the inductor varied. In practice the capacitor is most often used because it is easier and a variable capacitor has a higher quality factor than a variable inductor. Nevertheless it is possible to change the effective inductance, for example by switching between different inductors or by using current steering, see [4]. When current steering is used there are two inductors in the network and the current is divided between the two inductors. By varying the current fractions between the inductors the effective inductance is varied. Another method to tune inductances was reported in [8] and [9].

4.3 Transconductor Tuning

Transconductor tuning is described in [8] and [9]. They used a transformer parallel with a capacitor as load and tuned the phase shift ofthe transformer. The oscillation frequency was at the frequency where the total load phase shift was zero degrees. The load is shown in figure 4.4, the voltage controlled current source was used to tune the circuit. The circuit shown is only a single side of the differential LC circuit. The capacitance Ctank consists of the parasitics of the cross coupled pair and the capacitance CL consists of the parasitics of the voltage controlled current source with transconductance em. The transconductance em is changed by a current to change the oscillation frequency.

Ztan~ Z;nd ~

• L C'"n' 1 I Zg ~ Vg1 L3

L2 R L Vg2 • -- - Figure 4.4: Load of transconductor tuned VCO

The impedance Zg is used to tune the oscillator. The impedance is given in equation 4.18. The transfer function Yf2 has a phase shift of 90 degrees at the used frequency band. The impedance V g 1 Zg can then be seen as an inductance or capacitance, when em is positive or negative respectively. The impedance Zg can be seen as a component which modulates the capacitance CL , which in turn modulates the phase shift of the entire tank impedance. The transfer function is calculated later.

_1_Vg2 (4.18) em Vg1

The inductors L 1 and L2 are coupled coils and L 3 is not physically present, but together with the coupled inductors forms the model of the coupled inductors, see [14]. The inductances of the inductors are given below, where Lx is an inductance and k is the couple factor.

(4.19) (4.20) (4.21) CHAPTER 4. OSCILLATOR TUNING 28

The transfer function from Vg1 to Vg2 is given by equation 4.22 if the resistance R L is omitted. The voltage controlled current source is assumed to be added to the capacitance C L . Note that this is only valid where the transfer function has a 90 degree phase shift, if this is not the case the real part can be added to the resistance R L .

(4.22)

(4.23)

When the resistance is included the transfer function becomes equal to the one given by equation 4.24.

V w2 g2 n (4.24) Vg1 S2 + 2(wn s + w~

2 2 wn (4.25) CLLx (1 + k) 1 Lx (1 + k) ( (4.26) 2RL 2CL

The bode plots for the transfer functions ~92 with and without R L are shown in figure 4.5. 9 1 The values used for the circuit components are given in equations 4.27 to 4.29.

50i---~---~--r===:======il

iC 'C ;; -50 ~ -100

-150L-----~---~---~--- 108 10'0 10\2 1016 Frequency (md/s)

f -50 ..Q) -100 ~ Q. -150

_200L----~---'::_---'::_--- 108 10'0 1012 10'4 1016 Frequency (rad/s)

(a) Without RL (b) With RL

Figure 4.5: Bode plots for the transfer function .:...JJ..=.vV'2 9 1

0.5 (4.27) lOOfF (4.28) 120pH (4.29)

The resistance R L is used to widen the span where the transfer function has a phase shift close to ±90° . Widening this range increases the tuning range, but it deteriorates the quality factor because the slope of the phase characteristic becomes more flat as R L decreases. 29 4.3. TRANSCONDUCTOR TUNING

2 L 1 - k 8 + 2(zWnz8 + w;z Zind 48 x-- 2 .2 (4.30) 1 + k 8 + 2(pWnp8 + Wnp

2 2 wnz (4.31 ) CLLx (1 + k)

1 L x (1+k) (z -- (4.32) 2RL 2CL

2 1 wnp (4.33) CLLx

(p 1~ (4.34) 2RL C L The impedance Zind is tuned by the voltage controlled current source which modulates the ca­ pacitor CL and resistor R L . The impedance is given in equation 4.30. The impedance has two complex zeros and poles and a zero in the origin. The impedance acts like an inductance at low frequencies because of the zero in the origin. The simulated impedance of Zind and Ztank are given in figures 4.6(a) and 4.6(b). If the resis­ tance R L becomes to large, there are multiple frequencies where the phase shift of the impedance Ztank is zero degrees. The oscillator can oscillate if the phase shift is zero degrees. If there are multiple solutions there will be multiple oscillations, this is unwanted. This fact sets an upper bound for the resistance R L and thus for the quality factor.

50 =-===:::===:::::::=]------,---, 6°rr=_=~=:=RL==2=0::::O=hm:::::::;------,----.-, 1--RL=20 Ohm 40 I ~ .. ,., RL=1000hm . 50 RL=1000hm m ---RL=lkOhm -- -RL=lkOhm 40 :; 30 . ! ::Ii.. ~'" 30 20 20

Frequency (Hz) Frequency (HZ)

100,---_.-_-._-_-_-,_-._-,_-_-._-•.-~.--.-~-----_-~-----_~_--, 100,------, ...... ; .....:..... _._...._-' ... '''"' .... !"'\',':":.~.::':'.~.- ... I " ,I II \I -RL=200hm I RL=20 Ohm ,II -50 'I """ RL=100 Ohm \" -50 .. RL= 100 Ohm 1 II --- RL=l k Ohm -100L'======------'---.:....---'-----....J -100 l'::-=-=-=RL==='k=O=hm=-- ~~___I 1010 1011 1010 1011 Frequency (Hz) Frequency (Hz)

(a) Zind (b) Ztank

Figure 4.6: Simulation results of the impedances

4.3.1 Simulation Results The paper presented a veo with a wide tuning range at 26GHz. The circuit is shown in figure 4.7. The simulation results of the oscillator at 60 GHz is shown in figure 4.8(a), the voltage controlled current source used to tune the frequency is implemented with an ideal model. The tuning range is very large as can be seen. The inductance Lx is chosen to be 50pH, the coupling k was 0.5, the capacitance C L was 120fF and the resistance R L as 120, these values gave the best results. The capacitor Ctank consisted of the parasitics of the cross coupled pair, consisting of transistors M 1 and lvf2 , and a parallel capacitance of 10fF to model other parasitic effects. The capacitor C L consists of the parasitics of the buffer transistors connected to Vel and 1i~2. CHAPTER 4. OSCILLATOR TUNING 30

Vdd • • RL Lx Lx RL Vel ) ( Vc2 Lx •• Lx Vol /02

M l M 2

Figure 4.7: Circuit of transconductor tuned VCO

63.5

'N 66 "N 63 X X ~ 64 ~ 62.5 >- >- g 62 . g 62 1: 1: ~ 60 ~ 61.5 u- u- 58 61

56 60.5

54L--~-~-~-~-~-~_~_ 60 L-_____,L-_____,L-_____,~____:~____:~_____,:______,~____,J -20 -15 -10 -5 0 10 15 20 -20 -15 -10 -5 0 20 Gm(mS) Gm(mS) (a) Ideal voltage controlled current source (b) Voltage controlled current source implemented with transistors

Figure 4.8: Simulation results of the impedances

The simulation results of the oscillation frequency with the voltage controlled transconduc­ tance implemented with 65nm NMOS transistors is shown in figure 4.8(b). The tuning range is much smaller, this can partly be explained by the fact that the transconductance with the imple­ mentation with the transistors is smaller than the transconductance of the model. The biggest impact is that the transistors add capacitances between the tuning circuit and the VCO core. The simulated phase noise performance was between -8.5dBc/Hz and -81dBc/Hz. The phase noise performance is worse than described in the papers [8] and [9], probably because the quality factor was smaller at 60GHz. The parasitic capacitances of the transistors have less influence on the oscillator described in 31 4.4. VARACTORS

the papers, because the inductors and capacitors used in the paper are larger and the parasitics are relatively small. For the VCO to oscillate at 60GHz the inductance Lx was decreased to 50pH, this decreased the quality factor of the LC load. The other components had to be chosen to increase the quality factor and decrease the tuning range to get enough loop gain. The VCO topology can be used to create an oscillator with a large tuning range, but the quality factor is quite poor and this reflects on the phase noise performance.

4.4 Varactors

Varactors are very often used as variable capacitances. The CMOS implementation of a varactor is shown in figure 4.9.

Drain Gate Source Drain Gate Source

P substrate P substrate

(a) Unconnected MOS (b) Depletion region

Figure 4.9: Varactor implemented in MaS technology

The drain and source are connected and the variable capacitance is the capacitance between the gate and the substrate. The left figure shows a CMOS varactor without the depletion region and the right figure with depletion region. The depth d of this region depends on the gate drain and gate source voltages. The higher the voltage difference the deeper the depletion region is. The depletion gate substrate capacitance is inversely proportional to this depth d. The capacitance can be changed by changing the supplied voltage. The varactors are good at low frequencies, but at higher frequencies the quality factor drops and the relation g~ also decreases, leading to a smaller tuning range. Therefore it becomes more and more appealing to use other capacitance tuning mechanisms as the frequency increases. At 40GHz the simulated quality factor is approximately 10 and the simulated g~ is around 1.8 see [2]. And for 60GHz the simulated quality factor drops to 4.5 and g: drops to 1.6.

4.5 Miller Effect

The miller effect can be explained by figure 4.10. The miller effect causes the effective input capacitance to be a function of the again A. Zo is the output impedance of the amplifier. By changing the gain the input capacitance can be changed. This effect can be used to tune the LC network. Work on the Miller tuning is already been done [17] and [18]. The demonstrated VCO in the papers was implemented in a BiCMOS process. The derivation of the transfer function ~ is given in equation 4.37. Kirchhoff's current law is CHAPTER 4. OSCILLATOR TUNING 32

C

Figure 4.10: Miller circuit

used at node Va in equation 4.35.

Va (~J + (Va - Vx) sC (4.35)

ViA Va (~J + (Va - Vx)sC (4.36) AZ + sZaC a (4.37) 1 + sZaC BL¢ (4.38)

The transfer function can be written as 4.38, where B is the modulus and ¢ is the phase shift. The input capacitance can be derived by calculation the imaginary part of the input admittance. The input admittance Y; is calculated in equation 4.39 and the input capacitance C i in 4.43.

ii Y; (4.39) Vi Y; -1(V: - V:) sC (4.40) v: t a t

Yi sC (1- ~) (4.41 )

Yi jwC (1- B cos (¢) - jB sin (¢)) (4.42) 8'(Y;) C i (4.43) W

C i C (1 - B cos (¢)) (4.44)

The input capacitance can be changed by changing the gain B. When ¢ is k180° the input capacitance is maximal dependent on the gain. The input capacitance can be used to tune the LC network. The quality factor of the input capacitance can be calculate by dividing the imaginary part by the real part of the input admittance, see 4.45.

8' (Y ) Q i (4.45) ZR (Yi ) 1 - Bcos (¢) Q = (4.46) B sin (¢) The quality factor is maximal when ¢ = k180° , since the real part of the input admittance will be zero and there will be no loss, see 4.39. There is one exception, when the gain B = 1 and ¢ = k360° the quality factor will be zero since the capacitance will be zero. The ideal value for the phase shift ¢ is k180° both for the quality factor and the tuning. 33 4.5. MILLER EFFECT

4.5.1 Purely Resistive Output Impedance

In the case the output impedance Zo is pure resistive, the impedance can be replaced by Rand the transfer function is given by 4.47. In section 4.5 it was shown that the phase shift should be k180° .

VA AR+sRoC - (4.47) Vi 1 +sRC A W = (4.48) z C 1 W (4.49) p RoC

The transfer function has one zero and one pole, they are given by 4.48 and 4.49 respectively.

There are six different phase plots possible, the gain can be positive and negative and W z > wp ,

W z = wp or W z < wp ' If W z = wp the transfer function is 1 and it is no longer dependent on A. This is not practical since the tune-ability is lost. The bode plots of the other two situations and A> 0 are given in figures 4.11(a) to 4.11(d). The case where A < 0 will be studied later.

10100" I Vo 10 log Vo blVi Iv,

c/J 90°

(a) Magnitude plot (b) Magnitude plot (e) Phase plot W z < w p , A> a W z < wp , A > a W z > wp , A> a

-90'-'------

(d) Phase plot W z > wp , A > a

Figure 4.11: Bode plots for a pure resistive output

The phase never reaches 180° , only ¢ = 0° is possible. Note that a phase shift of 0° can only be achieved if the pole wp and the zero W z are much higher or much lower than the oscillation frequency woo The phase shift is 0° when the imaginary part of the transfer function is zero. When the numerator of a fraction is zero, the fraction itself is also zero, thus setting the numerator of the imaginary part to zero will lead to a phase shift of k180° . The numerator of the imaginary CHAPTER 4. OSCILLATOR TUNING 34

part divided by W is given in 4.50.

RC (1- AR) (4.50) ~ { ~ }INumerator 1 R (4.51 ) A The numerator is zero when R is given by equation 4.51. Thus the quality factor is only high for one value of A, it is preferable that the quality factor is high over the entire tuning range. If R is given by 4.51, the transfer function is equal to 1 and the Miller capacitance is zero. Thus it is not a good solution. When the gain A is negative there is no solution, since the resistance R can only be positive. A purely resistive load does not lead to a good Miller capacitor.

4.5.2 Inductive Output Impedance When using a purely resistive load it is impossible to obtain a good Q factor over a large range of gain. The problem is that with an implementation with a MOST as amplifier the phase will shift down with 90° for both the zero and the pole. Thus when the operating frequency is not much lower than both the pole or the zero frequency the phase ¢ is not equal to k180° . The exception is when the operating frequency is much higher than the pole and the zero frequencies. In practice there are many effects that change the frequency response for very high frequencies, which are not modeled in the simple models. In practice even for very high frequencies the phase shift is not equal to k180° . A solution can be to introduce a low frequency zero in the left half plane to shift the phase 90° up. This can lead to a frequency range where the phase shift is around 180° with negative gain. The zero can be created by adding an inductor to the resistive output impedance. The inductive output impedance is given in equation 4.52 and the new transfer function in 4.54.

Zo R+ sL (4.52)

V0 AZo + sZoC (4.53) Vi 1 + sZoC Vo AR + s [RC + AL] + S2 LC (4.54) Vi 1 + sRC + s2LC The zeros are given in equation 4.55 and the poles in 4.56. In practice the poles will be complex.

AR - RC+AL Wz (4.55) {------yc-AL+RC -R _ JR2C2_4LC w 2L 2LC (4.56) p { -R + JR2C2_4LC 2L 2LC The transfer function can be written as the sum of the real and imaginary parts. The phase shift will be k180° when the imaginary part is zero. The imaginary part is zero when its numerator is zero, it is enough to analyze the numerator. The numerator of the imaginary part divided by w of the transfer function is given by equation 4.57.

_L2w2AC + LA + RC (1 - AR) (4.57) ~ {~ }INumerator To find the optimal inductance and resistance values the imaginary part should be O. For the inductance this is done in equation 4.58. As can be seen the optimal inductor is dependent on the resistance R and the gain A, for now we will neglect the influence of the gain. For certain resistance values there will be zero, one or two solutions. 1 J A2 + 4w2ARC2 (1 - AR) -- ± ...:..-_------,,---,----::----'------'- (4.58) 2w2C 2w2AC :35 4.5. MILLER EFFECT

The inductance L can only be a positive and real value, therefore the discriminant of the optimal inductor in equation 4.58 should be larger than zero. This restricts the capacitance C, the capacitance should obey the restriction given by equation 4.60. o < A 2 + 4w 2ARC2 (1 - AR) (4.59) 1~ C < (4.60) 2wyR(l=AR) The optimal inductance L as function of the resistance R is shown in figure 4.12. There exist a solution when Ri < R < R"2. Note that in a practical system the inductance and the resistance will always be positive, valid values for R are in the range R E [0, R 2 ].

L

Figure 4.12: Optimal L as function of R, A < 0

When R = R] or R = R 2 equation 4.58 has only one solution. This is the case when the deter­ minant is zero. R"2 is always positive, thus there always are optimal solutions. The corresponding values for R] and R 2 are calculated below, 0 A 2 + 4w 2ARC2 (1 - AR) (4.61 ) 2 A 0 -R A+R+ 4w2C2 (4.62)

1 )1+ 3~2 R* (4.63) ] 2A 2A

A2 1 J1 + w 2 C 2 R* (4.64) 2 2A + 2A The partly inductive load gives more design freedom than the pure resistive load. Using the partly inductive load a good Q can be achieved, therefore the inductive load is preferred over the resistive load.

4.5.3 Optimal inductance as function of gain The optimal inductance L from equation 4.58 is only valid for a certain gain A. The gain is changed to change the effective Miller capacitance. Ideally the optimal inductance should not depend on the gain, this would lead to an optimal Q over the entire gain range and thus tuning range. The sensitivity of the optimal inductance with respect to the gain can be analyzed by taking the partial derivative of the inductance to the gain, this is done below, 1 J A2 + 4w2ARC2 (1 - AR) L],2 -2w--C- ± --'----2-w""7------'---- (4.65) 2 ZAC 8L ± 1 (4.66) 8A ) R1~2 + 4w 2 A (-k - A) CHAPTER 4. OSCILLATOR TUNING 36

To minimize the dependence, the partial derivative should be minimized. For the derivative to be minimal, R should be minimal and C should be minimal.

4.5.4 Optimize Tuning Range In this section the partly inductive output impedance from section 4.5.2 is used. The tuning range is discussed in section 3.3, it is given in equation 3.50 on page 18. To maximize the tuning range, g: should be maximized. The Miller capacitance is given in equation 4.44 on page 32. Using the Miller capacitance 4.67 should be maximized for the maximum tuning range, where ~ is the closed loop transfer function from equation 4.37. ' 1-~{v,'1 C+ V, A=A+ } (4.67) C- 1-~{Ys,.1 V, A=A- }

Substituting the transfer function ~ in equation 4.67 and assuming that the minimum gain (A-) is zero, gives 4.69.

AR-w2LC(I-w2LC) +w2R 2C 2 (4.68) w2R2C2 + (1 - w2LC)2 C+ A+R 1------;;--=-=: (4.69) C- 1- w2 LC

To maximize 4.69 the gain A+ needs to be negative and the resistance should be maximized. When the denominator of the fraction is zero the capacitance factor will be infinite and the tuning range will also be very large. The denominator is zero when L = )c.

4.5.5 Optimal parameters There are a number of system properties which should be kept in mind when searching for the optimal component values, such as the tuning range and the quality factor. The optimal component values are different for different system properties, to get a good overall system performance the components are usually chosen to be sub-optimal for a single property. The optimal component values for different system properties are given in table 4.1.

Optimization goal R L C ----'---- Maximize tuning Range Maximize w2C w2 L 2 J~2 2 1 ± y'A2+4w ARC2(l-AR) < -L w C Maximize quality factor 2A + 2A 2w 2C 2Aw 2C 0 Flat Q characteristic 0 - 0

Table 4.1: Optimal component values Chapter 5 veo design

In the previous chapters the theory behind voltage controlled oscillators and Miller tuning was discussed. In this chapter the theory is used to design a veo using Miller tuning. In each section the design process is described, attention is paid on the various relations between component values and system parameters. The theory described in previous sections can lead to component values that are much bigger or smaller than can be used in practice. Attention should therefore be paid that the components can be made in practice.

5.1 VCO Core Design

The circuit of the veo core is depicted in figure 5.1. The two transistors perform the function of a negative resistance as was discussed in sections 2.2.1 and 2.2.2. The Le circuit sets the oscillation frequency.

L c

Figure 5.1: veo core

When designing the veo core there are several parameters that can be chosen. These param­ eters are roughly estimated at first using simple first order models the estimated values are used for simulation and using the simulation results they are fine tuned. Several system properties are influenced by several parameters, the most important relations are summarized in table 5.1. The oscillation frequency is influenced by the width of the transistors, because the parasitic capacitances are dependent on the width and the parasitic capacitance changes the oscillation fre­ quency. The dependence of the parasitic capacitance on the biasing current is negligible compared to the dependence on the transistor width. The negative conductance is linearized with respect to the transistor width. The formula is given by 5.1, where A is a constant and can be derived from simulations the transistor width W is

37 CHAPTER 5. VCO DESIGN 38

Circuit Parameter Influence system properties Width of transistors Gneg, Wa and Tuning Bias Current G neg L R p , wa and Tuning C R p , Wa and Tuning

Table 5.1: Dependency of system properties on Circuit parameters given in Mm. The parasitic capacitance due to the cross coupled pair is linearized and given by 5.3, B is again a constant and derived from simulations. Both the constants A and B are dependent on the biasing current. A biasing current of 3mA is chosen.

Gneg,possible AW (5.1 )

Gneg ,passible ~ 0.34W(mS) (5.2)

Cpar,cross BW (5.3)

Cpar,cross ~ 1.37W(fF) (5.4)

The mlllimum negative conductance needed depends on the loss in the LC circuit and on the minimal open loop gain needed to have good start-up behavior. The loss resistance R p is given in equation 3.39 and is copied to 5.7. The capacitance in equation 5.7 is only the variable capacitance and not the parasitic capacitance since only the variable capacitance contributes to the loss resistance. The small signal open loop gain can be used since at start up the oscillation amplitude is very small, it is given by equation 2.50. For good start up behavior the minimal open loop gain 0: needs to be 3. The quality factor of the inductor is 25 and the quality factor of the capacitance is assumed to be 6.5, based on simulations.

1 C tot (5.5) wa2 L C var C tot - C par (5.6) {;f; QCQL R p (5.7) C var Qc + QL O:min IGneg,minRpl (5.8)

Gne9,min ~ JCv;r (5.9)

When choosing the parameter values these dependencies and the practical limitations should be kept in mind. The inductance L can not be larger than 220pH since the self resonance frequency would be too low, the self resonance should be about 2.5 times as large as the highest frequency. The minimum value of L is 70pH, smaller values are not possible using the library components. The parasitic capacitances due to interconnections are estimated to be llfF. The minimal needed negative conductance and the achievable negative conductance as function of the added inductance and the transistor width are given in figure 5.2(a).

The inductor L and width TV should be chosen in such a way that the achievable 'I G neg I is above the minimum IGnegl. These values are shown in figure 5.2(b) the dark area is the solution space. The choice for the inductor and transistor width restrict the choice of the variable capacitance. The minimum and maximum capacitances (C- and C+) can be calculated when the inductance and the maximum and minimum frequencies are known. The equations for capacitances where 39 5.1. VCO CORE DESIGN

Possible Land W combinations Negative Conductance 70

80 14

12 90 10 ~ B 100 ~ 6 S2. 110

120 a 60 10 130

140 40 35 30 25 20 15 10 L (pH) W(um) W(um) (a) Achievable and minimum negative conduc­ (b) Possible Land W tance

Figure 5.2: Minimum negative capacitance needed and achievable negative conductance

given in section 3.3 and are copied below, 1 C- (5.10)

C+ (5.11) (W-)2 L The minimum capacitance is the sum of all the parasitic capacitances and the minimum value of the variable capacitance. The minimal needed and achievable variable capacitances are given in figure 5.3(a). Based on simulations the achievable minimum capacitance is estimated to be 18fF.

200

150

100

50

-50

-lOa 60 10

140 40 35 30 25 L (pH) W(um) W(um)

(a) Achievable and minimum variable capaci­ (b) Possible Land W tance

Figure 5.3: Minimum negative capacitance needed and achievable negative conductance

The minimum and maximum variable capacitances are calculated by subtracting the parasitic capacitances from the total minimum and maximum capacitances, see equations 5.12 and 5.13 respectively. CHAPTER 5. VCO DESIGN 40

C;ar C- - Cpar (5.12) ctar C+ - Cpar (5.13) Ratioc cta.r (5.14) C;;ar An important parameter of a variable capacitance is the ratio of maximum and mInImUm capacitance see 5.14. In most of the practical variable capacitances this values is between 1 and 2. The needed capacitance factor is calculated and given in picture 5.3(b). The darker the area the higher the capacitance factor has to be to obtain the desired tuning range. As can be seen a large part of the solution space leads to a ratio of capacitance Ratioc that is larger then 2, thus it is hard to reach the tuning range target. The white area in the upper right corner does not contain any possible solution, since the achievable negative conductance is to low. And the white area in the lower left corner does not contain any possible solution since the minimum needed variable capacitance is lower then possible, here 18fF. Only the colored area is a achievable solution space.

5.1.1 Component Choice The chosen value for the inductor L is 90pH and the chosen transistor width is 25f-lm, because there is room for parameter mismatch, if some of the parameters are different than the chosen values still lead to a good solution. The values are used in the simulation of the YCO. After simulation the parasitic capacitances and the losses where found to be higher then expected. To decrease the loss in the LC circuit the inductor L was increased slightly to 94pH, since a higher inductor value increases the resistance of the LC circuit, see section 3.2.4. A higher resistance leads to a higher open loop gain. A larger inductor will also decrease the tuning range, but it is more important to have a stable oscillation. The width of the transistors is decreased to 22f-lm to decrease the parasitic capacitances and the tail current is increased to 3.2mA to increase the negative conductance.

5.2 Design of Miller Tuning

The circuit for the variable capacitance using the Miller effect is given shown in figure 5.4, the Miller tuning capacitor is differential. The Miller capacitances are the effective input capacitances looking into the nodes ~- and V/. These nodes are connected to the YCO core. The model of the Miller capacitance was given in section 4.5, transistors M 3 and M 4 act as the amplifiers and the capacitance used for the Miller effect are the gate drain capacitances (Cgd ). The voltage biasing at the gates of the transistors is necessary to ensure that the gate drain voltage does not become too high. The outputs are connected to Vdd using inductors, the voltages at those points can. The decouple capacitors Cc should be as large as possible to minimize their influence on the Miller capacitance and the tuning range. The transconductance A from figure 4.10 is equal to the negative of transconductance of the transistors 1'1'13 and M 4 , A = -gm. An approximation of the transconductance of a MOST transistor is given by equation 5.15, which can be found in [1]. The transconductance is dependent on the drain current flowing through the transistor. This current can be used to tune the effective input capacitance.

(5.15)

The current mirror consisting of the transistors M I and M 2 sets the current through the differential pair. By changing the current I tune the transconductance is changed which changes 41 5.2. DESIGN OF MILLER TUNING

Cc l--L...----l ~v:+ v:- ---11--...... l..------j Cc

Figure 5.4: Miller capacitance circuit

the Miller capacitance, therefore the current Itu.ne can be used to change the oscillation frequency. The current Itu.ne can be generated by a MOST, by changing the gate voltage the current through the drain will be changed. For this design it is chosen to externally generate the current to have more control over it. The resistor R tune is used to protect the circuit. When a current is applied and the voltage of the current source is slightly different from the voltage Vds over transistor M j the circuit can be damaged. The capacitor used in the current mirror is used to filter the noise from the source and the transistor M j • This will be discussed further in section 5.2.l. The resistor RL, inductor LL and the output resistance of the transistors (rds) define the output impedance Zo in figure 4.10 on page 32. Figure 5.5 shows an equivalent small signal circuit of the output admittance.

Figure 5.5: Output impedance

The equivalent output impedance is given in equation 5.17. CHAPTER 5. VCO DESIGN 42

1 1 1 -+ (5.16) Zo rds RL + SLL RL + SLL ZOlrdo=-L (5.17) " 9ds 1 + Rgds + sgdsLL The output impedance from equation 5.17 is substituted in the transfer function for the miller capacitance given by equation 4.53. The transconductance A is substituted by -gm, which is the transconductance of the transistor. This leads to the transfer function given by 5.18.

gmRL + s (gmLL - RLCgd ) - s2 LLCgd (5.18) 1 + RLgds + s (RLCgd + LLgds) + s2 LLCgd The transfer function is slightly different than the transfer function given by equation 4.53 in section 4.5.2, because we didn't include the output impedance rds of the transistor in that section. The theory and the optimal values found in section 4.5.2 still hold with some modifications. The optimal values for the inductance was calculated in section 4.5.2 by setting the numerator of the imaginary part of the transfer function to zero. This approach still holds, the new criterion is given by equation 5.19.

o (5.19) Solving the criterion gives the optimal values for the inductor LL, the solutions are given in equation 5.20. Both the criterion and the optimal inductance value are quite similar to those found in section 4.5.2. Only the transconductance of the amplifier changed, this is explicable, since the transconductance can be seen to be parallel on the output admittance gds'

gm Vgm2 - 4RLw2C;d (gm + 9ds) (1 + RL [gm + gds]) LLl.2 -::---;::-=:---";---....,- ± (5.20) 2w2Cgd (gm + 9ds) 2w2Cgd (gm + 9ds)

The possible values for R L are calculated in the same way as was done in section 4.5.2. The maximum and minimum capacitances can be calculated by setting the determinant ofequation 5.20 to zero, this leads to resistances given by 5.21 and 5.22. The minimum resistance value is given by Rj and the maximum value by Ri.

1 V1+~ R* (5.21 ) 1 2 (gm + 9ds) 2 (gm + gds) 1 II + J~~ R* _ + V gd (5.22) 2 2 (gm + 9ds) 2 (gm + gds)

5.2.1 Effects of Noise in Current Mirror

The current provided to the differential pair M 3 and 1114 by the current mirror. Influences the Miller capacitance by influencing the transistor transconductance. A practical current mirror im­ plementation introduces noise to the mirrored current, this noise modulates the Miller capacitance. A simplified model of the miller capacitance was given by equation 4.44, the equation is copied in 5.23.

C 1, wC(l- Bcos(

C 1, wC (1 + B) (5.24) 43 5.2. DESIGN OF MILLER TUNING

Assuming that the inductor and resistance values are chosen optimally, the phase shift ¢ is 0 180 • With this assumption the effective Miller capacitance can be approached by 5.24. The gain B is proportional to the square root of the tail current Iss, see 5.25.

C; ex: J Itune (5.25) Iss It + In (5.26)

The tune current consists of an wanted DC It current and a noise component In. The noise current can modulate the Miller capacitance and thus the oscillation frequency. The unwanted change in frequency variation due to noise can be seen as phase noise, the tail current noise deteriorates the phase noise performance. Even the low frequency noise components influence the phase noise performance. For good phase noise performance the noise component In should be minimized. The current biasing circuit is copied and the noise sources are added in figure 5.6. The noise sources i NM1 and i N M2 represent the noise generated by the transistors M I and M 2 respectively. The power densities of a 1Hz band are given by equations 5.27 and 5.28, the noise density is given 2 in A / Hz. The noise densities can be found in [16].

Figure 5.6: Output impedance

-'2-- Kgmi 2NM1 4kTi9mI + Cox WILd (5.27) 2 -'2-- Kgm 2NM2 4kTi9m2 (5.28) + Cox w2l 2f 2 VNR 4kTRtune (5.29)

The voltage noise source VNR is the noise produced by the biasing resistor Rtune . The spectral 2 density is given by 5.29, the spectral density is expressed in V / H z. To analyze the influence of the noise sources on the phase noise they should be moved to the output node of the current mirror. Since all the noise sources are uncorrelated they can be analyzed individually and the results can be added using superposition. The noise current INM2 is already at the output. We start with moving the noise current of transistor AI]. The small CHAPTER 5. VCO DESIGN 44

Figure 5.7: Small signal circuit

signal representation of the circuit is given in figure 5.7, where Zo is the output impedance seen at the drain of ]1',{2' The circuit depicted in figure 5.8 shows the simplified small signal circuit only with the noise source IN M 1. The current noise source of transistor Af1 is transferred to a voltage noise source at node Va. To transfer the source, the transfer function is used.

1 gm,

Figure 5.8: Simplified small signal circuit

To calculate the transfer function, the nodal equations are written in matrix form, see 5.32.

1 Yo (5.30) Zo

Cv Cn + Cgs1 + Cgs2 + Cgd2 (5.31 )

-I~Ml [ gml + gdsl + S (Cv ) -SCgd2 ] ~ (5.32) [ gm2 - SCgd2 Yo + SCgd2 ][ ]

The transfer function is calculated from the nodal equations and is given in 5.33.

(5.33)

The added capacitor Cn is chosen much larger than any of the gate capacitances of the tran­ sistors. Using this fact the transfer function is simplified and given by equation 5.34. The zero and pole frequencies are given by equation 5.35 to 5.37 respectively, with the assumption that

W p2 » W p l which holds since Cn » Cgd2 . 45 5.2. DESIGN OF MILLER TUNING

o V I (5.34) I NM1 C"»C,,, Yo (gml + gdsd + sYoCn + S2Cgd2 Cn gm2 (5.35) C gd2 gml + gdsl Wpl (5.36) Cn Yo W p 2 (5.37) C gd2 The first pole of the system has a much lower frequency than the other pole and zero, the circuit acts as a low pass filter. This should be the case since the tune current also has a DC component. The dominant pole can be influenced using the added capacitor Cn, to filter out more of the noise the capacitance should be increased. On the other hand lowering the frequency of the dominant pole also filters out the high frequency signals in the tuning, the capacitor will limit the bit rate. The influence of the noise generated by the tuning resistor R tune can now be easily calculated by transforming the voltage source by a Norton equivalent current source, since the output resistance of the current source is quite large the influence of the thermal noise produced by the resistor can be neglected. The simulation of the phase noise of the complete system as function of the capacitance Cn is given in figure 5.9. As can be seen the phase noise performance becomes better when the capacitance Cn gets larger. In practice it is impossible to fit a very big capacitor in the layout, since there is not enough room.

Phase Noise vs C n

-86.5

-87 N ~ ~ -87.5 Z c. -88

-88.5

-89 '---~~~~-'-'--~~~~...... L__~~~.l..-~~~_..J 10-'2 10-11 10-10 10-9 10-8 en (F)

Figure 5.9: Phase noise versus capacitance

The noise contribution of the current mirror can also be decreased by increasing the width and the length, see equations 5.27 and 5.28. The current flowing through a transistor when it is working in the saturation region is given by 5.38, see [1]. To retain a constant current the fraction r should be kept constant. The current buffer is used to tune the Miller capacitance and the maximum current is 20mA which is high. To obtain this current the width W is much larger than the length L. CHAPTER 5. VCO DESIGN 46

W 2 K 2L (Vgs - Vi) (5.38)

To decrease the noise generated by the current mirror the gate length is increased and the ratio ! is kept constant. The transistors are made as large as possible, keeping in mind the layout of the circuit.

Component Choice The optimal values for the resistance R and inductance L were given in table 4.1 in section 4.5.5. In the implementation the load of the amplifier is different because of the finite output impedance of the transistors. The new model was already described in section 5.2, the updated ideal parameters are given in table 5.2.

I Optimization goal ----!..- ---.!.- TIming Range Maximal w2C d w2L gm Quality Factor )1+ J~~ 2w2C gd (gm+gds) 0 1 ~ gd 2 -4RLW2C~d(gm+gds < - 2(gm+gds) 2(gm+gds) ± jgm )(l+RL [gm+gdsJ) 2w C d(gm+gd.,) Flat Q characteristic 0 - 0

Table 5.2: Optimal component values

Parameter Typical value Maximal value Cgd 20fF - gm 24mS - gds 3mS - RL (for good Q) - 42.3f2 L L (practical limit) - 1l0pH

Table 5.3: Typical and maximal parameter values

In table 5.3 typical values for various circuit parameters are given, note that the first three parameters are dependent on the size of the transistors but the values can be useful to estimate boundaries for other parameters. The upper limit for the resistor RL was calculated using equa­ tion 5.22 and the upper limit for the inductor LL is due to practical limitations. The combination of the two inductors LL is implemented as a single differential inductor, this differential inductor can not be larger than 220pH since the resonance frequency of the inductor would become to low. The width W of the transistors is chosen to be as large as possible to increase the tuning range, since wider transistors have higher gain. The upper bound of the transistor width is determined by the gate drain capacitance Cgd . When this capacitance becomes too large the solutions for the optimal inductor is no longer valid, see section 4.5.2. From simulations a width of 45.9J.Lm was extracted.

For the largest gain and thus tuning range the resistance RL should be large and the inductor LL should be equal to W2~9d' The gate drain capacitance is very small in practice, about 201F. Using this value the optimal inductor becomes very large, about 340pH which is larger than the upper bound. When the quality factor is taken into account the upper limit of the resistance is bounded and the gate drain capacitance should be as low as possible. A low resistance value is also preferred to get a flat Q characteristic, thus a good Q over a large gain range. 47 5.3. OUTPUT BUFFER

A small resistance is preferable because of the DC biasing. The DC voltage at the output node is given by equation 5.39. The current I tune is changed to tune the Miller capacitance, this current is maximally 20mA. A smaller load resistance RL leads to a smaller change in DC voltage, for a stable biasing the resistor needs to be as small as possible.

tune v:dd - RL-I - (5.39) 2

To increase the gain the largest feasible inductor is used, which is about 10SpH. A large induc­ tor decreases the needed resistor which is preferable for the DC voltages. Using the relationship between the optimal inductance and resistance a resistance of 40n is chosen. The chosen values are summarized in table 5.4.

Parameter Chosen value W 45.9/'lm R 40n L 10SpH

Table 5.4: Chosen parameter values

5.3 Output Buffer

It is impossible to directly measure at the output of the VCO core, because the core is very sensitive to changes in capacitance and resistance. To make measurements possible an output buffer is added. The chosen circuit is shown in figure 5.10. The buffer is a differential amplifier with a source resistance instead of current source. The input at the gate is DC decoupled using capacitance Ce , the capacitor is custom made because the capacitances in the library had larger parasitic capacitances to ground. The capacitor is described in section 5.4.

Vdd

Vg

Ro

V+ 0 v-o

M 1 f--"-----11-v:+ v:- ----1 f--.....J....---1 Ce Ce

Figure 5.10: Output buffer

In the specifications it was specified that the output power should be higher than -13dBm when measured with a differential lOOn probe. The voltage top of the signal is calculated in equation 5.44. CHAPTER 5. VCO DESIGN 48

dHrn Pmw 10--ru (5.40) Vr~s Pw (5.41 ) Rprobe Pm\V Vrms --R1000 probe (5.42)

vtop hvrms (5.43) vtop ;:::; 100mV (5.44)

The peak voltage has to be approximately 100mV and the output voltage amplitude of the VCO core is about 50amV, the buffer may attenuate the signal instead of amplify the signal. It is desirable to have small transistors, because the input impedance of the transistors is directly seen by the tank. Small transistors have small input capacitances and hence they introduce less parasitic capacitances in the VCO core. The gain of the buffer is calculated below, the common connection at the sources is virtual ground. The small signal circuit is depicted in figure 5.11. The resistances Rprobe represent the probes and are 50n.

V+ y- If

_1_ }--+-..y+ ~---+---{ Rprobe 9rl.<: ,

Figure 5.11: Output buffer small signal circuit

The differential gain is given by equation 5.48 where the influence of the probe is taken into account.

I+ gm - sCgd a gds + L + SCgd a 0 I- a gm - SCgd a ~o gd y+ 0 gds + + sC , I+ a a 1 a 0 - Rprobe v-, I- 1 y+ 1 0 a a a - Rprobe [y-0 f45 Vi 1 -1 a a o Vo a a 1 -1

10 1: - 1;; (5.46) RoRprobe R v (5.47) R o + Rprobe Vo -gmRv + sRvCgd - (5.48) Vi 1 + Rvgds + SRvCgd The zero and pole have a very high frequency, higher than the band of interest (58GHz-64GHz) therefore the gain can be approximated by taking the DC gain. The zero and pole frequencies are 49 5.3. OUTPUT BUFFER

calculated in 5.55 and 5.56 respectively and the DC gain is given by equation 5.57.

gm Wz (5.49) Cgd 1 + Rogds wp (5.50) RoCgd gm ;:::; 20mB (5.51 ) gds ;:::; 3mB (5.52) Cgd ;:::; 15fF (5.53) R o 550 (5.54) fz ;:::; 212GHz (5.55) fp ;:::; -225GHz (5.56) gmR Vol v (5.57) v:, w=Oradj s 1 + Rvgds

5.3.1 Component Choice

The output is measured using a 1000 terminated differential probe, single ended the input impedance of the probe is 500. For small reflection thus a higher efficiency, the single ended output impedance of the buffer should be 500, see [5]. The single ended output impedance of the buffer can be calculated using equation 5.45, the equation for the output impedance is given by 5.58.

Zout V+I (5.58) It v/=o Ro Zout (5.59) 1 + Rogds + sRoCgd

The influence of the gate drain capacitance Cgd can be neglected. The output impedance of the buffer is a little bit smaller than the resistance R o . The output impedance of the transistor is larger than the resistance R o and has less influence, R o is chosen to be 550. The gain of the buffer was approximated by equation 5.57. The input signal amplitude is about 250mV and the output amplitude is 50mV, the gain needs to be approximately 0.2 see 5.61.

gmRv Vol (5.60) v:., w=O 1 + Rvgds V 0.05 o -- (5.61 ) V; 0.25

Using relation 5.62 the desired transconductance gm can be calculated, this is done in 5.69. The needed transconductance is quite small, thus a small transistor can be used. Note that the decouple capacitor Cc also decreases the input power therefore the transconductance should be CHAPTER 5. VCO DESIGN 50 larger than the minimum value. gm gds ;:::: - (5.62) 6 RoRprobe R v (5.63) R o + Rprobe gmRv Vol (5.64) v:1 w=o 1 + Rvgds H vol (5.65) v:1 w=o gmRv H (5.66) 1 + gm~v H gm (5.67) ~Rv R v ;:::: 26.2~ (5.68) gm ;:::: 9.2mS (5.69)

The gate voltage is externally biased, if this wasn't the case the DC voltage at the gates would be the same as the DC voltage of the VCO core which is close to Vdd . For the transistors to operate in the saturation region equation 5.70 should hold. If the DC input voltage is Vdd there isn't much headroom left for the output voltage.

Vax > Vix - Vi (5.70) Vi ;:::: 0.34V (5.71 )

The single ended input voltage amplitude is 250mV and the single ended output amplitude is approximately 50mV. The transistor should operate in the saturation region. The minimum DC voltage different between the output and the input is given in equation 5.75.

X x Va > Vi - Vi (5.72) Voxl DC - VoxlAmplitude > VixlDC + VixlAmplitude - Vi (5.73) x Voxl DC - VixlDC > Vox IAmplitude + Vi IAmplitude - Vi (5.74) Voxl DC - VixiDc > -0.04V (5.75) The DC output voltage should be low enough to allow the output voltage to swing to the maximal amplitude, which is 50mV. The DC biasing current is specified in equation 5.76. To decrease the DC current the output voltage should be chosen close to Vdd.

(5.76)

The input DC voltage is chosen to be 0.95V and the output DC voltage as 1.00V. The DC current is 3.6mA per side. Using this DC current, the gate and drain bias points and the calculated gm the transistor width is chosen to be 20p,m and the gate source voltage is chosen to be 0.74V. This gives a source voltage of 0.21V. The source voltage is given by 5.77. Twice the DC current is taken since the currents from the "+" and the"-" side flow through the resistor R s . Using the source voltage of 0.21V the source resistance R s approximately needs to be 30~.

(5.77) 51 5.4. FRINGE CAPACITANCE

5.4 Fringe Capacitance

The DC decouple capacitors Cc used at the gates of the Miller tuning and output buffers are directly connected to the YCO core. A practical capacitor always has parasitic capacitances to ground, these should be as low as possible since they lower the oscillation frequency of the YCO. The parasitic capacitances have a negative influence on the tuning range of the oscillator.

(a) Finger structure (b) Capacitor model

Figure 5.12: Fringe capacitor

A fringe capacitance consist of parallel metal lines see figure 5.12(a) called fingers. The wanted capacitance Cf is given by 5.78, CL is the capacitance per unit length. The capacitance per unit length depends on the metal height h, since the height is fixed for a certain process the capacitance per unit length is constant and is different for different metal layers.

(5.78)

(5.79)

The parasitic capacitance is given by 5.79. The left part of the right hand side of the equation is the parallel plate capacitance between the finger and ground. The right part is the fringing capacitance of the perimeter. The wanted capacitance between the fingers should be maximized and the parasitic capacitance to ground should be minimized. To accomplish this the line width W should be minimized and the distance df between the fingers should be minimized. The height dh between the fingers and the substrate should be maximized. The capacitors used in the library have a multi finger structure. The library capacitors consist of a finger structure in metals one to five, the parasitic capacitance are between the metal 1 layer and the ground, this leads to a large parasitic capacitances since dh is small. To overcome this problem custom capacitances are made consisting of metal layers five to seven. The distance from the substrate to metal five is much larger than the distance from substrate to metal one, the parasitic capacitances are smaller. When multiple layers of metal are used for the fingers and the metals lay exactly on top of each other only the lowest metal layer contribute to the parasitic capacitance. The minimal width Wand finger distance df of metal 5 is larger than for metal 1. To make a fare comparison between the different solutions the wanted parasitic capacitance Cpor divided by the wanted capacitance Cf should be used. This is done in equation 5.81, this fraction should be as low as possible. The minimum width and minimum finger distances for the metal fingers are chosen to maximize Cf' in practice these minimum sizes are the same. CHAPTER 5. VCO DESIGN 52

WL f""""d";" + 2 (W + L) Cper (5.80) CL.b... df EvrL+2(W+L)Cper " (5.81)

In table 5.5 the fraction from equation 5.81 is summarized for different metal layers, as can be seen the higher the metal layer the lower the fraction becomes. To optimize the capacitor the highest metal layer should be used. \\Then using only one metal layer the area needed for large capacitances is large, when multiple metal layers are used the needed area for the same capacitance is decreased. In the table the needed width of a capacitor of lOOfF and length lOJ'Lm is given. The width needed for a capacitor consisting of only metal 6 or 7 is larger than the width needed for the other metal layers, this is because the minimum width and distance of metal 6 and 7 are larger than for the other metal layers.

L/1'O'l"> Metal layer 0, W (J'Lm) Metal I 23.2% 10.2 Metal 2 21.8% 14.0 Metal 3 18.6% 13.7 Metal 4 14.4% 12.9 Metal 5 14.3% 11.6 Metal 6 15.7% 27.3 Metal 7 12.7% 25.5 Metals I to 5 5.0% 3.1 Metals 5 to 7 3.7% 9.6

Table 5.5: Capacitance values

It is better to use multiple metal layers to increase the capacitance per area and to decrease the parasitics per wanted capacitance as can be seen in the table. For the decouple capacitors used at the gates of the transistors of the output buffer and the tuning circuit metals 5 to 7 are used to minimize the parasitic capacitances to ground. The capacitors used to filter out unwanted disturbances on the supply lines are standard library components using metals 1 to 5, because it has the highest capacitance per area and the capacitance to the grounded substrate can be used to decrease the disturbances. Note that models used in this section are simplified and do not take the capacitance between different fingers on different metal layers into account. Chapter 6

Layout

The schematic does not capture the parasitic effects, because the physical connections are not known. The capacitances between components and interconnects can only be estimated after the whole chip is layed-out. During the layout process, the schematic should be altered to include the parasitic effects and the circuit parameters should be fine tuned in an iterative process to obtain the desired specifications. The automatic extraction available only extracts parasitic capacitances and resistances, this is good enough for short wide lines, but not for longer interconnects. For smaller and longer interconnects the line inductance is no longer negligible, the model for small and long interconnects is given in section 6.1. The layout of analog circuits is more complicated than for digital circuit, despite the fact that digital designs have many more transistors, because digital circuits are less sensitive to noise and phase shifts and digital circuits operate on much lower frequencies. High frequency analog circuits are very sensitive to parasitic capacitances because they influence the behavior of the circuit. There are no clear rules for analog layout only rules of thumb, that's why computers can not layout analog circuits. In this chapter the layout of the various sub circuits are discussed including the parasitic extraction of long interconnects.

6.1 Impact Of Interconnects On Circuit

The long connections between various components consist of a metal 7 signal line and underneath a ground" return" line in metal 1. The height between the signal line and return line is maximized to minimize the parasitic capacitances. The interconnect can be modeled as a microstrip transmission line, see [15] for an in-depth analysis of transmission lines. The interconnects are all relative short in comparison with the wavelength which is approximately 3mm on chip. If the transmission line is shorter than 1/10 of the wavelength it can be approximated with a single RLGC section, see figure 6.1. A 7f model is used, the total capacitance and conductance is divided by two and placed at the beginning and end of the line section.

R L

Figure 6.1: Line RLGC 7f model

The conductance between metal 7 and metal 1 is very small, the conductance G is neglected in the model.

53 CHAPTER 6. LAYOUT 54

The total capacitance between the signal line and the ground plane can be divided in two components, a parallel plate capacitance and a fringe capacitance. The physical model is shown in figure 6.2(a). Parameter Len is used for the length of the line and L for the total inductance of the line.

M7

M1

(a) Physical parameters (b) Capacitances

Figure 6.2: Line model

The equation for the parallel plate capacitance is given in 6.1. The variables used are the same as in figure 6.2.

LenW Cpl ate fOfr --- (6.1) h Cjringe 2(Len + W)Cper (6.2)

The equation for the fringe capacitance is given in 6.2. The capacitance Cper is the unit capacitance of the perimeter per J.lm. The unit perimeter capacitance is multiplied by the perimeter which leads to the total fringe capacitance. The resistive loss in the model is modeled by R. The resistance is calculated by using the expression 6.3. The resistance per square (Rsq ) is simply multiplied by the number of squares in the signal line.

R Len R sq W (6.3)

The modeled inductance is slightly more difficult to calculate. The velocity of propagation of a signal in a lossless transmission line is given by equation 6.4, where LL and CL are the inductance and capacitance per unit length respectively.

1 (6.4)

The velocity can also be written as,

1 (6.5)

Using equation for the speed of light in vacuum and the fact that the relative permeability on chip is one, the velocity simplifies to equation 6.6, where c is the speed of light.

(6.6) 55 6.2. VCO CORE

Equation equations 6.4 and 6.6 leads to an expression for the inductance per unit length in equation 6.7.

(6.7)

Substituting the inductance and capacitance per unit length in 6.7 gives rice to the equation for the total inductance of the line, see 6.10. Note that c is used for the speed of light and capital C is used for the total line capacitance. L LL (6.8) Len C CL (6.9) Len L Er Len2 (6.10) c2 C 6.2 VCO Core

The layout of the VCO core is shown in figure 6.3, the cross coupled pair depicted in figure 5.1, consists of the transistors marked 1 and 2. The transistors marked with 3 and 4 make up the current mirror which sets the bias current.

Figure 6.3: Core layout

The inductor is marked with C. The lined A and B form the interconnects from the cross coupled pair to the inductor and Miller capacitance. The lines are relatively long and should be replaced with the simple pi model discussed in section 6.1. Figure 6.4 shows the cross coupled pair with interconnects in more detail. The length of the most important interconnects is given in table 6.1, the component values of equivalent model are also given. The model was described in section 6.1. The width of all the interconnects is 4.4p,m which is the same width as lines of the inductor. The lines are chosen this width to lower the loss resistance in the VCO core, wider lines lead to CHAPTER 6. LAYOUT 56

Figure 6.4: Zoomed in core layout

Interconnect Length (lIm) C (iF) L (pH) R (Sl) Ml Drain to J 11.6 1.61 3.44 0.03 Ml Drain to C- 19.2 2.46 6.17 0.05 Ml Gate to J+ 14.0 1.88 4.29 0.03 M2 Drain to J+ 13.3 1.81 4.06 0.03 M2 Drain to C+ 18.5 2.38 5.92 0.04 M2 Gate to J- 19.1 2.45 6.13 0.05

Table 6.1: Estimated lines smaller resistance. A disadvantage of wide lines is that the parasitic capacitances to ground are increased. The lines from the gates of the transistors to the connections of the inductor cross each other, the line from the gate of transistor 2 under crosses the other line in metal six. The resistance value of metal 6 is equal to metal 7 and a lot of low ohmic vias are used, therefore the extra resistance can be neglected. The line has a slightly higher capacitance to ground and a lower inductance. These effects are taken into account in table 6.1. The crossing also introduces a parasitic capacitance between the two sides of the differential VCO core. The extra parasitic capacitance is approximately 3.41P, this capacitance is parallel to the inductor and variable capacitance and influences the oscillation frequency and tuning range.

6.3 Miller Tuning

The layout of the Miller circuit is shown in figure 6.5. The transistors labeled 1 to 4 are the same transistors as in the circuit given by figure 5.4. The current mirror transistors 1 and 2 are made very big to decrease the noise, see section 5.2.1. The capacitor labeled "c" is the capacitor Cn which is used to decrease the noise contribution of transistor 1. The capacitor is made as large as possible to fit into the layout. The capacitors"A" are the decouple capacitances, they are custom made and described in more detail in section 7.1. The resistors at "B" are the load resistors R L . Next to the resistors R L a couple of dummy resistors are placed. Dummy resistors are used to increase the accuracy of the wanted resistors. When the resistors are processed the first resistor in a row has more deviation than the one next to it. The outer resistors are dummies and thus may have a large deviation. 57 6.4. OUTPUT BUFFER

Figure 6.,5: Complete Miller circuit layout

Longer resistors have smaller deviations from their nominal resistance value than shorter ones. There are two long interconnects, the lines from the decouple capacitors and the transistors M3 and AI4. Since they are long it is better to extract them manually. The length and the model parameters of the extracted lines are given in table 6.2. The lines are identical and their width is 3f..Lm. The width is smaller then the width of the lines used in the core, because the parasitic capacitance has to be reduced to a minimum. The biasing of the Miller tuning is less sensitive to the resistive losses in the lines then the core is, since losses in the core deteriorate the open loop gain which has to be compensated with a larger negative conductance.

Interconnect Length (f..Lm) Decouple capacitor to transistor 11.4

Table 6.2: Estimated line

6.4 Output Buffer

The output buffer is cut into two pieces, this way the output buffers could be placed closer to the output of the VCO core to decrease the extra interconnecting lines. The complete output buffer is shown in figure 6.6. The transistors 1 and 2 correspond with the transistors in the buffer circuit depicted in fig­ ure 5.10. The output buffer is split into two parts as was said before, one part is placed around transistor 1 and the other part around transistor 2. The resistance connected to the sources of the transistors R s is placed between the two sides of the output buffer. The DC decouple capacitances Cc are placed directly on the output of the VCO core, this way there are no long interconnections necessary.

6.5 Complete VCO

In figure 6.7 the entire layout of the VCO is shown. The big inductor is part of the tuning circuit and the small inductor is part of the VCO core. The output of the output buffers is connected to the right side bondpads, the output is connected using transmission lines with a characteristic impedance (Zo) of 500 to minimize their influence on the matching, since the input of the probes and the output of the buffers are approximately 500. CHAPTER 6. LAYOUT 58

Figure 6.6: Entire output buffer

Figure 6.7: Complete VCO layout

The Vdd of the tuning circuit is separated from the Vdd of the VCO core and output buffers. This gives more flexibility, because the two sub-circuits can work with different supply voltages if necessary. The other advantage is that the coupling between the circuits is decreased, if there exists a small RF disturbance on the supply of the VCO core it will not be introduced in the tuning sub-circuit. The darker squares near the bondpads are decouple capacitances and are used to stabilize the biasing and supply voltages. The capacitances act as a low pass filter and the higher frequency disturbances are filtered out. The very small blue diodes labeled"a" are ESD protection diodes. They protect the circuit against static discharges outside the circuit for example in the probes. The ESD protection diodes near the biasing bondpads protect the circuit during manufacturing. During manufacturing charge can build up on long lines and when these lines are connected to the transistors the transistors can be destroyed by the build up charge. The ESD protection discharge the lines safely to the substrate. Chapter 7

Simulations

In this section the simulation results of the designed sub-circuits and of the complete VCO are analyzed. The simulation of the circuits with and without parasitics are compared. In section 7.4.1 the simulated system parameters and the target specifications are compared.

7.1 Decouple Capacitance

The DC decouple capacitor Ce in the circuit depicted in figure 5.4 is connected between the VCO core and the Miller tuning. This capacitor is in series with the Miller capacitance, the substitute capacitor C v is given by equation 7.1. The tuning range is maximized by minimizing the influence of the capacitor Ce , thus by maximizing the capacitor value.

CMil/erCe (7.1 ) CMiller + Ce

For the analysis of the used multi finger capacitors see section 5.4. To minimize the parasitics metal layers 5 to 7 are used. The metal width and spacing are minimal to maximize the capacitance and minimize the area.

The Miller decouple capacitance Ce is calculated using the model from section 5.4, simulated using Momentum and simulated using the RC extraction of Cadance, the results are depicted in figure 7.1(a) and the percentage of parasitic capacitance is depicted in figure 7.1(b). The simulation results for the buffer decouple capacitance are given in figures 7.1(c) and 7.1(d). Only the capacitance simulated by Momentum can predict resonance behavior, because the both the model and the RC extraction do not take the inductance of the fingers into account. The simulated capacitance for low frequencies are constant. The modeled capacitance is approximately the same as the extracted capacitance of Cadance. The capacitance simulated is lower than was predicted by the model and the RC extraction. The decouple capacitance is composed of multiple metal layers stacked on each other and act more as a parallel plate capacitor than as separate fringe capacitors. The model and extractor might overestimate the fringing. The capacitance value will probably be in the vicinity of the Momentum simulation result. The differences between the results of the percentage of parasitic versus wanted decouple ca­ pacitance is bigger. It seems that the model overestimates the parasitic capacitances to substrate. Again it can be argued that the modeled parasitic capacitance is larger than it will be in practice since the fringing of the parasitic capacitances taken into account is too high. Because there are many fingers next to each other the capacitance to substrate will act more as a parallel plate capacitor than as a combination of lines with a high fringe capacitance.

59 CHAPTER 7. SIMULATIONS 60

550 --- Cadance Extraction ,I --- Cadance Extraction 500 ~ Momentum SimulatIon : 4.5 -.-Momentum Simulation -Model -Model 450

400 3.5 350 l 3 jL300 S2" 2.5 u"'" 250 ~ -_.- .------U 200 -- .-J 1.5 150

100 50 0.5o'-----~~~~ ~_~-....J____"'''''"_'______J o 9 8 9 11 10' 10 10 10 10'0 10 I (Hz) I (Hz) (a) Simulated Miller capacitance (b) Percentage of parasitic Miller capacitance

4.5,--,------,-----,-----,__,------,-----,-----,__,-----,-----,-----,-----.------,

----_._.~-~--~------_._._---

25 3.5

_ 3 ii:' .. e 24 U ~" 8. 2.5 U 23

22 fr-~~----'''--"",,-''''' --- Cadance Extraction 1.5 --- Cadance Extraction -.-Momentum Simulation - Momentum Simulation 21l\:-=-;M=:od=:e:=1==;:=='---.._~"'""'""'-;-;,-----'------''---~"'""'""'-;-;,--'r ,l'=-=-;M=od=e=1====='--.._"""-'-~,-----'------'---'---c....lif....L,.J 8 8 ,~ ,~ ,~o 10" 10 10 10'0 10" I(Hz) I (Hz)

(c) Simulated buffer capacitance (d) Percentage of buffer parasitic capacitance

Figure 7.1: Buffer capacitance

7.2 Negative Resistance

The simulated negative conductance Gneg as function of the current Iss for various transistor widths are shown in figure 7.2(a). The width used in the design is 22J.Lm and the tail current is 3.2mA. The negative conductance increases when the width or the tail current increase, which was predicted in section 2.2.1 and 2.2.2. In figure 7.2(b) the simulated negative conductance, the small signal model and large signal models are plotted with a transistor width of 22J.Lm. The parameter K is fitted since this parameter is only valid for the simple transistor model. As can be seen both the small and large signal models are accurate for a small Iss current, for larger signals the large signal model is better but still has an error. This error exists because the used transistor model in the small and large negative conductance model is only a simplified model. Increasing the transistor width also increases the parasitic capacitance which is shown in fig­ ure 7.3(a), this can be explained by the fact that wider transistors have a larger gate area and thus a larger capacitance. The parasitic capacitance depends almost linear on the width of the transistors and the influence of the tail current Iss is small, as can be seen in the figures 7.3(a) and 7.3(b), thus the assumptions made in section 5.1 are valid. 61 7.2. NEGATIVE RESISTANCE

-1 r--~------~--~-~-~-~-- -2,-~-~-~-'-~---;::======;l -W=10~m --Simulated --W=22~m -- - Small signal roodel ...... large signal rncxiel -'-W=40~m

-4 -4 Cil .5-.. -5 -, ~ -6 ...... CJ -7

-8 -9 , -. J-8~"~----"-~'. ."., -10 -~-~-~~5---'-~-~--~-~--10 1 1 2 345 6 13 10 I•• (rnA) I., (mA)

(a) Negative conductance (b) Simulated Gneg and modeled Gneg

Figure 7.2: Simulation of the cross coupled transistor pair

55 55r;====:::::;-~--~-~--~-,

'---IM =1 mA I 50 50 __ l =5mA ss .... '-'" 45 45 Iss=10 rnA

40 40 iL :=. 35 :=.iL 35

UX- 3D

25 25

20 20

15

10 1 5 6 10 15 20 30 35 40 I.. (rnA)

(a) Parasitic capacitance versus 1s8 (b) Parasitic capacitance versus W

Figure 7.3: Parasitic capacitance

40,-~-r-~-_-_-~-~_~_--,-_...,

o 5.8

5.7

5.• 20 55

5_40L~~~~----:--~-~'Q---:':12--,:'c4--,e:-.---:,e:-.---:2()

11une(mA)

(a) Miller Capacitance (b) Quality factor

Figure 7.4: Simulation results CHAPTER 7. SIMULATIONS 62

7.3 Miller Tuning

The simulated Miller capacitance as function of the current injected into the current mirror is depicted in figure 7.4(a). The minimum and maximum capacitances are given in 7.2 and 7.3 respectively and the capacitance factor is given in 7.4.

c­ 18.549(fF) (7.2) c+ 38.571(fF) (7.3) c+ c- 2.08 (7.4) The quality factor of the tuning range is shown in figure 7.4(b), the minimum quality factor is 5.44 which is a little bit lower than was expected.

7.3.1 LC tuning circuit The LC tuning circuit consists of the Miller capacitance and the core inductor which is 94pH. The quality factor of the coil was simulated to be approximately 30, it will probably be lower in practice. The minimum quality factor of the LC circuit is approximately 4.6, see section 3.2.4 for the equation for the LC quality factor.

340 ,___----.------,------,-~----r--,---,___-,______,_-___,

330

E os:; ;0. 290

280

270

260

2500~L------:----'-4-----:-6----'------:"0:-----'-'2--'-'-:-4--':-6--:':'8:------:'20 I (rnA) tune

Figure 7.5: Simulated loss resistance

The simulated loss resistance R p of the LC circuit as function of the tuning current is depicted in figure 7.5.

7.4 veo

The oscillation frequency as function of the tuning current is given in figure 7.6(a). The oscillation frequency is simulated for the circuit without parasitics and the circuit with parasitic extraction. As can be seen in figure 7.6(a) the oscillation frequency ofthe RC extracted circuit is lower than the oscillation frequency of the circuit without parasitics. The oscillation frequencies differ because the parasitic capacitances add to the capacitance in the LC circuit, this lowers the resonance frequency. The output power as function of the tuning current is shown in figure 7.6(b). The output power of the extracted circuit is slightly higher than for the circuit without parasitics. The oscillation frequency of the extracted circuit is lower, thus the skin effect is less and the resistance of the interconnects is lower which leads to higher output power. 63 7.4. veo

631~-~~~---~r=_=_=:=:N=O -10.6,------~-r======il R:=c==e=xt=ra=ct=;on'1l [ _. - No RC extraction -10.7 L= RC extractl,?n - RC extraction

N' 60 E -11 :I: ~ ~ '" -111 - 59 D.~ -1'.2

-11.3 '. 58 '. -11.4 57 '" -11.5t- ····_··----1 560~'--'--~~~~-~'0-~'2--'~4-~'6-~'8----'20 -11.6 '----L-----,O----cc'5:------:20 0 'tuM (mA) Itu.. (mA) (a) Oscillation frequency (b) Output power

Figure 7.6: Simulation results

-88,----~----~--~-~~_=O=si=m=UIa:::I'ed==::=:pN"il

-89 - .. -Modeled PN

-90 'N 'N ~ -90 ::!: -91 ,li '"~ -91 :Eo. -92 :1\ ~ -92 ~=-93 :1\ m -93 .c: !=-94 Q. Q. -94 -95

-95 -96 ...... ~------960:------:-----"":'0---~,5:-----=-20 -97Q'---'----'------',----~--~'0---012:-----,''-c4-:'::'8-..:',8:---:20

Itu.. (mA) 'U1.... (mA)

(a) Comparison between extracted and non extracted (b) Comparison between model and simulation circuit

Figure 7.7: Simulated phase noise performance

The simulated phase noise performance is depicted in figure 7.7(a). The phase noise perfor­ mance of the circuit with parasitics is better than of the non extracted circuit. It may be caused by the different models used for the transistors, the models used for the schematic simulation are different than the models used for the extracted simulation. Another possible explanation is that the added capacitances filter the noise. The simulated and the modeled phase noise performances are given in figure 7.7(b). Equa­ tion 3.82 is used for the modeled phase noise performance. The simulated quality factor, signal power and oscillation frequency are used. The fitting factors (3 and (31 are chosen to be zero, only the noise generated by the cross coupled pair and the LC circuit are taken into account as well as the quality factor of the LC circuit. The modeled phase noise performance should be lower than the simulated phase noise performance, because the simulator takes more noise sources into account. The peak in the phase noise performance coincides with the peak in the quality factor, see figure 7.4(b). Theory tells us that a higher quality factor should lead to a lower phase noise, the contrary is observed. The needed fitting factor (31 is shown in figure 7.8(a). The transistors in the Miller tuning circuit are off for very low values of tuning current and for a current around 3mA the transistors are starting to turn on and operate in the linear area. The noise power equations used in section 3.4 are only valid when the transistors operate in the saturation region. The phase noise peak occurs when the transistors operate in the linear area. CHAPTER. 7. SIMULATIONS 64

The flicker noise generated by the current mirror used in the Miller circuit is shown in figure 7.8(b). The shape is almost the same as the shape of the fitting factor, the increased flicker noise can explain the peak in the phase noise performance.

- NOise generated in current mirror

j .

°OL-~-~---:--8~--C'':-O 10 12 14 16 18 20 -'':-2-,:'-:-.-,c::-6 -,C::-8c::=:'20 Iwne(mA) ltune(mA)

(a) beta] (b) Simulated noise generated in current mirror

Figure 7.8: Noise fitting factor {31

7.4.1 Target Specification Comparison with Simulation The simulated VCO performance should be checked with the target specifications to see if they are met. The target specification and simulation results are summarized in table 7.1.

Sytem Property Without parasitics With parasitics Target Specification Tuning Range 8.14% 7.52% 9.84% fmin 57.62 GHz 56.34 GHz 58 GHz fmax 62.51 GHz 60.74 GHz 64 GHz Worst Phase Noise -87.8 dBc/Hz -88.5 dBc/Hz < -85 dBc/Hz

Table 7.1: Comparison of non extracted and RC extracted circuit

The tuning range and the frequency band specifications are not met. The oscillation frequen­ cies obtained by the simulations are lower than the desired oscillation frequencies. This is caused by parasitic capacitances, they add to the tunable capacitance and lower the oscillation frequency. There were more parasitic capacitances than was expected. The parasitic capacitances also de­ crease the tuning range as was analyzed in section 3.3, see equation 3.52. The variable capacitance g~ is slightly higher than two, see section 7.4, which is slightly better than is obtained with varac­ tors. To increase the tuning range the minimal Miller capacitance should be higher or the parasitic capacitances should be lower. The simulated phase noise performance is within specifications and is even better than was required. Chapter 8

Measurement

The measurement results of the test structures and veo are given in sections 8.2 and 8.3 respec­ tively. Many aspects of the veo can be analyzed, because test structures are taped-out. The test structures are the core coil and the Miller capacitor circuit. The oscillation frequency and tank losses can be extracted using the two structures. To obtain the test structure measurement data the bondpads have to be de-embedded. The de-embedding procedure is given in section 8.1.

8.1 De-embedding

When measuring a device on wafer not only the device is measured, but also the bondpads and the interconnects from the bondpads to the device under test (DDT). To obtain only the characteristics of the DDT the bondpads have to be removed, this process is called de-embedding. The bondpads and interconnects can only be de-embedded if they can be characterized, therefore de-embedding structures and a model are necessary. Dp to approximately 20GHz only open and short structures are needed at higher frequencies a known load is also needed. The difference is that at low frequencies the bondpad and interconnect can be modeled as a parallel capacitance and a series inductor, the capacitance at the end can be neglected, at high frequencies this no longer is the case. The de-embedding structures are shown in figures: 8.l(a), 8.l(b) and 8.l(c), where the black box is a known resistor. The model of the bondpads with interconnect is shown in figure 8.l(d).

(a) Open (b) Short (c) Load (d) Bondpad model

Figure 8.1: De-embedding structures

The capacitance C 1 is the sum of the capacitances of the bondpad, ESD protection and half of the interconnect capacitance. This capacitance can be characterized by the open structure. The Y parameter of the open structure is approximately equal to this capacitance, note that an error is made in this assumption. The error is corrected after all the parameters in the model are characterized, the error term at the end gives an indication whether the estimated capacitance is too large or too small. The model characterization is done using an iterative process. The series inductance is removed by de-embedding the Z parameters using the de-embedded short structure. The short structure has to be de-embedded using the open structure to remove C 1 from the short structure. And the interconnect capacitance Cz is removed by de-embedding the Y parameters using the de-embedded load structure.

6.'5 CHAPTER 8. MEASUREMENT 66

During the de-embedding several assumptions are made about the model and the load structure and one set of measured data is corrected with an other set of measured data, errors are introduced. The measurement uncertainty is small and is approximately 0.2% at 20GHz and 0.7% at 67GHz, these values are retrieved by the calibration procedure. The components are characterized at low frequencies to decrease the measurement uncertainty. The measurement uncertainty grows after each de-embedding step and after all the de-embedding steps it is 8 times larger than for one measurement. The uncertainty of the capacitances and inductance in the DDT is about 1.6% the uncertainty of capacitor C j adds approximately 6%. The resistance of the DDT is more difficult to measure, because an assumption is made about resistance of the load. The resistance can vary by as much as 9%, this is received after Monte Carlo simulations of the load. The uncertainty of the DDT capacitance and inductance is approximately 7.6% and the uncertainty of the resistance of the DDT is approximately 15.6%.

8.2 Test structures

Along with the VCO there were two test structures taped-out to verify the simulation results. If there are any differences between the simulation results and the measurements of the VCO the test structures can give valuable insights as to what changed. The two structures that were taped-out were the VCO core coil with interconnects and the actively tuned capacitor. The inductor test structure is the bottom structure in figure 8.3 with the small circle, the inductor. The actively tuned capacitor is the bottom structure which also has five extra bondpads to bias the circuit. The simulations and measurement of the core inductor gave a difference in inductance values, the measured inductance was approximately lOpH lower. The measured inductance was 115pH with a quality factor of 20.

35

30 LL :e. 25 - -". - ~._.- -~ ~ ~.~.-.-.- i ...... --- ~ 20 (,) " 15 t' I 10 --Simulated --- Measured 51---~--~-----,------'====='-J o 5 10 15 20 25 Itune (rnA)

Figure 8.2: Measured and simulated Miller capacitance

The simulated and measured Miller capacitance as a function of the tuning current is shown in figure 8.2. The simulated Q was approximately 6 and the measured Q 4.3.

8.3 veo

The VCO is the large top structure in figure 8.3. The right bondpads are the differential output. The large circle is the actively tuned Miller capacitor inductor and the small circle the VCO core inductor. The capacitors can be seen as big dots and the transistors are almost invisible. It is impossible to directly measure signals at 60GHz therefore an external mixer is added to down-convert the 60GHz signal into the frequency band of the spectrum analyzer. The mixer raises the noise floor to -55dBm which is very high. To measure the phase noise it was necessary 67 8.3. veo

Figure 8.3: Photo of the die to add an external low noise amplifier to increase the difference between the signal power and the noise floor. The simulated and measured oscillation frequency is depicted in figure 8.4(a). Three different samples are measured, the difference in frequency is small thus the process spread is very small.

681-~--~--r~'==:=Si=mU=latC:::ed=='il -10,----~-----~~--~--,

--. Measured sample 1 -12 ... - - Measured sample 2 ...... - Measured sample 3 -I'

~ -16 :!!.

. - Simulated . -+- Measured sample 1 -2 . ... - - Measured sample 2 ...... - Measured sample 3 _24L__c'======~--~_..-J 10 15 20 25 o 10 15 20 2S ltune(mA) Itune (mA) (a) Oscillation frequency (b) Output power

Figure 8.4: Measurement and simulation results

The output power measurement results are given in figure 8.4(b), the three measured samples are the same as the ones measured in figure 8.4(a). Again it can be seen that the difference between the samples is small, the output power of the third sample is lower than for the others. The phase noise of an oscillator is difficult to measure. The output signal of the presented veo is not clean, it contains multiple peaks at small frequency offsets, when measuring the spectrum analyzer sometimes found the wrong carrier and the measurement was corrupted. The spectrum is shown in figure 8.5. At small frequency offsets the phase noise can't be measured because of the noisy spectrum. At CHAPTERS. MEASUREMENT 68

I1kr! Ext M,x

~! ~3 ~~Iii...._WfII~-~ £(f): \. , ,...... •...... , ,...... •...... f>S0k Swp

VB~ 270 Hz

Figure 8.5: Output spectrum high frequency offsets the noise floor is hit and the phase noise also can't be measured. A typical measurement is shown in figure 8.6(a). The phase noise measurement is only reliable between a frequency offset of 400kHz and 5MHz. The phase noise performance of the veo as function of

Carrier Freq 60.98 GHz Signal Track Off DAHL Off Trig Free -65,--~--~--~-r===;====:ll Log Plot ."...... f...... Carrier PONer -16.84 dBm AUen 10.00 dB Mkr2 -70 Ref -50.00dBc!Hz ...... 10.00 • - ~ -75 ...... dB! i -00 ------31 '0 Z -85 " .I:::: -90 a. -95

Marker Type Value -100'------'-----~--~--~-----' 10 15 20 25 1 Spa t fr-eq 111Hz -8121.66 dBa/Hz o 2 Spo t fr-E'~ 1011Hz -'39.82 dBa/Hz Itune (rnA) (a) Screen shot (b) Phase noise as function of the tuning current

Figure 8.6: Phase Noise measurement the tuning current is depicted in figure 8.6(b). The values are obtained my measuring the phase noise at each point a number of times and take the average phase noise. The difference between two measurements were as high as 10dBm, the figure is only an approximation.

8.4 Comparison between simulations and measurements

The measured core inductance was slightly lower than the simulated inductance and the Miller capacitance was about lOfF lower than simulated. The measured Miller capacitance consisted mainly of the gate capacitances, the gate capacitances are also the parasitic capacitances of the cross coupled pair in the veo core. The parasitic capacitances are probably also smaller than simulated. The measured tuning range and oscillation frequency are larger than simulated. The simulated tuning range is 8.12% and the measured tuning range is 10.45%. The increased oscillation fre­ quency and tuning range can be explained by the fact that the Miller capacitance and the parasitic capacitances were smaller than expected. The measured output power is lower than simulated, 69 8.4. COMPARISON BETWEEN SIMULATIONS AND MEASUREMENTS but the shape is the same. This can be caused by three effects. The two differential outputs are combined by a hybrid and converted to a differential signal which is measured. When both paths have a mismatch the measured power can be less than the actual output power. The resistive loss in the transmission lines is also higher than was expected, maybe the resistive loss in the rest of the circuit was also higher. The third part of the explanation is that the output has a small mismatch, as a result not all the output power is transferred to the probes. The difference between the simulated and measured phase noise performance is large. It should be noted that the phase noise measurements were not stable and fluctuated by as much as lOdBc/Hz. The measured phase noise is approximately 15dB higher than simulated. This can be partly explained by the fact that the output spectrum was not as clean as was simulated. The actively tuned capacitor is probably less stable than simulated, when the capacitance varies by only a few aF the frequency changes by a few MHz. The shape of the phase noise performance is the same, the peak in the phase noise is caused by noise generated in the current mirror biasing the Miller capacitance circuit. When the tuning current is OmA the current mirror is off and the generate almost no noise, at high currents the transistors operate in the saturated region and generate a modest amount of noise. At approximately 2mA the transistors start to turn on and generate much more noise. This noise modulates the Miller capacitance which in turn modulates the oscillation frequency. Chapter 9

Comparison with reported VCOs

To compare different VCOs a figure of merit (FOM) is used. The FOM used is given in equation 9.1, where fo is the oscillation frequency 6f is the frequency offset of the phase noise measurement and Pdc is the consumed DC power. C~~ FOM =.L (61) - 20 log (if) + 10 log ) (9.1 )

To make a fare comparison between different VCOs the center frequency is taken into account. In table 9.1 different VCOs are compared to the presented work. The oscillators fabricated in SiGe often have better phase noise performance and thus FOM, because SiGe devices generate less noise than CMOS devices and need less current for the same gm. In figure 9.1(b) it can be seen that the SiGe circuits have a better FOM. The CMOS colpitts oscillator and the oscillator described in [6] have better FOMs. The oscillator described in [6] has a good FOM, but almost no tuning range. VCOs with small tuning range can have better phase noise performance, because the tune-able capacitor degrades the phase noise performance. The FOM for the presented VCO is good, taken in mind that the variable capacitor is actively tuned. The tuning range is large for the frequency band as can be seen in figure 9.1(a). The circuit using the Miller effect described in [17] and [18] are not included in the table since no measurement results were presented. They only remarked that their phase noise was poor, which probably had to do with the active tuning.

Reference Technology favg Tuning FOM [22] band 1 SiGe 61.5GHz 8.1% -164dB [22] band 2 SiGe 76.5GHz 1.3% -168dB [21] SiGe 81.5GHz 2.2% -182dB [10] band 1 SiGe 46.7GHz 8.5% -158dB [10] band 2 SiGe 59.2GHz 4.1% -156dB [11] InGaP 60GHz 2.3% -153dB [8], [9] CMOS 0.13p,m 26.3GHz 23.6% -165dB [19] Colpitts CMOS 90nm 77GHz 8.1% -182dB [19] Cross coupled CMOS 90nm 77GHz 2.6% -151dB [6] CMOS 90nm 60GHz 0.17% -192dB This Work CMOS 65nm 62.8GHz 10.5% -158dB

Table 9.1: VCO performance summary

70 71

TUning range (%)

... [8], [9] - SiGe • InGaP ... CMOS 20

15

This...work 10 [10] band- 1 [22] band- 1 [19] C2lpitts 5 [10] band 2 - [11] [19] Cross coupled • [22] band 2"" - [21] o [6] 25 35 45 55 65 75 freq (GHz)

(a) TUning range as function of the average oscillation frequency

jFOM(dB)1 - SiGe • InGaP ... CMOS 190

[19] Colpitts ... [2-1] 180

170 ... [8], [9]

160 This...work [10] balld 2 [V] [19] Crosi' coupled 150 25 35 45 55 65 75

(b) FOM as function of the average oscillation frequency

Figure 9.1: Comparison between different oscillators Chapter 10

Own Contribution

• Different tuning mechanisms were analyzed and compared.

Second order tank Transconductor tuned VCO Miller effect

• Systematic design flow of a VCO with Miller tuning.

• The VCO was designed, simulated, layed-out and measured.

• Compared different high frequency calibration and deembedding techniques. Measuring at very high frequencies is difficult and very sensitive to influences from the outside. Good probe placement and calibration is very important. Different calibration methods were compared, SOLR was chosen the best calibration algorithm.

72 Chapter 11

Conclusions and recommendations

This work proves that active capacitor tuning using the Miller effect works at high frequencies. The presented VCO operates in the 59.5GHz to 66.1GHz frequency range and has a tuning range of 10.4%, which is larger than needed. The VCO has been implemented in CMOS 65nm process. The output power is lower than the target. The phase noise varies from -80dBcjHz to -67dBcjHz. The circuit makes use of a actively tuned capacitor using the Miller effect, the phase noise performance is deteriorated by the noise generated in the tunable capacitor circuit. The core operates at 1.0V and consumes only 2.5mW, the complete VCO consumes 34mW. The circuit area is 330p,m by 145p,m without bondpads. The circuit is competitive in power consumption and frequency range.

Specification Target Realized Output power -13dBm -17dBm Center frequency 61GHz 62.8GHz Tuning range 9.8% 10.5% Phase noise @lMHz < -85dBcjHz -67dBc/Hz to -80dBcjHz

Table 11.1: Specifications

Future work should focus on increasing the phase noise performance. Attention should be paid to the noise generated in the current biasing circuit of the Miller capacitance. Maybe some differential biasing scheme can be used to remove the effect of the noise generated in the biasing source. Attention should also be paid on the extra frequency peaks close to the desired signal. The phase noise performance can also be increased by increasing the power of the output signal, so that it will be raised higher above the noise floor.

73 Chapter 12

References

74 Bibliography

[1] Phillip E. Allen and Douglas R. Holberg. CMOS Analog Circuit Design. Oxford University Press, Inc., second edition, 2002.

[2] H. M. Cheema. A 44.5 ghz differentially tuned vco in 65nm bulk cmos with 8range. In to be published: Proc. RFIC Symposium, June 2008.

[3] Sohrab Emami, Chinh H. Doan, Ali M. Niknejad, and Robert W. Bodersen. A highly inte­ grated 60ghz cmos front-end receiver. ISSCC, 2007.

[4] F. Herzel et al. A new approach to fully integrated cmos lc-oscillators with a very large tuning range. IEEE Custom Integrated Circuits Conf. (CICC), pages 573-576, 2000.

[5] Guillermo Gonzalez. Microwave Transistor Amplifiers. Prentice Hall, second edition, 1997.

[6] D. Huang, W. Hant, N. Wang, T.W. Ku, Q. Gu, R. Wong, and M.F. Chang. A 60ghz cmos vco using on-chip resonator with embedded artificial dielectric for side, loss and noise reduction. ISSCC Digest, pages 314-315, Feb 2006.

[7] Daquan Huang, William Hant, Ning-Yi Wang, Tai W. Ku, Qun Gu, Raymond Wong, and Mau-Chung F. Chang. A 60ghz cmos vco using on-chip resonator with embedded artificial dielectric for size, loss and noise reduction. ISSCC, 2006.

[8] KaChun Kwok and John R. Long. A 23-to-29 ghz transconductor-tuned vco mmic in 0.13 urn cmos. IEEE Journal of Solid-State Circuits, 42(12):2878-2886, Dec 2007.

[9] KaChun Kwok, John R. Long, and John J. Pekarik. A 23-to-29 ghz transconductor-tuned vco mmic in 0.13 urn cmos. ISSCC, 2007.

[10] Ja-Yol Lee, Sang-Heung Lee, Haecheon Kim, and Hyun-Kyu Yu. A 45-to-60ghz two-band sige:c vco for millimeter-wave applications. Radio Frequency Integrated Circuits Symposium, pages 709-712, 2007.

[11] Ockgoo Lee, Jeong-Geun Kim, and Joy Laskar. A 60-ghz push-push ingap hbt vco with dynamic frequency divider. IEEE Microwave and Wireless Components Letters, 15(10):679­ 681, Oct 2005.

[12] Thomas H. Lee and Ali Hajimiri. Oscillator phase noise: A tutorial. IEEE Journal of Solid­ State Circuits, 35(3):326-336, March 2000.

[13] D. B. Leeson. A simple model of feedback oscillator noise spectrum. Proceedings of the IEEE, 54:329-330, Feb 1966.

[14] John R. Long. Monolithic transformers for silicon rf ic design. IEEE Journal of Solid-State circuits, 35(9):1368-1381, Sept. 2000.

[15] R. K. Mongia, 1. J. Bahl, P. Bhartia, and J. Hong. RF and MICROWAVE COUPLED-LINE CIRCUITS. Artech House, second edition, 2007.

75 BIBLIOGRAPHY 76

[16] Behzed Razavi. Design of Analog CMOS Integrated Circ'u,its, chapter 7. McGRAW-HILL, 2001.

[17] K. Stadius, R. Kaumisto, and V. Porra. A high frequency harmonic vco with an artificial varactor. ICECS, 3:161-164, Sept 1998.

[18] K. Stadius, R. Kaumisto, and V. Porra. Varactor diodeless harmonic veas for ghz-range applications. ICECS, 1:505-508, Sept 1999.

[19] K.W. Tang, S. Leung, N. Tieu, P. Schvan, and S.P. Voinigescu. Frequency scaling and topology comparison of millimeter-wave cmos veas. IEEE Compo'u,nd Semicond-u,ctor Integrated Circ'u,it Symposium, pages 55-58, Nov 2006.

[20] Chi-Hsueh Wang, Hong-Yeh Chang, Pei-Si Wu, Kun-You Lin, Tian-Wei Huang, Huei Wang, and Chun Hsiung Chen. A 60ghz low-power six-port transceiver for gigabit software-defined transceiver applications. ISSCC, 2007.

[21] Robert Wanner, Herbert Schafer, Rudolf Lachner, Gerhard R. Olbrich, and Peter Russer. A fully integrated sige low phase noise push-push vco for 82 ghz. Gallium Arsenide and Other Semiconductor Application Symposium, pages 249-252, Oct 2005.

[22] Wolfgang Winkler, Johannes Borngraber, Bernd Heinemann, and Peter Weger. 60ghz and 76ghz oscillators in 0.25p. m sige:c bicmos. ISSCC, Feb 2003. Appendix A veo circuits

A.I veo core

The outputs V/ and Vo- are connected to the inputs V/ and V;- of the Miller tuning and output buffer circuits.

Figure A.I: veo core circuit

Component Parameter values L = 0.06jim M 1 ,M2 W = 22/1m Folding = 22 L = 0.18/1m M 3 W = I30jim Folding = 50 L = 0.18jim M 4 W = 60.03jim Folding = 23 L L = 47pH Rneg R = ±320n

I neg 1= 2.5mA (used in measurements) Vdd V = 1V (used in measurements)

Table A.1: veo core circuit components

77 APPENDIX A. VCO CIRCUITS 78

A.2 Miller tuning circuit

The inputs v:+ and v:- are connected to the outputs V/ and Vo- of the veo core.

Cc t--....I.----t ~v:+ v:- -II------'-----l Cc

Rtune

Figure A.2: Miller tuning circuit

Component Parameter values L = 0.18JLm M 1 W = 122JLm Folding = 50 L = 0.18JLm M 2 W = 139.08JLm Folding = 57 L = 0.06JLm M 3 ,M4 W= 45.9JLm Folding = 45 LL L = 107.5pH R L R = 40Sl Rbias R = ±5kSl Cc C = ±200jF Cn C = ±400jF R tune R = ±320Sl Ineg IE [OmA - 25mA] (used in measurements) Vg V = 1V (used in measurements) Vdd V = 1.2V (used in measurements)

Table A.2: veo core circuit components 79 A.3. OUTPUT BUFFER

A.3 Output buffer

The inputs V/ and V;- are connected to the outputs Vo+ and Vo- of the veo core.

v+o V-o I--'----it--V;+ V;- ----i I-----'----i Cc Cc

Figure A.3: Output buffer circuit

Component Parameter values L = 0.06f.Lm M1 ,M2 W= 20 f.L m

Folding = 20 I Ro R= 55n Rs R = 30n Rbias R = ±5kn Cc C = ±25fF

Vg V = 0.95V (used in measurements) Vdd V = 1V (used in measurements)

Table A.3: veo core circuit components Appendix B

Graduation paper

80 60GHz VCO Design With Miller Effect Tuning and Large Tuning Range Using 65nm CMOS Process

Maarten Lont Mixed-signal Microelectronics, Eindhoven University of Technology [email protected]

Abstract-Modern wireless systems aim for the license free 60GHz losses. At higher frequencies the quality factor decreases and thus frequency band to meet today's ever increasing call for higher bit the losses of the varactors increase and begin to dominate the tank rates. Current wireless standards are less suited, because of bandwidth losses. To arrive at a stable oscillation these losses will have to be restrictions. The large tuning range and high oscillation frequency are the biggest challenges. Varactors are often used to tune the oscillation compensated. Therefore, the losses should be minimized. The oscilla­ frequency, but at high frequencies the quality factor and tune-ability tion criteria are discussed in section II-A. At high frequencies also the begin to decrease and varactors become less desirable. The presented tune-ability of varactors degrades. The tune-ability can be expressed VCO makes use of an actively tuned capacitor using the Miller effect as g::~. For varactors this factor at 60GHz is approximately 2.1. using a standard NMOST transistor. Because the VCO is actively tuned the phase noise performance will be deteriorated. A CMOS technology The proposed VCO makes use of the Miller effect for the tuning is used to decrease the manufacturing costs and make it possible to mechanism, see section III. The maximal and minimal capacitance integrate the digital circuits on the same chip. This paper presents a ratio is 2.6 at 60GHz. The main goal of this work is to demonstrate a VCO operating in the frequency range from 59.5GHz to 66.1GHz. The 60GHz VCO with large tuning range using the Miller effect tuning. phase noise performance is dependent on the oscillation frequency and is between ·68dBcJHz and -82dBclHz. Therefore it is chosen to use a non-quadrature architecture to simplify the design. I. INTRODUCTION A. Related work Modem multimedia systems demand a wideband wireless There are not many publications on CMOS oscillators operating transceiver architecture and standard. The 60GHz band was chosen at 60GHz most VCOs use SiGe technology. SiGe is usually chosen because it is license-free. This band has a bandwidth of 6GHz, which is high enough for even the most demanding applications. The because it has a higher ft, better llf noise performance and higher Q of on chip passive components. The downside is that analog and standard is not fixed yet, the details are still under discussion. The digital integration is more difficult when SiGe is used. Negative 60GHz band is mainly suited for short distance communication since resistance VCOs operating on very high frequencies using SiGe:C the oxygen in the air absorbs the 60GHz electro magnetic energy. This limitation is an advantage since it reduces the problems with BiCMOS technology are reported In fl] [2] [3]. The core of the VCO presented in [2] operates at 4lGHz and uses a push-push architecture interfering transmissions, increases frequency reuse and increases the to obtain a single ended output at 82GHz. The VCO described in [4] security of the link. Transmitters in the vicinity are not received, because the attenuation is high. They can't interfere with the local also uses the push-push architecture and InGaP/GaAs technology. A 60GHz low power CMOS transceiver is described in [5] which transmission. The transmissions are secure because only devices in close proximity can receive the signal. uses a 60GHz VCO with a small tuning range. The transceiver in [6] uses a 30GHz CMOS VCO with a frequency doubler. Another VCO A zero-IF architecture is chosen for the transceiver. The received operating at 60GHz using CMOS technology is reported in [7] with 600Hz signal is directly demodulated to obtain the baseband signal. a good phase noise performance but a very small tuning range of This architecture is chosen because only one oscillator and mixer are required. The disadvantage is that the oscillator has to oscillate lOOMHz. There are no CMOS VCO's reported which operate at at 60GHz and has to span the entire frequency range, and clock­ 60GHz and have a large tuning range. There are a couple of VCO designs that address the tuning problem. feedthrough is possible. The details of this architecture is outside the scope of this paper. The Miller tuning used in the proposed VCO is already demonstrated in [8] and [9] using O.811m BiCMOS technology operating on The target specifications of the VCO presented in this paper are 2GHz. A transconductor-tuned oscillator operating on 26GHz is summarized in table I. The proposed VCO has a negative resistance architecture as is explained in section II-B, because it is a very robust demonstrated in [10] [11]. architecture. II. VCO ARCHITECTURE Specification Target A. Oscillation criteria Output power -13dBm with a 1000 differential output An oscillator can be seen as a feedback circuit as is depicted in Frequency band 58GHz-64GHz figure l(a). The H (jw) block is an amplifier and the (3 (jw) is the Phase noise < -85dBc/Hz @ IMHz frequency dependent element. The input signal Xi (jw) is normally TABLE I not present. For an oscillator to start oscillating an input signal is TARGET SPECIFlCATIONS required. This usually is circuit noise. The noise is amplified and fed back to the input through the feedback circuit (3 (jw). If the open loop gain is high enough the oscillation amplitude will start to grow. Most of todays negative resistance VCO designs use varactors to There are two criteria, called the Barkhausen criteria, which must tune the frequency. This is fine for oscillator designs operating at be met to have a stable oscillation. The first condition is the "gain frequencies below IOGHz where inductor losses dominate the tank condition" and is given by equation L. It specifies that the open loop x (jw) Y (jw) Active Part

L..-_-=+-,- +-_-'Yneg l:::,V

(a) Closed Loop Gain l:::,V' x (jw) Y (jw)

Passive Part X' (jw) Fig. 2. Negative Resistance Oscillator Model (b) Open Loop Gain

Fig. 1. Feedback system The amplitude is stable when the open loop gain is one, see the previous section. This leads to the relationship between the active gain (a) should be 1 when the oscillator is stable. This condition and passive admittance given by 8. ensures that the output signal does not grow nor decreases. The o (8) second condition is called the "phase condition" and is given by equation 2. This condition states that the open loop phase shift should The conductances Yp and Yneg are both complex admittances, their 0 be k times 360 , which is needed for the positive feedback. sum is zero when the sums of both the real and imaginary parts are IH (jw) (3 (jw)1 (1) zero, LH (jw) (3 (jw) (2) R{Yp } + R{Yneg } o (9)

For an oscillator to start oscillating the open loop gain should be 'S {Yp } + 'S {Yneg } o (10) larger than one. Equation 3 ensures that the signal power is limited C. Small signal negative resistance it holds in all practical oscillators. Psig is the signal power and a is the open loop gain. An implementation of negative conductance, Yneg in figure 2, aoo is given in figure 3(a). The two MaSTs implement the negative < 0 (3) apsig conductance and the current source is only necessary for biasing. There are a number of frequently used oscillator topologies. The most often used topologies are: ring oscillators, Colpitts oscillator, Hartley ~+ .+ Z oscillator, Clapp oscillator and negative resistance oscillator the last one is discussed in this work.

B. Negative resistance oscillator Alternatively to the feedback approach, a negative resistance ap­ proach can be used for some oscillator topologies. This is the case when both Hand (3 can be written as impedances or admittances. The negative resistance model is shown in figure 2. The oscillator is a differential oscillator. To calculate the open loop gain both sides have to be opened. When opening both sides the two subsystems seem to (a) Circuit be not connected anymore, this is not the case. Only the voltages are ~+ .+ v-t decoupled, the currents can still flow through the cuts. Z The voltage l:::, V' acts as the input signal, the current i is generated by the active part which leads to a voltage difference l:::, V at the passive part. The relationships for the active and passive part are given by 4 and 5 respectively.

l:::, V' X -Yneg (4) z rds l:::,V (5) Yp The open loop gain a is given by 6 substituting 4 in 5 leads to the open loop gain of the system given by 7. l:::,V a (6) (b) Small signal model l:::,V' _Yneg a (7) Fig. 3. Cross Coupled Pair Yp The small signal model is depicted in figure 3(b). In the small signal model it is assumed that both MOST Ml and M2 are identical. The small signal capacitances can be moved to the feedback loop {3. The negative resistance depends on the output resistance rd., and the trans-conductance gm. The small signal input conductance is calculated by solving the nodal equations and the real part is given in II. The parasitic capacitance is given by equation 12 as was expected. Since vt and - j Vi are connected i = -i- holds. (a) £::,.1 vs £::,. V

1 - gmrds (11 ) 2rds I:::,.V 1 2Cgd + 2CgS (12) The transconductance gm is given by equation 13, see [12]. Note that this is only true for a simple MOST model, not for a practical transistor. But the model still gives useful insights.

J1 KW (13) grn ss L (b)Ginvs£::"V

D. Large Signal Negative Resistance Fig. 4. Large signal IIV and GinN characteristics The analysis of the negative resistance in the previous section is only valid for small signals, since the linearized small signal model of the transistors are used. The small signal model also can't explain the of and the total bias current Iss goes through one transistor. This self-limiting behavior of the cross coupled transistor pair. However happens for the input voltage I:::,. V; 1 given by equation 17. Beyond using the large signal analysis it can be explained. In this section this voltage the model no longer holds.

the output resistance r ds and the parasitic capacitances Cpa1 are ss assumed to be constant and equal to the values in the small signal J2I L (17) model. This assumption holds only when the transistors operate in the KW saturated region. Assuming that rds is constant only a large signal In practise the output resistance rds can not be neglected. The trans-conductance Gm would have to be calculated which can be input admittance can be seen as thc admittance Gin from equation 16

substituted in the negative conductance given by II to obtain a large parallel with 2rds and parallel with Cpar • The complete input signal negative conductance. The drain current is usually modeled admittance is then given by 18. as a quadratic function of the gate source voltage. Note that this is 2 a simplified view. The model is given by equation 14, the output KW 4J:;: - 21:::,.V 1 --- + -- + sCpar (18) resistance is neglected for the moment. 4L J4J:{\f - I:::,.V2 2rds The negative conductance is the real part of the input admittance W 2 K 2L (Vgs - Vi) (14) and is given by equation 19. Which is the same as the small signal negative conductance in equation II except for the large signal The parasitic capacitance CPUT" given by 12 can be assumed to be Gm. The large signal trans-conductance Gm can be written as in the same for the large signal model as for the small signal model. equation 20. The capacitance is not taken into account when calculating the large 1- rdsGm signal negative resistance, it is transferred to the frequency selective (19) sub-circuit. 2rds Solving the nodal equations, the relationship between the differen­ KW W- 21:::,.V2 Gm (20) tial voltage I:::,. V and the differential current is given in equation 15. ss L - I:::,.VZ ---u J41KW

(15) The self limiting behavior of the negative resistance oscillator can be explained by the fact that the trans-conductance Gm and thus the The input admittance of the circuit without the resistance rds is negative conductance decreases as the signal voltage I:::,. V increases. given in equation 16. The admittance is equal to the slope of the At some point the open loop gain will be I and the signal amplitude current versus voltage characteristic. will be stable. When the input signal amplitude I:::,. V approaches zero the large KW 41ss L- 21:::,. V 2 Gin --- KW (16) signal trans-conductance Gm approaches the small signal trans­ 4L . /41s' L _ I:::,.V2 V KW conductance gm, which was given in equation 13. The current 1:::,.1 as a function of I:::,.V is given in figure 4(a). The E. Open loop gain input admittance as function of I:::,.V is depicted in figure 4(b). As can be seen the input admittance is a function of the input The passive part in figure 2 is the frequency selective element and signal. At a certain input voltage the negative conductance will drop consists of a lossy LC network, which is depicted in 5. The losses to zero. This happens when one of the transistors (Ml or M2) turns are modeled by the resistor R. The quality factor increases as the loss decreases. The quality factor of an inductor L with series resistance R is given by 31 and the R C L quality factor of a capacitance C with a parallel resistance R is given by 32. wL (31 ) Fig. 5. Lossy LC network R wRC (32)

The quality factor of the LC tank can be approximated by 33, when The admittance of the RLC tank is given by equation 21. The QL » 1. admittance for the negative conductance was already calculated and is copied in 22. Q (33) l+jR(wC- U:L) Ytank R (21) Using the quality factor, the impedance of the LC tank can be

v 1- gmrds 2C C gs (22) rewritten as, "neg 2 +s gd+ s - - rds 2 R Ztank (34) For an stable oscillation equations 9 and 10 should hold, substi­ 1 + jvQ tuting 22 and 21 gives, w Wo v (35) 2 I Wo w - + - gm (23) R rds The resistive loss R from figure 5 is given by equation 36.

j (w [c + 2Cgd + C;s] - w1L) 0 (24) R (36) The trans-conductance gm can be either the small signal gm or the large signal Gm trans-conductance. Equation 23 gives a condition The quality factor should be as high as possible, to maximize R for the gain of the oscillator, the trans-conductance should cancel and make the trans-conductance condition in 23 less stringent on gm. the losses in the loop. The frequency condition is given by 24, the condition is met when the frequency is given by 25. H. Phase noise 1 Wo (25) An ideal oscillator will have an output signal at exactly one fixed y!LC v frequency point, thus with an infinitely small bandwidth. The wider gs C+ 2Cgd + C2 (26) the output spectrum the more the performance of the transceiver decreases. In practice the bandwidth of an oscillator is finite the F. Tuning range noise generated in the circuit will modulate the phase of the output The tuning range is a measure of tune-ability and is expressed as signal. the frequency difference divided by the average oscillation frequency, The generated noise power i;' is amplified by the closed loop see 27, it is usually given as a percentage. The maximal oscillation gain of the oscillator and consists of thermal noise, flicker noise frequency is given by wei and the minimal by wo' and noise in the tuning circuit. Note that all normal capacitances are noiseless, if the loss is neglected, but the proposed YCO has .6wo an actively tuned capacitor. In the capacitor tuning circuit noise is TR --=- x 100% (27) Wo generated and this noise modulates the effective capacitance. Half of + - wo the noise power will modulate the phase of the signal, because the TR(%) 200 - Wo (28) wei +wo equipartition of thermodynamics tells that in equilibrium the phase noise and amplitude noise will be equal in power [13]. Thus half Substituting the oscillation frequency defined in 25 in 28 and of the amplified circuit noise is phase noise. The phase noise is assuming that the capacitor Cv is variable leads to 29, where ct expressed as a factor of noise power divided by signal power at a and C;; are the maximal and minimal capacitances respectively. certain offset frequency. It is usually given in a log scale in dBc/Hz. The phase noise equation is given by 37. TR 200 /fJ-Ic,-: (29) 1 1 2 i V~!"CT + L(.6f) = 10 log (-2 IHcl (j [fo + .6f])1 '2 ;') (37) 'lstgnal ~~ To increase the tuning range the factor should be maximized. The closed loop gain of the oscillator is given in 38, assuming that Substituting equation 26 and assuming onlyv C to be variable shows the oscillator is stable and the frequency offset .6f « fo. that ideally C should be much larger than the parasitic capacitances 1 to obtain a good tuning range. Hcl (j [j .6f])I/=/o (38) + . (?:..!:=.l.) Q G. Quality factor J /0 The quality factor Q of an element is a measure of the resistive Substituting the closed loop gain in 37 leads to 39. loss, the equation for the quality factor is given by 30. 1 fo 2 -i;' ) Estored L (.6j) 10 log 8Q2 (.6f) -'2- (39) Q w--- (30) ( 2stgnal Plost The model of the phase noise postulated by Leeson [14] is given by 47 in the equation for the tuning range given by 29 and assuming in 40. ¢ = 7f gives the tuning range with Miller tuning,

L (6J) lOlog _1_ A 2)PkT (40) Jl+B+ -1 (2Q2 (6j) Psignal 200 l+B- (48) Jl+B+ + 1 Leeson's model can be fitted to our model by writing the noise l+B- power as 41 and the signal power Psignal as 42. 200V1+B+ -1 (49) 4kT VI + B+ + 1 p (41) R The tuning range is independent of the Miller capacitance C. Note Psignal i;ignal R (42) that this only holds if the miller capacitance is much larger than the Leeson's model does not model the behavior for very small parasitic capacitances. frequency offsets, Leeson's model predicts a slope proportional to The quality factor of the input capacitance can be calculated by -z:}p- over the entire frequency range. For small frequency offsets the dividing the imaginary part by the real part of the input admittance, see 50. The quality factor is a measure of the loss in the capacitor, all slope is proportional to -z:!-rs this can be modeled in our model given the losses have to be compensated by the negative conductance. The in 39 by adding a l/f (flicker noise) component in the generated negative conductance is limited, thus the losses should be minimized noise. The phase noise will not decrease indefinitely, at some point and the quality factor should be maximized. it will hit the noise floor and will remain constant. 'S(Y;) Ill. TUNING USING THE MILLER EFFECT (50) Q iR(Y;) The miller effect can be explained by figure 6. The miller effect I-Bcos(¢) causes the effective input capacitance to be a function of the gain A. Q (51 ) Bsin (¢) Zo is the output impedance of the amplifier. By changing the gain the input capacitance can be changed. This effect can be used to tune The quality factor is maximal when ¢ = k7r, since the real part of the LC network. Work on the Miller tuning has already been done [8] the input admittance will be zero and there will be no loss. There is and [9]. The demonstrated YCO in the papers was implemented in a one exception, when the gain B = I and ¢ = 2krr the quality factor BiCMOS process. will be zero since the capacitance will be zero. The ideal value for the phase shift ¢ is krr both for the quality factor and the tuning.

C IV. CIRCUIT DESIGN A. VCO core Vi A.>---"-"oi o V The circuit of the YCO core is depicted in figure 8. The two transistors perform the function of a negative resistance and the LC circuit sets the oscillation frequency.

L Fig. 6. Miller circuit C The transfer function -if- is given in equation 43. The magnitude is denoted by B, which ii dependent on the gain A, and the phase shift by ¢.

Vo (43) Vi Vo BL¢ (44) Vi The input capacitance can be derived by dividing the imaginary part of the input admittance by w. The input capacitance C is given i Fig. 8. veo core by 47. From now on the input capacitance will be called the Miller capacitance. There are several parameters that can be chosen when designing jwC(I- Bcos(¢) - jBsin(¢)) (45) 'S{Y;} the YCO. The parameters are estimated at first using simple first (46) order models. The estimated values are used for simulation and using w the simulation results they are altered. Several system properties are C(I-Bcos(¢)) (47) influenced by several parameters they are summarized in table II. The input capacitance can be changed by changing the transcon­ The available negative conductance is given by 52. The constant ductance B. When ¢ = k7r the input capacitance is maximally is derived from simulations the transistor width W is given in p,m. dependent on the transconductance. The input capacitance can be The parasitic capacitance due to the cross coupled pair is linearized used to tune the LC network. Substituting the input capacitance given and given by 53. The constant is derived from simulations. Both the Possible Land W combinations Negative Conduclance 70

80 14

12 90

10 ~ 100 8 ~ g; 6 -' ~ 110

120 o 60 10 130

140 40 35 30 25 20 15 10 L (pH) W(um) W(um) (a) Achievable and minimum negative conduc­ (b) Possible Land W tance

C~ar

200

150

100

50

-50

-100 60 10

140 40 35 30 25 20 15 10 L (pH) W(um) W(um) (c) Achievable and minimum variable capaci­ (d) Possible L and W taking into account the tance capacitances

Fig. 7. Achievable solutions

Circuit Parameter Influence system properties gain Q needs to be 3. Based on simulations the quality factor of the Width of transistors G neg , WQ and Tuning Bias Current Gneg inductor is assumed to be 30 and the quality factor of the capacitance L R p, WQ and Tuning is assumed to be 6.5. C R v , WQ and Tuning 1 C tot (54) w1;L TABLE II C - C (55) DEPENDENCY OF SYSTEM PROPERTIES ON CIRCUIT PARAMETERS C var tot par QCQL R p {;f; (56) C var Qc + QL constants are dependent on the biasing current. A biasing current of Gneg,min ~JC~ar (57) 3mA is chosen. When choosing the parameter values these dependencies and the Gneg,possible ~ 0.34W(mS) (52) practical limitations should be kept in mind. The inductance L can Cpar,cross ~ 1.37W(jF) (53) not be larger than 220pH since the self resonance frequency would be too low. The self resonance should be at least 2.5 times as large The minimum negative conductance needed depends on the loss in as the highest frequency. The minimum value of L is 70pH, smaller the LC circuit and on the minimal open loop gain needed to have good values are not possible using the library components. The parasitic start-up behavior. The loss resistance R was previously derived and capacitances due to interconnections are approximately I IfF, based is copied to 56. The capacitance in equation 56 is only the variable on simulations. The minimal needed negative conductance and the capacitance and not the parasitic capacitance since only the variable achievable negative conductance as function of the added inductance capacitance contributes to the loss resistance. The small signal open and the transistor width are given in figure 7(a). loop gain can be used because at start up the oscillation amplitude The inductor L and width W should be chosen in such a way that is very small. For good start up behavior the minimal open loop the achievable IGnegl is above the minimum IGnegl. These values are shown in figure 7(b) the dark area is the solution space. The choice for the inductor and transistor width restrict the choice of the variable capacitance. The minimum and maximum capacitances (C- and C+) can be calculated when the inductance and the lowest and highest frequencies are known. The capacitor C is the same as depicted in figure 5. The equations for capacitances where already derived and are copied below,

(58)

(59)

The minimum capacitance is the sum of all the parasitic capac- Rtune itances and the minimum value of the variable capacitance. The minimal needed and achievable variable capacitances are given in figure 7(c). Based on simulations, the achievable minimum capaci- M1 tance is assumed to be 18fF. The minimum and maximum variable capacitances are calculated by subtracting the parasitic capacitances from the total minimum and maximum capacitances, see equation 60.

C± - CpaT (60) CtaT Fig. 9. Miller capacitance circuit Ratioc (61 ) C;;ar An important parameter of a variable capacitance is the ratio of maximum and minimum capacitance see equation 61. In most of the generates noise, this noise modulates the tail current Iss which practical variable capacitances this values is between 1 and 2. The modulates the Miller capacitance and the oscillation frequency. The needed capacitance factor is calculated and given in picture 7(d). The Miller capacitance will deteriorate the phase noise performance more darker the area the higher the capacitance factor has to be to obtain than a varactor would do. the desired tuning range. As can be seen a large part of the solution space leads to a rati 0 of capacitance Ratioc that is larger then 2 that R L + 8LL is why it is hard to obtain the entire tuning range. The white area in Z 0 = -----,=:------;:-- (62) 1 + Rgds + 8gdsLL the upper right corner does not contain any possible solution, since 2 V gmRL + 8 (gmLL - RLCgd) - 8 LLCgd the achievable negative conductance is to low. And the white area in o (63) 2 the lower left corner does not contain any possible solution since the 11; 1 + RLgds + 8 (RLCgd + LLgds) + 8 LLCgd minimum needed variable capacitance is lower then possible, here (64) 18fF. Only the colored area is a achievable solution space. gm= JIBS K;

B. Tuning circuit The transfer function can be written as the sum of the real and imaginary parts. The phase shift will be 0 0 or 1800 when the As was stated before the phase shift of the amplifier should be kJr. imaginary part is zero. Ideally the transfer function of the Miller When the load in figure 6 is purely resistive it is impossible to obtain amplifier, shown in equation 63, is purely real. The imaginary part a phase shift of kJr over a large range of transconductance B since is zero when its numerator is zero, so it is enough to analyze the the phase will be shifted by the capacitor C. numerator. The numerator of the imaginary part divided by w of the The phase is changed by introducing a low frequency zero in the transfer function is given by equation 65. left half plane. This leads to a frequency range where the phase shift 2 is approximately 7r, when a negative transconductance is assumed o Liw cgd (gm + gds) - LLgm + (65) which will be true for our implementation. The zero can be created by RLCgd (1 + RL [gm + gdsJ) adding an inductor to the load impedance. The circuit implementation is shown in figure 9. The solution for the inductance is given by equation 66. As can be The Miller capacitances are the effective input capacitances looking seen the optimal inductor is dependent on the resistance R and the into the nodes v:- and v:+. These nodes are connected to the veo transconductance gm. For now we will neglect the influence of gm. core. The transistors M 3 and M 4 act as the amplifiers and the For certain resistance values there will be zero, one or two solutions. gate drain capacitances (Cgd) are the Miller capacitors. The voltage gm ± (66) biasing at the gates of the transistors is necessary to ensure that the 2w 2 C gd (gm + gds) gate drain voltage does not become too high. 2 2 Jgm - 4RLW C;d (gm + gds) (l + RL [gm + gdsJ) The inductive output impedance is given in equation 62 and the 2 transfer function in 63, note that the previously declared transcon­ 2w C gd (gm + gds) ductance A is equal to - gm. The transconductance can be changed The inductance LL can only be a positive and real value, therefore by changing the tail current Iss, the equation for gm is given by 64. the discriminant should be larger than zero. This gives an upper bound To tune the veo with a voltage a voltage to current converter will for the capacitance C. be placed in front of the current mirror. In the presented paper the The optimal inductance LL versus resistance RL is shown in :onverter is omitted. The current mirror biasing the Miller circuit figure 10. There exist a solution when Rj < RL < R~. Note that in I Optimization goal ~ Maximize tuning range Maximize +r 9"'~ Jl+ 2 2 ....,2C~d 'Ii gm -4RL'.,2C d(gm+gds)(l+RL[gm+gds]) Maximize quality factor < _ 1 gm ± 9 2(gm+gd.<) + 2(gm+gd;) 2",2C, d(gm+gd.s) Z",2Cq d(gm+gd') Flat Q characteristic 0 -

TABLE 11\ OPTIMAL COMPONEI\T VALUES

a practical system the inductance and the resistance always will be C. Output buffer positive, valid values for R are in the range R E [0, Rz]. The VCO core itself is very sensitive to changes in capacitance and resistance, therefore it is impossible to directly measure at the output of the VCO core. To make measurements possible an output buffer is added. The chosen circuit is shown in figure 11. The buffer is a differential amplifier with a source resistance instead of current source. The input at the gate is DC decoupled using capacitance Cc, the capacitor is custom made because the capacitances in the library had large parasitic capacitances to ground which would decrease the tuning range.

Fig. 10. Optimal LL as function of R L

When R = Ri or R = R"2 equation 66 has only one solution. This is the case when the determinant is zero. R"2 is always positive thus there always are optimal solutions. The corresponding values for Ri and R"2 are given below,

VI + J~~d R; (67) 2 (gm + gds) 2 (gm + gds) R s 1 VI + J~~ R; + gd (68) - 2 (gm + gds) 2 (gm + gds) Fig. II. Output buffer To get a good quality factor of the entire tuning range, and thus gm range, the optimal inductance should not depend on the In the specifications it was specified that the output power should transconductance gm. The sensitivity of the optimal inductance with be higher than -13dBm when measured with a differential lOOn respect to the transconductance can be analyzed by taking the partial probe. The corresponding peak voltage is approximately 100mV. derivative of the inductance, this is done below, The output voltage amplitude of the VCO core is about 500mV, the buffer may attenuate the signal instead of amplifying the signal. It is 8L ± 1 (69) desirable to have small transistors, because the gate capacitances of 8gm lf~2 Z 3 V - 4w gm (1 + E) (gm + R1L) the transistors are connected to the LC circuit and will decrease the tuning range and oscillation frequency. The transfer function of the The output conductance gds can be approximated by Ex gm, where buffer is given by 71. The resistances Rprobe represent the probes E is a constant. Based on simulations E is derived to be approximately and are 50n. t. To minimize the dependence of LL on gm, the partial derivative should be minimized. For the derivative to be minimal R L and C RRprobe should be minimal. (70) R + Rprobe To optimize the tuning range the gain should be maximized since Vo -gmRv + sRvCgd the capacitance is proportional with the gain. To maximize the gain (71) Vi 1 + Rvgds + SRvCgd and thus tuning range the resistance R should be maximized and the L The zero and pole have a very high frequency, higher than the inductance LL should be ± )c' only the positive value is feasible. band of interest (58GHz-64GHz) thus the gain can be approximated There are a number of system properties which should be kept in by taking the DC gain, which is given in 72. mind when searching for the optimal component values, such as the tuning range and the quality factor. The optimal component values Vo I gmRv (72) are different for different system properties, the optimal component Vi w=Orad/s 1 + Rvgds values are given in table III. To get a good overall system the The output is measured using a lOOn terminated differential components are usually chosen to be sub optimal for a single property. probe, the single ended input impedance of the probe is 50n. For small reflection and thus a higher efficiency, the single ended output M7 impedance of the buffer should also be 50n, see [15]. The single ended output impedance is given by equation 73. Rout is slightly smaller than R as can be seen, for good matching R is chosen to be 55n. R Rout (73) 1 + Rgds V. LAYOUT CONSIDERATIONS

The schematic does not capture the parasitic effects, because (a) Physical parameters (b) Capacitances the physical connections are not known. The capacitances between components and interconnects can only be estimated after the whole Fig. 13. Line model chip is layed-out. During the layout process, the schematic should be altered to include the parasitic effects and the circuit parameters should be fine tuned in an iterative process to obtain the desired The equation for the fringe capacitance is given in 75. The specifications. capacitance Cper is the unit capacitance of the perimeter per p,m. The layout of analog circuits is more complicated than for digital The unit perimeter capacitance is multiplied by the perimeter which circuit, despite the fact that digital designs have many more tran­ leads to the total fringe capacitance. sistors, because digital circuits are less sensitive to noise and phase The resistive loss in the model is modeled by R. The resistance shifts and digital circuits operate on much lower frequencies. High is calculated by using the expression 76. The resistance per square frequency analog circuits are very sensitive to parasitic capacitances (R5q ) is simply multiplied by the number of squares in the signal because they influence the behavior of the circuit. There are no clear line. rules for analog layout, only rules of thumb. That's why computers can not layout analog circuits. R Len The parasitic resistances and capacitances can be extracted by R 5q W (76) the software for the components and short wide metal lines. The The velocity of propagation of a signal in a lossless transmission long interconnects also have parasitic inductances, these can not be line is given by equation 77, where LL and C are the inductance extracted automatically. These long lines are extracted manually. L and capacitance per unit length respectively. The long connections between various components consist of a metal 7 signal line and underneath a ground "return" line in metal J. 1 VL (77) The height between the signal line and return line is maximized to VLLCL minimize the parasitic capacitances. The interconnect can be modeled Using the equation for the speed of light in vacuum and the fact as a microstrip transmission line, see [16] for an in-depth analysis that the relative permeability on chip is one, the velocity simplifies of transmission lines. The interconnects are all relative short in to equation 78, where c is the speed of light. comparison with the wavelength which is approximately 3mm on c chip. If the transmission line is shorter than III 0 of the wavelength (78) it can be approximated with a single RLGC section, see figure 12. V4 A 7r model is used the total capacitance and conductance is divided Equations 77 and 78 leads to an expression for the inductance per by two and placed at the beginning and end of the line section. unit length in equation 79. (79) 2 C CL R L Substituting the inductance and capacitance per unit length in 79 gives rice to the equation for the total inductance of the line, see 80. Note that c is used for the speed of light and capital C is used for the total line capacitance.

E 2 L r Len (80) Fig. 12. Line RLGC 1r model c2 C VI. MEASUREMENT AND SIMULATION RESULTS The conductance between metal 7 and metal 1 is very small, A. De-embedding therefore the conductance G is neglected in the model. When measuring a device on wafer not only the device is measured, The total capacitance between the signal line and the ground plane but also the bondpads and the interconnects from the bondpads to can be divided in two components, a parallel plate capacitance and the device under test (DUT). To obtain only the characteristics of the a fringe capacitance. The physical model is shown in figure l3(a). DUT effects of the bondpads and interconnects have to be removed. Parameter Len is used for the length of the line and L for the total This process is called de-embedding. The bondpads and interconnects inductance of the line. can only be de-embedded if they can be characterized. Therefore, The equation for the parallel plate capacitance is given in 74. The de-embedding structures and a model are necessary. Up to 20GHz variables used are the same as in figure 13(a). only open and short structures are needed. At higher frequencies, LenW a son load is also needed. The reason for de-embedding is that Cplate EOE r --- (74) h at low frequencies the interconnect can be modeled as a series 2(Len + W)Cper (75) inductor and the capacitance can be neglected, at high frequencies this no longer is the case. The de-embedding structures are shown the simulation rcsults and the measurements of the YCO the test in figures: 14(a), l4(b) and l4(c), where the black box is a known structures can give valuable insights as to what changed. resistor. The two structures that were taped-out were the YCO core coil and the actively tuned capacitor. The inductor test structure is the bottom structure in figure 17 with the small circle, the inductor. The actively tuned capacitor is the bottom structure which also has five extra bondpads to bias the circuit. The simulated inductance was 134pH with a quality factor of 20. The measured inductor was approximately l25pH with a quality factor of 20 after the de-embedding procedure. The quality factor was not reliable because it was noisy. (a) Open (b) Short (c) Load

Fig. 14. De-embedding structures

The model of the bondpads with interconnect is shown in figure 15.

LL e. 25 --.... - "- . -- .... ------­ :i ~~~ 'E 20 , .­ u , 15 " I 10 --Simulated - - - Measured 51----'------'------'------======.J 5 10 15 20 25 Fig. 15. Bondpad model o Itune (rnA)

The capacitance C1 is the sum of the capacitances of the bondpad, Fig. 16. Measured and simulated Miller capacitance ESD protection and half of the interconnect capacitance. This capac­ itance can be characterized by the open structure; the Y parameter of The simulated and measured Miller capacitance as a function of the open structure is approximately equal to this capacitance. Note the tuning current is shown in figure 16. The simulated Q was that an error is made in this assumption. The error is corrected after approximately 6 and the measured Q 4.3. all the parameters in the model are characterized. The error term at the end gives an indication whether the estimated capacitance is too large or too small. The error is corrected and the procedure is repeated. The series inductance is removed by de-embedding the Z parame­ ters using the de-embedded short structure. The short structure has to be de-embedded using the open structure to remove C1 from the short structure. And the interconnect capacitance C2 is removed by de­ embedding the Y parameters using the de-embedded load structure. During the de-embedding several assumptions are made about the model and the load structure and while one set of measured data is corrected with an other set of measured data, errors are introduced. The measurement uncertainty is small and is approximately 0.2% at 20GHz and 0.7% at 67GHz. These values are retrieved by the calibration procedure. The components are characterized at low fre­ quencies to decrease the measurement uncertainty. The measurement uncertainty grows after each de-embedding step and after all the de-embedding steps it is 8 times larger than for one measurement. The uncertainty of the capacitances and inductance in the DDT is about 1.6%. The uncertainty of capacitor C 1 adds approximately 6%. The resistance of the DDT is more difficult to measure, because an Fig. 17. Photo of the die assumption is made about resistance of the load. The resistance can vary by as much as 9%, this is received after Monte Carlo simulations c. VCO of the load. The uncertainty of the DDT capacitance and inductance The YCO is the large top structure in figure 17. The right bondpads is approximately 7.6% and the uncertainty of the resistance of the are the differential output. The large circle is the actively tuned Miller DDT is approximately 15.6%. capacitor inductor and the small circle the YCO core inductor. The capacitors can be seen as big dots and the transistors are almost B. Test structures invisible. Along with the YCO there were two test structures taped-out to It is impossible to directly measure signals at 60GHz therefore an verify the simulation results. [f there are any differences between external mixer is added to down-convert the 60GHz signal into the frequency band of the spectrum analyzer. The mixer raises the noise Carrier Freq 60.98 GHz 5i9nal Track Off DAHL Off Tri9 Free Log P1(1t 1100r to -55dBm which is very high. To measure the phase noise it Carrier POHer -16.84 dB" Alten 10.00 dB was necessary to add a low noise amplifier to increase the difference between the signal power and the noise floor. The simulated and measured oscillation frequency is depicted in figure 18. Three different samples are measured, the difference in frequency is small thus the process spread is very small.

100 kHz Morker Trace Type Ualoe 681----r----~--7======:::;l , Spo\ Fr.q 1 MHz -813.66 d8c/H:z , Spo t Fr.q 19 "Hz -99.132 dBc/Hz --Simulated -e- Measured sample 1 6 --- Measured sample 2 Fig. 20. Phase Noise Measurement - Measured sample 31 1

-65,--~--~~--~-r=:::::::==;l , _-Simulated -70:"-- ...... 1- ...... Measured , , ¥ -75 I , , 13 , ------...... S'" -80 --. ill ~ -85

.c: -90 5 10 15 20 25 n. Itune (rnA) -95

_1()()L---~--~~--~--~------J Fig. 18. Measured and simulated oscillation frequency o 10 15 20 25 ltune(mA)

The output power measurement results are given in figure 19, three Fig. 21. Phase Noise measurement samples are measured. It can be seen that the difference between the samples is small, the output power of the third sample is lower than for the others. VII. DISCUSSION

-10,------r----.,-----,------,----_ The measured core inductance was slightly lower than the simu­ lated inductance and the Miller capacitance was about IOfF lower -12 than simulated. The measured Miller capacitance consisted mainly of the gate capacitances, the gate capacitances are also the parasitic -14 capacitances of the cross coupled pair in the veo core. The parasitic E 1II -16 capacitances are probably also smaller than simulated. ~ The measured tuning range and oscillation frequency are larger than simulated. The simulated tuning range is 8.12% and the mea­ sured tuning range is 10.45%. The increased oscillation frequency and --Simulated -e- Measured sample 1 tuning range can be explained by the fact that the Miller capacitance -2 --- Measured sample 2 and the parasitic capacitances were smaller than expected. The - Measured sample 3 -24l----':-'=====:::;:::====::;'----'~-~ measured output power is lower than simulated, but the shape is the o 5 10 15 20 25 same. This can be caused by three effects. The two differential outputs Itune (rnA) are combined by a hybrid and converted to a differential signal which is measured. When both paths have a mismatch the measured Fig. 19. Measured and simulated output power power can be less than the actual output power. The resistive loss in the transmission lines is also higher than was expected, maybe the The phase noise of an oscillator is difficult to measure. The resistive loss in the rest of the circuit was also higher. The third part output signal of the presented veo is not clean, it contains multiple of the explanation is that the output has a small mismatch, as a result peaks at small frequency offsets, when measuring the spectrum not all the output power is transferred to the probes. analyzer sometimes found the wrong carrier and the measurement The difference between the simulated and measured phase noise was corrupted. At small frequency offsets the phase noise can't be performance is large. The measured phase noise is approximately measured because of the noisy spectrum. At high frequency offsets 15dB higher than simulated. This can be partly explained by the the noise floor is hit and the phase noise also can't be measured. fact that the output spectrum was not as clean as was simulated. A typical measurement is shown in figure 20. The phase noise The disturbances in the output spectrum made the phase noise measurement is only reliable between a frequency offset of 400kHz measurements unstable, the measured values can change by as much and 5MHz. The phase noise performance of the veo as function of as 10%. The actively tuned capacitor is probably less stable than the tuning current is depicted in figure 21. The values are obtained my simulated, when the capacitance varies by only a few aF the frequency measuring the phase noise at each point a number of times and take changes by a few MHz. The shape of the phase noise performance the average phase noise. The difference between two measurements is the same, the peak in the phase noise is caused by noise generated were as high as lOdBm, the figure is only an approximation. in the current mirror biasing the Miller capacitance circuit. When the tuning current is OmA thc cun'cnt mirror is otT and the gencrate almost performance can also be increased by increasing the power of the no noise, at high currents the transistors operate in the saturated outout Sl gna1, so that It WI'11 be raise . d h'IgJher a bove t h e nOIse fl00r. region and generate a modest amount of noise. At approximately Specification Target Realized -13dBm -17dBm 2mA the transistors start to tum on and generate much more noise. Output power Center frequency 61GHz 62.8GHz This noise modulates the Miller capacitance which in tum modulates Tuning range 9.8% 10.5% the oscillation frequency. Phase noise @IMHz < -85dBclHz -67dBclHz to -80dBclHz To compare different VCOs a figure of merit (FOM) is used.

The FOM used is given in equation 81, where f 0 is the oscillation TABLE V frequency 6f is the frequency offset of the phase noise measurement SPECIFtCATIONS and Pdc is the consumed DC power. (~f) (l~d~l) FOM = £(6f) - 20 log + 10 log (81) ACKNOWLEDGMENT

To make a fare comparison between different VCOs the center I would like to thank NXP for giving access to CMOS 65nm technology and especially Edwin van der Heijden and Anton de frequency is taken into account. In table IV different VCOs are Graauw for there help. Also I would like to thank Reza Mahmoudi compared to the presented work. The oscillators fabricated in SiGe often have better phase noise performance and thus FOM, because for his guidance. SiGe devices generate less noise than CMOS devices. The tuning REFERENCES range is high for the frequency band and the FOM is average, this is [I] W. Winkler, J. Bomgraber, B. Heinemann, and P. Weger, "60GHz and mainly caused by the bad phase noise performance. The circuit using 76GHz Oscillators in 0.25Jl m SiGe:C BiCMOS," ISSCC, Feb 2003. the Miller effect described in [8] and [9] are not included in the table [2] R. Wanner, A. Schafer, R. Lachner, G. R. Olbrich, and P. Russer, "A since no measurement results were presented. They only remarked Fully Integrated SiGe Low Phase Noise Push-Push VCO for 82 GHz," that their phase noise was poor, which probably had to do with the Gallium Arsenide and Other Semiconductor Application Symposium, pp. 249-252, Oct 2005. active tuning. [3] J.-Y. Lee, S.-A. Lee, H. Kim, and H.-K. Yu, "A 45-to-60GHz Two­ Band SiGe:C VCO for Millimeter-Wave Applications," Radio Frequency Reference Technology favg TIming FOM Integrated Circuits Symposium, pp. 709-7 t2, 2007. [I] band I SiGe 61.5GHz 8.1% -164dB [4] O. Lee, J.-G. Kim, and J. Laskar, "A 60-GHz Push-Push InGaP HBT [1] band 2 SiGe 76.5GHz 1.3% -168dB VCO With Dynamic Frequency Divider," IEEE Microwave and Wireless [2] SiGe 81.5GHz 2.2% -182dB Components Letters. vol. 15, no. 10, pp. 679-681, Oct 2005. [3] band I SiGe 46.7GHz 8.5% -158dB [5] C.-H. Wang, H.-Y. Chang, P.-S. Wu, K.-Y. Lin, T-W. Huang, A. Wang, [3] band 2 SiGe 59.2GHz 4.1% -156dB and C. H. Chen, "A 60GHz Low-Power Six-Port Transceiver for Gigabit [41 InGaP 60GHz 2.3% -153dB Software-Defined Transceiver Applications," ISSCC, 2007. [10], [111 CMOS O.13Jlm 26.3GHz 23.6% -165dB [6] S. Emami, C. H. Doan, A. M. Niknejad, and R. W. Bodersen, "A Highly [17] Colpitts CMOS 90nm 77GHz 8.1% -182dB Integrated 60GHz CMOS Front-End Receiver," ISSCC. 2007. [17] Cross coupled CMOS 90nm 77GHz 2.6% -t5ldB [7] D. Huang, W. Hant. N.-Y. Wang, T W. Ku, Q. Gu, R. Wong. and M.­ [18] CMOS 90nm 60GHz 0.17% -192dB C. F. Chang, "A 60GHz CMOS VCO Using On-Chip Resonator with This Work CMOS 65nm 62.8GHz 10.5% -158dB Embedded Artificial Dielectric for Size. Loss and Noise Reduction," ISSCC, 2006. TABLE IV [8] K. Stadius, R. Kaumisto, and V. Porra, "A High Frequency Harmonic VCO PERFORMANCE SUMMARY VCO with an Artificial Varactor," ICECS, vol. 3, pp. 161-164. Sept 1998. [9] --, "Varactor DiodeIess Harmonic VCOs For GHz-Range Applica­ tions," ICECS, vol. 1. pp. 505-508. Sept 1999. VIII. CONCLUSIONS AND RECOMMENDATIONS [10] K. Kwok and J. R. Long, "A 23-to-29 GHz Transconductor-Tuned VCO MMIC in 0.13 Jlm CMOS," IEEE Journal of Solid-State Circuits, This work proves that active capacitor tuning using the Miller vol. 42, no. 12. pp. 2878-2886, Dec 2007. effect works at high frequencies. The presented VCO operates in [II] K. Kwok, J. R. Long, and J. J. Pekarik. "A 23-to-29 GHz the 59.5GHz to 66.1GHz frequency range and has a tuning range of Transconductor-Tuned VCO MMIC in 0.13 Jlm CMOS," ISSCC, 2007. 10.4%, which is larger than needed. The VCO has been implemented [12] P. E. Allen and D. R. Holberg. CMOS Analog Circuit Design, 2nd ed. Oxford University Press, Inc., 2002. in CMOS 65nm process. The output power is lower than the target. [13] T H. Lee and A. Hajimiri, "Oscillator Phase Noise: A Tutorial," IEEE The phase noise varies from -80dBclHz to -67dBclHz. The circuit Journal ofSolid-State Circuits. vol. 35, no. 3, pp. 326-336, March 2000. makes use of a actively tuned capacitor using the Miller effect, the [14] D. B. Leeson, "A Simple Model of Feedback Oscillator Noise Spec­ phase noise performance is deteriorated by the noise generated in the trum," Proceedings of the IEEE, vol. 54, pp. 329-330. Feb 1966. tunable capacitor circuit. The core operates at 1.0V and consumes [15] G. Gonzalez. Microwave Transistor Amplifiers, 2nd ed. Prentice Hall, 1997. only 2.5mW, the complete VCO consumes 34mW. The circuit area [16] R. K. Mongia, I. J. Bah], P. Bhartia, and J. Hong, RF and Microwave is 330JLm by 145JLm without bondpads. The circuit is competitive Coupled-Line Circuits, 2nd ed. Artech House, 2007. in power consumption and frequency range. [17] K. Tang. S. Leung. N. Tieu, P. Schvan, and S. Voinigescu, "Frequency Future work should focus on increasing the phase noise perfor­ Scaling and Topology Comparison of Millimeter-wave CMOS VCOs," IEEE Compound Semiconductor Integrated Circuit Symposium, pp. 55­ mance. Attention should be paid to the noise generated in the current 58, Nov 2006. biasing circuit of the Miller capacitance. Maybe some differential [18] D. Huang, W. Hant, N. Wang, T Ku. Q. Gu. R. Wong, and M. Chang, biasing scheme can be used to remove the effect of the noise "A 60GHz CMOS VCO Using On-Chip Resonator with Embedded generated in the biasing source. Attention should also be paid on the Artificial Dielectric for Side, Loss and Noise Reduction," ISSCC Digest, extra frequency peaks close to the desired signal. The phase noise pp. 314-315. Feb 2006. A 60GHz Miller Effect Based VCO 111 65nm CMOS with 10.5% TU11ing Ral1ge

1 1 1 Maarten Lont , Reza Mahmoudi1, Edwin van der Heijden2, Anton de Graauw2, Pooyan Sakian , Peter Baltus , Arthur van Roermund1

1Mixed-signal Microelectronics, Eindhoven University of Technology, Eindhoven the Netherlands 2NXP Research, High-Tech Campus 37, Eindhoven the Netherlands

Abstract-This paper presents a 60GHz voltage controlled its tum confines the tuning range of the YCO. In practice the oscillator implemented in conventional 65nm CMOS technology. varactors dominate the finite quality factor of the resonator This VCO employs an alternative tuning system based on at high frequencies. The g:,:~ ratio of the variable CMOS the Miller capacitance instead of conventional varactors. The presented VCO has a tuning range of 10.5% and operates in the varactors are simulated to be as low as 2.1 at 60GHz using a frequency range of 59.5GHz to 66.1GHz. It has an output power CMOS 65nm technology. As a consequence the needed tuning of -13dBm and a phase noise of 80dBc to -85dBclHz @ 1MHz range using these varactors is very difficult at 60GHz. over its entire range. The figure-of-merit (FOM) of this VCO is As an alternative to the conventional approach, in this paper, -162dB. we will present a tuning architecture based on the miller Index Terms- VCO, Phase Noise, Millimeter-wave, Miller capacitance principle with a target tuning range of 10% and effect a target phase noise performance of -85dBc/Hz. The Miller effect tuning was first proposed in [3].

1. INTRODUCTION II. TUNING USING THE MILLER EFFECT Extrapolating the rapid growth of wireless data rates that Fig. 1 illustrates the major principle behind the Miller effect, we have seen over the last three decades, where the wireless whereby the voltage gain is given by 1 and 2 and the effective capacity has been increasing two-fold every 18 months, leads input admittance is given by 3 and 4. to the unambiguous conclusion that data rates of about 2Gbps Vo gmZo + sZoC will be needed in couple of years from now [I]. (1) Vi 1 + sZoC Most of the present effort towards higher data rates is aimed V o BL¢ (2) at enhancing the spectral efficiency of existing or currently Vi developing microwave and millimeter-wave wireless systems. The quality factor (Q) of the effective input admittance However, the spectral bandwidth of such systems is limited, (li) is given by 5. These parameters are a function of the and they will not be able to support data rates exceeding amplifiers transconductance (gm), the load impedance (Zo) 500 Mbps. In the long run, there is no alternative but to and the capacitance (C). They can also be expressed as a tum towards higher carrier frequencies. The ISM frequency function of the magnitude of the voltage gain B and the phase range of 57-64GHz offers new possibilities for this matter. It of the overall voltage gain ¢. is unregulated and offers very large bandwidths, in excess of 2GHz. Among different transceiver concepts, the homodyne archi­ jwC(I-Bcos(¢) -jBsin(¢)) (3) tecture has been considered as a serious candidate for 60GHz C(l-Bcos(¢)) (4) applications due to its compactness and simplicity. Among 1 - B cos (¢) Q (5) the general well-known challenges [2], the requirement for a B sin (¢) voltage controlled oscillator with a large tuning range and a proper phase noise performance can be seen as one of the main bottlenecks to the proper functionality of homodyne concept. The span of the operating frequency dictates the tuning range C of the voltage controlled oscillator and the performance of the ii i g o V phase noise is dominated by the characteristic of the phase­ Vi o locked-loop in use, which can vary from -85dBc to -95dBc at IMHz offset of the carrier frequency. Zo Yaractors are typically used for the realization of frequency tuning in conventional voltage controlled oscillators. Operating at high frequencies in conjunction with the non-ideal intercon­ Fig. 1. Miller circuit nects degrades the quality factor of the CMOS varactors that in 2

Further inspection of these relations reveals that when the capacitances which decreases the tuning range. To satisfy the phase characteristic of the overall voltage gain approaches oscillation criteria the open loop gain is chosen to be a = 3 0 180 , the value of the effective input capacitance becomes and the LC tank is tuned to the appropriate frequency. mainly a function of the amplifier transconductance and the real value of the effective input admittance becomes minimal. 1 Controlling the amplifier transconductance with the amplifier (6) w2 L biasing provides the required mechanism for the control of the o Cvar Ctot - Cpar (7) effective input capacitance (Ci ). The reduction of the effective input-loss can be used to improve the quality factor of the Equations 6 to 8 describe general characteristics of an LC effective input capacitance. network containing a variable capacitance. The total capaci­ tance, including the added variable capacitance Cvar and the III. DESIGN parasitics Cpar is given by Ctot and L is the core inductor. Using the proprierity inductor model of NXP a quality factor A. veo Design Boundaries (QL) of 30 can be assumed for the inductor. The quality factor The well known cross-coupled topology is used for the VCO of the variable capacitor (Qc) is simulated to be 6.5. The core. Optimizing the tuning range for a certain frequency range overall LC tank quality factor is given by Qtank. in conjunction with fulfilling the oscillation criteria can be con­ sidered as the main target of this design paradigm. The phase noise performance was only a secondary design criterion. var Qc + QL G p JC (8) Accomplishing this target demands an appropriate overview of L QCQL the parasitic capacitances of the active and passive components var and non-ideal interconnections. A proper understanding of Gneg,min a JC (9) Qtank L the relations between design parameters is also necessary. Increasing the vco core inductance will increase the quality Equation 8 relates the effective loss of the LC network (Gp ) factor and thus phase noise performance and increase the open to the unloaded quality factor of the LC network. From these loop gain, but it will decrease the capacitance value and thus relations, one can conclude the minimum negative conductance the tuning range. Increasing the width of the VCO core cross­ (Gneg,min) of the cross coupled oscillator. coupled transistors will increase the negative conductance and The above relation gives a lower boundary for the negative thus the open loop gain but it will also increase the parasitic conductance. Fig. 2(a) and 2(b) illustrate the attainable nega­ tive conductance as function of the width of transistor and the inductance value. The attainable negative conductance has to Possible Land W combmabons 70 be above the lower boundary for oscillation to take place. The frequency of operation dictates a direct relation between the inductor and the effective capacitance which is a function 90 of parasitic capacitances of passive and active components and 100 ~ tuneability of the variable capacitance. Fig. 2(c) illustrates the 110 realizable minimum value of the capacitance for operating at

120 the upper boundary of the required tuning range as function of the width of transistor and the value of the inductor. '30 A combination of these two boundaries draws the general

35 25 ,.., .., W(um) L (pH) W(um) guideline for our design procedure. Fig. 2(d) distinguishes realizable and infeasible areas as a function of transistor width (a) Achievable and minimum negative (b) Possible Land W conductance and inductor value. Unachievable areas are presented at the upper right corner and the lower left corner because infeasible value for the minimum negative conductance and minimal variable capacitance. Projecting the required ratio between the maximum and minimum capacitance (~,t"r) into this picture will define the boundary for a proper trade-off between the power consumption and reducing the susceptibility to process variation. Fig. 2(d) illustrates that a transistor width of 15ft m and an inductor value around 120 pH can be used as the '0 initial values for design procedure.

140 40 L(pH) W(um) B. Tuning circuit (c) Achievable and minimum variable (d) Possible Land W taking into ac- capacitance count the capacitances Fig. 3 illustrates the tuning circuit of the VCO. The effective ~+ ~- Fig. 2. Achievable solutions capacitances at the nodes and are used to tune the circuit, these capacitances are a function of the tail current 3

Iss. Iss manipulates the gain of M3 and M4 and the gate­ drain capacitances, Cgd. Although the mirror current provides a robust and compact gain control system, its contribution to the deterioration of the phase noise performance has reduced its usefulness. At worst the current mirror noise contributed approximately 60% to the overall noise. The quality factor of the effective capacitance is a function of the voltage swing over the load which can deteriorate the phase noise performance. Although the implementation of a capacitance at the gate of transistors MI and M2 can improve the phase noise performance, its practical value limits its effectiveness. Improving the quality factor of the effective capacitances is accomplished through the insertion of an inductor LL, see Fig. 3. This inductor creates a low frequency zero at the left Fig. 4. Photo of the die half plane and it contributes to the realization of 1800 phase shift over entire tuning range.

35

lL:' ~ ~. ~ ::::;. 25 ~ ..;"..- .. -.-. -. -- ""':' - .9i -- -~- ~ 20· ... U " 15 I' I 10

5 10 15 20 25 Ilune (rnA)

Fig. 5. Measured and simulated Miller capacitance

Fig. 3. Miller capacitance circuit B. VCO Fig. 6 shows the simulated and measured oscillation fre­ quency of three different samples. Discrepancies between IV. MEASUREMENT AND SIMULATION RESULTS three samples are small. The simulated tuning range was 8%, the measurement showed 10.5% tuning range. This can be For test and debugging purposes additional test structures, explained by the smaller than expected value for the Miller e.g. an inductor and an active capacitance have been taped capacitance. out alongside the VCO (see fig. 4). The inductor occupies the biggest area in the active Miller capacitor layout. Mea­ surements have been made using an Agilent PNA Network 68,--~--~--r=_=~::;:Sim=U:;=la=led:;=====il ...... Measured sarrple 1 Analyzer E8361A and an Agilent PSA Spectrum Analyzer -- - Measured sarrple 2 ___ Measured sample 3 E4446A extended with an Agilent preselected millimeter mixer ll974V Measurement results are compensated for the external loss of e.g. cables and probes.

A. Test structures 56L---:-----':c-=::::~==":""'~~~ The simulation results have indicated a value of 134pH with o 10 15 20 25 a quality factor of 20 for the VCO core inductors L which Itune (rnA) closely matches the measurements results of approximately Fig. 6. Measured and simulated oscillation frequency I25pH. Fig. 5 depicts the simulation and measurement results of the active Miller capacitance. The measurement results are approximately 10fF lower than simulated which probably is A value of -13dBm has been measured for the output power due to overestimation of transistor parasitics. The simulation level which is 2dB lower than simulated. This difference can results indicated a value of 6 for the quality factor the active be caused by mismatch in the differential output paths and Miller capacitance, although the measurement results point larger loss in the transmission lines. A varying shift of the toward a Q value of 4.3. center frequency in the range of 5MHz, complicated a proper 4 phase noise measurement. This behavior caused a shift of tuned capacitor using the Miller effect. The phase noise the operational frequency of the VCO during the phase noise performance is influenced by the noise generated in the tunable measurement which made the measurement less reliable. The capacitor circuit. measured phase noise is shown in fig. 7 as a function of the To improve the phase noise performance, the current mirror tuning current. in the Miller capacitor circuit can be removed and the Miller The peak in phase noise is caused by the generated IIf noise capacitance can be directly tuned by biasing the gate. To make of the current mirror. From simulations it was estimated that a better model and gain more insights into the working of the the IIf noise made up 60% of the total noise. At the high Miller capacitor circuit a large signal model should be used. end of the tuning range, transistors M and 111 operate in 1 2 IFOM(dB) I the saturated region and they generate a modest amounl of noise. At approximately 2mA these transistors are biased just 190 .[8] • SiGe above threshold and the contribution of the l/f noise will be .... CMOS maximal. [5] [7] C£lpitts 180 •

-781Ji1\--~--~---r-;======::;l \ -Simulaled -80 I , _ .. '\ . - .. - Extracted results [4] band 2 -82·j , .,. "" '... 170 N ~ , • [4] band L · k ~ -84 '\ ... _------­ •T h IS .wor ~-B6 160 [6] band 1 ~ -88 [6] band 2 • '0 '-----_ • ~ -90 [7] Cross coupled ~ -92 150 a. -94 o 2.5 5.0 7.5 10.0 -96 Tuning Range (%)

_98'---__~__~ ~______.J o 10 15 20 25 Itune (rnA) Fig. 8. FOM as function of tuning range

Fig. 7. Phase Noise measurement ACKNOWLEDGMENT We would like to thank NXP for giving access to CMOS V. DISCUSSION 65nm technology and especially Dennis Jeurissen for his help. To compare different VCOs, a figure of merit (FOM) as shown in 10 is used, the FOM of the presented VCO is -162dB. REFERENCES Where fa is the oscillation frequency, £:'f is the frequency [I] S. Cherry, uEdhoim's Law of Bandwidth," IEEE Spectrum, no. 4I, p. 50, offset of the phase noise measurement and Pdc is the consumed July 2004. DC power. [2] B. Razavi, UDesign considerations for direct-conversion receivers," IEEE Transactions On Circuits And Systems, vol. 44, no. 6, 1997. (1~~) [3] K. Stadius, R. Kaumisto, and V. Porra, uYaractor Diodeless Harmonic FOM = L(£:'f) - 20 log (if) + 10 log (10) YCOs For GHz-Range Applications," ICECS, vol. I, pp. 505-508, Sept 1999. In fig. 8 different VCOs, all operating around 60GHz, are [4] W. Winkler, J. Bomgraber, B. Heinemann, and P. Weger, u60GHz and compared to the presented work. Compared to other presented 76GHz Oscillators in 0.25/1. m SiGe:C BiCMOS," ISSCC, Feb 2003. [5] R. Wanner, H. Schafer, R. Lachner, G. R. Olbrich, and P. Russer, UA VCO's the tuning range is large and the FOM is average. Fully Integrated SiGe Low Phase Noise Push-Push YCO for 82 GHz," The average FOM is caused by the non optimal phase noise Gallium Arsenide and Other Semiconductor Application Symposium, pp. performance. 249-252, Oct 2005. [6] J.- Y. Lee, S.-H. Lee, H. Kim, and H.-K. Yu, uA 45-to-60GHz Two­ Band SiGe:C YCO for Millimeter-Wave Applications," Radio Frequency VI. CONCLUSIONS AND RECOMMENDATIONS Integrated Circuits Symposium, pp. 709-712, 2007. [7] K. Tang, S. Leung, N. Tieu, P. Schvan, and S. Yoinigescu, "Frequency The presented VCO operates in the 59.5GHz to 66.1GHz Scaling and Topology Comparison of Millimeter-wave CMOS YCOs," frequency range and has a tuning range of 10.5%. The VCO IEEE Compound Semiconductor Integrated Circuit Symposium, pp. 55­ has been implemented in a CMOS 65nm process. The phase 58, Nov 2006. [8] D. Huang, W. Hant, N. Wang, T. Ku, Q. Gu, R. Wong, and M. Chang, "A noise varies from -85dBclHz to -79dBclHz. Al the latter point 60GHz CMOS YCO Using On-Chip Resonator with Embedded Artificial the Miller tuning current mirror contributed approximately Dielectric for Side, Loss and Noise Reduction," ISSCC Digest, pp. 314­ 60% of the tolal noise. The circuit makes use of an actively 315, Feb 2006.