Bandwidth Extension of High-Gain CMOS Stages Using Active Negative Capacitance

David J. Comer, Fellow, IEEE, Donald T. Comer, Jonathan B. Perkins, Kevin D. Clark, Adrian P. C. Genz

Department of Electrical and Computer Engineering

Brigham Young University

Provo, Utah, USA

approaching two orders of magnitude are observed in Abstract—A method of extending the bandwidth of a CMOS simulations. Circuit designs are simulated with Spectre Spice amplifier by the use of a negative capacitance circuit is presented. (Cadence), using TSMC .25-micron CMOS device models. Nonideal effects of the negative capacitance circuit are combined Two high gain amplifiers are first designed and simulated. with the one-pole amplifier response resulting in a two-pole The bandwidth extension technique is then applied to extend response. Proper selection of element values leads to a maximally-flat magnitude response with a significantly improved the bandwidth of each amplifier. bandwidth for the amplifier. Specific guidelines are given for the design of an effective negative capacitance circuit. Simulations II. GENERATION OF NEGATIVE CAPACITANCE using TSMC 0.25-micron device models show a bandwidth improvement approaching two orders of magnitude in a typical Typically, high-gain MOS stages use active loads to CMOS high-gain stage. generate large values of load resistance, RL. The bandwidth is then

I. INTRODUCTION 1 RESENT day electronic circuits continue to have f = (1) 3−dB π P frequency limitations primarily due to parasitic 2 RLCL capacitances. A large capacitance, such as IC pad where C is the parasitic capacitance in parallel with R . capacitance, may limit the speed of a circuit even if its L L associated node resistance is small. Likewise, a very small Although a second pole could result from the input capacitance will limit the speed of a circuit if its associated capacitance and resistance of the stage, values of RL sufficient node resistance is large. Continual improvement in the to maximize gain lead to a dominant pole given by (1). In fabrication process is reducing these parasitic capacitances; order to increase this pole frequency, a negative capacitance could be used to decrease the value of C . however, parasitic capacitances still limit high frequency L circuit performance in many cases. In theory, negative capacitance can be generated using the Negative capacitance circuitry provides a method for Miller effect and an ideal inverting amplifier with no output minimizing the effects of parasitic capacitances by partial impedance or frequency limitation. A more practical circuit is cancellation. Negative capacitance is generated by adding shown in Fig. 1. This stage is designed to cancel some portion active circuitry to a node with excessive parasitic capacitance. of the load capacitance for the amplifying stage plus the input Others have proposed this type of circuitry for several uses capacitance to the negative capacitance generator (NCG) including: improvement of bus switching speed [1], circuit. The resistance, R1, represents the output resistance cancellation of MESFET optical receiver input capacitance and the capacitance, C1, is the parasitic output capacitance of [2], cancellation of input capacitance of differential stages [3], the NCG circuit. These two elements account for the and improvement of op amp unity gain frequency and phase frequency behavior of the NCG. The capacitance C bridging margin [4]. the amplifier’s output along with the gain A create the The concept of negative capacitance is applied to high-gain negative capacitance. When the NCG circuit connects to the MOS stages in this work. Bandwidth improvement output node of the amplifier the voltage gain is proportional to the impedance at this node,

This means that a node with a small upper corner frequency will exhibit a great amount of improvement when loaded by a negative capacitance circuit that maximizes z1. Amplifying stages that use large active loads to achieve high gain can experience large increases in bandwidth. To show how to maximize z1 it is helpful to look at its inverse, given by

Fig. 1. Negative Capacitance stage used for canceling a node capacitance. 1 = R C + R C (6) v 1 z 1 1 1 Z = out = * 1 i R (CC +C C +CC ) in 1 L L 1 1 1+ sR (C + C ) 1 1 (2) Designing a fast amplifier for the negative capacitance − + + + 2 (1 A)CR R C R (C C ) 1 circuit will minimize the term R C . It is seen from (6) that s + s L L L 1 1 + 1 1  + +  + +  R1RL (CCL CLC1 CC1)  R1RL (CCL CLC1 CC1) minimizing the term R1C is also important. Specifically, if the feedback capacitance C is much larger than C1, the bandwidth Before adding the NCG, the impedance of the amplifier improvement will be limited by the product of R1 and C. output node had a single pole and a low-frequency value of Canceling a large capacitance will require a large feedback RL. capacitor C. This implies that better results will be obtained if After adding the NCG, the low frequency impedance is still the bandwidth of the amplifier stage is limited by a large equal to RL, but there are now two poles and one zero rather resistance RL and small capacitance CL. than a single pole. If the magnitude of the zero is considerably Because the high gain of a high-gain stage is formed by a larger than that of the poles it can be neglected. The large output resistance, the bandwidth can be dramatically denominator can be expressed in standard form as improved with negative capacitance. The output resistance ω combines with the associated parasitic device capacitance, = 2 + 0 + ω 2 D s s 0 (3) which is usually small, to create a low upper corner frequency Q for the stage. As seen later, the bandwidth of such a stage can be improved by a factor exceeding 50. Using (2) and (3) allows Q to be written as If a large value of output capacitance is to be cancelled, varying the gain of the negative capacitance stage allows the + + feedback capacitance to be smaller. For an ideal NCG with no R1RL (CCL CLC1 CC1) Q = (4) parasitics, that is, zero values of R and C , the negative − + + + 1 1 (1 A)CRL RLCL R1(C C1) capacitance generated is

RL and CL are associated with the high gain amplifier output = CNEG (1 - A)C (7) node and are constant. R1 and C1 are associated with the negative capacitance circuit and determined by the negative capacitance gain stage implementation. The value of Q can Solving for C gives best be controlled by the choices of C and A, to which Q is C NEG highly sensitive. For a wideband response, a good choice for C = (8) Q is that value resulting in a maximally-flat magnitude 1- A response (MFMR). This leads to the widest possible bandwidth with no peaking within the pass band. In this case, Because (7) results from using an ideal amplifier for the NCG, CNEG functions as an approximate value of the negative a value of Q = 1/ 2 leads to MFMR. The improved 3-dB capacitance desired. If CNEG = -10fF is desired for bandwidth is now given by cancellation of CL, then A=2 requires that C be 10 fF. If A=3 1 however, the required value of C is 5 fF. f − = (5) Increasing the gain A will likely cause the amplifier of the 3 dB π + + 2 R1RL (CCL CLC1 CC1) NCG circuit to be slower due to the gain-bandwidth tradeoff The extended bandwidth from (5) can be many times greater typically present in all amplifiers. Inspection of (6) shows that than the original bandwidth given by (1). increasing R1 to increase the gain A will increase the first term and could decrease the second term by decreasing C. If III. DESIGN CONSIDERATIONS the second term in (6) is much greater than the first, then this As seen earlier, the negative capacitance circuitry will be increase in gain could be beneficial to maximize z1. Typically, if the capacitance to be cancelled is similar in more effective if designed to maximize the zero, z1, in (2). magnitude to C1, then A=2 is a good choice for amplifier gain. The greater the ratio between z1 and the uncompensated node bandwidth, the greater the percentage of improvement will be. If a much larger capacitance is to be cancelled however, then a

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from Table I will be used to find the value of C in (4) to produce a maximally flat magnitude response.

V. SIMULATION OF NEGATIVE CAPACITANCE CIRCUITRY The design of high gain CMOS amplifier stages is a widely covered topic. Stages such as the cascode circuit [5], composite cascode [6], and others are often used when high gain is desired. It has been shown how parameters such as device dimensions and inversion level can be optimized for high gains [7-8]. In each case, the benefit of a high amplifier gain is typically accompanied by the disadvantage of a low bandwidth. The low bandwidth is due to the parasitic Fig. 2. Differential pair amplifier for negative capacitance generation. slightly larger value of A may be useful in maximizing z1, and capacitance appearing in parallel with the very large output likewise the performance of the negative capacitance. resistance. High gain CMOS stages will therefore benefit significantly from adding a negative capacitance to the output IV. SIMULATION OF NEGATIVE CAPACITANCE CIRCUITRY node. One implementation of a negative capacitance circuit is the differential pair of Fig. 2. The low frequency gain of this circuit is given by

1 gm (gm + gmb ) 1 2 2 gm Avv = 3 , (9) (gm + gmb )rds + + + 2 2 2 gds1 gm1 gmb1 + 1 rds2 gm 3 For RD<< rds1,2, gds << gm, and gm1=gm2 the gain becomes 1 gm 1 gm A ≈ 3 (10) VV 2

When designed to have a small positive gain, this stage has several benefits. It displays low input capacitance by eliminating the Miller effect on the input stage. The output Fig. 3. High gain cascode differential pair. capacitance is small when the device sizes are small. Due to the low gain requirement, the output resistance can also be A. Bandwidth Extension in a High Gain Cascode Stage small, especially if the transconductance value is designed to The differential cascode amplifier of Fig. 3 was first be relatively high. This amplifier has a response that can be simulated alone. Then the cascode amplifier was loaded by approximated as a one-pole system, with the dominant pole the negative capacitance amplifier to determine CL. The due to the output resistance and capacitance. In this case, pertinent results are shown in Table II. equations developed in the previous sections are valid. The stage from Fig. 2 was designed using TSMC's 0.25- TABLE II micron technology for Wp = 3, 2.5, 2, and 1.5 microns. These KEY RESULTS FROM SIMULATION OF CIRCUIT IN FIG. 3. different widths provided varying gains. Vbias will be the Amb 12,800 V/V quiescent voltage of the output node of the high-gain stage. f3dB Cascode Amp 65.7 kHz Table I summarizes the results obtained from the design of f3dB Loaded Cascode Amp 50.1 kHz this amplifier. Once RL and CL are determined, the values RL 34.5 MΩ TABLE I CL unloaded 70.2 fF KEY RESULTS FROM SIMULATION OF CIRCUIT IN FIG. 2.

WP A R1 C1 CL loaded 92.0 fF uM V/V KΩ fF

3 2.18 8.65 24.2 The results form Table I and Table II were inserted into (4) 2.5 2.45 9.40 22.7 to solve for the feedback capacitance C that produces a 2 2.84 10.5 21.2 maximally flat magnitude response as tabulated in Table III. 1.5 3.42 11.95 19.7 630 4

The feedback capacitor was then added between the outputs of the differential cascode amplifier and the negative capacitance TABLE V amplifier, as shown in Fig. 3. SIMULATION OF CIRCUIT IN Table III gives the feedback capacitor value, bandwidth FIG. 4 AFTER BANDWIDTH EXTENSION. after extension, and bandwidth improvement for several Itail 1uA 2uA values of WP. The midband gain of the cascode stage remained constant at 12,800 V/V. The best bandwidth C 28.4 fF 29.0 fF improvement was displayed by the smallest PMOS width, f3dB old 17.8 kHz 42.9 kHz which had the largest gain. The differential cascode amplifier f3dB extended 1.37 MHz 2.17 MHz bandwidth was improved by a factor of 54. Improvement Factor 77 50 TABLE III value of feedback RESULTS FROM THE CIRCUIT IN

FIG. 3 AFTER BANDWIDTH EXTENSION. capacitance, C, was found to result in a maximally flat gain WP C f3dB extended Improvement response. Table V gives the value of feedback capacitance, uM fF MHz Factor bandwidth of the cascode stage before extension, bandwidth 3 76.38 2.63 39 after extension, and bandwidth improvement factor. The 2.5 61.92 2.66 39 bandwidth of the high gain composite cascade amplifier was 2 48.78 2.81 43 1.5 37.2 3.53 54 extended from 17.8 kHz to 1.37 MHz, a factor of 77.

B. Composite Cascode Stage VI. CONCLUSIONS The composite cascode stage of Fig. 4 was reported in [5] to A negative capacitance circuit can be used to minimize achieve a very high voltage gain by careful choice of device critical node capacitance to increase the bandwidth of MOS operating regions. This stage was simulated using Cadence, amplifiers. This method is particularly well-suited to high- where M1 and M2 were operating in the active region, but M2 gain amplifiers such as cascode stages. In such cases, the operated in the subthreshold region. The pertinent results factor of bandwidth extension ranges from one to two orders obtained during simulation are shown in Table IV. of magnitude over the uncompensated amplifier. While future work is being directed toward automatic tuning TABLE IV schemes, the use of negative capacitance in amplifier KEY RESULTS FROM SIMULATION OF CIRCUIT IN FIG. 4. bandwidth extension appears promising. Itail 1uA 2uA Amb 3079 V/V 2040 V/V REFERENCES f (before loading) 17.8 kHz 42.9 kHz [1] M. Shoji and R. M. Rolfe, "Negative capacitance bus terminator for 3dB Improving the switching speed of a microcomputer databus," IEEE J. f3dB (after loading) 12.4 kHz 30.4 kHz Solid-State Circuits, vol. 20, Issue 4, pp. 828-832,Feb.1985. [2] Jason D Drew, Izzat Z Darwazeh and Brett Wilson, "Generation of RL 175.5 MΩ 69.5 MΩ negative capacitance in a common gate MESFET stage and application C 73.25 fF 75.4 fF to optical receiver design at microwave frequencies," IEE Colloquium L on Wideband Circuits, Modeling and Techniques, 10 May 1996 Page(s):2/1 - 2/5 The amplifier from Fig. 2 was used along with a feedback [3] A. B. Grebene, Bipolar and MOS Integrated Circuit Design, New York: Wiley, 2003 (1972), ch. 8. capacitor to generate a negative capacitance at the output node [4] B. Shem-Tov, M. Kozak, and E. G. Friedman, "A high-speed CMOS op- of the amplifier in Fig. 4. The PMOS width was chosen to be amp design technique using negative Miller capacitance," Proceedings 1.5microns, as this device width showed the highest of 2004 11th IEEE International Conference of Electronics, Circuits and Systems, pp. 623-626, Dec. 2004. performance in the differential cascode simulations. The [5] P. R. Gray, P. J. Hurst, S. H. Lewis, and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 4th Ed., New York: Wiley, 2001, ch. 3. [6] D. J. Comer, D. T. Comer, and Craig S. Petrie, "The Utility of the composite cascode in analog CMOS design," Int. J. Electronics, vol. 91, pp. 491-502, August 2004. [7] D .J. Comer and D. T. Comer, "Using the weak inversion region to optimize input stage design of op amps", IEEE Transactions on Circuits and Systems II, Vol. 51, No. 1, pp. 8-14, January 2004. [8] Timothy M. Hollis, D. J. Comer, and D. T. Comer, "Optimization of MOS amplifier performance through channel length and inversion level selection", IEEE Transactions on Circuits and Systems II, Vol. 52, No. 9, pp. 545-549, September 2005.

Fig. 4. Composite cascode stage.

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