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Design, Fabrication, and Characterization of Three‑Dimensional Embedded Capacitor in Through‑Silicon Via This document is downloaded from DR‑NTU (https://dr.ntu.edu.sg) Nanyang Technological University, Singapore. Design, fabrication, and characterization of three‑dimensional embedded capacitor in through‑silicon via Lin, Ye 2019 Lin, Y. (2019). Design, fabrication, and characterization of three‑dimensional embedded capacitor in through‑silicon via. Doctoral thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/102666 https://doi.org/10.32657/10220/48586 Downloaded on 28 Sep 2021 02:52:36 SGT ( O n th e S p ine) DESIGN, FA BRICATION, AND CHARACTERIZATION OF 3 DESIGN, FABRICATION, AND CHARACTERIZATION OF THREE-DIMENSIONAL EMBEDDED CAPACITOR IN THROUGH-SILICON VIA - D EMBEDDED CAPACITOR IN TSV LIN YE LIN YE SCHOOL OF ELECTRICAL AND ELECTRONIC ENGINEERING 2019 2019 DESIGN, FABRICATION, AND CHARACTERIZATION OF THREE-DIMENSIONAL EMBEDDED CAPACITOR IN THROUGH-SILICON VIA LIN YE (B. Eng., Nanyang Technological University) SCHOOL OF ELECTRICAL AND ELECTRONIC ENGINEERING A thesis submitted to the Nanyang Technological University in partial fulfillment of the requirement for the degree of Doctor of Philosophy 2019 Statement of Originality I hereby certify that the work embodied in this thesis is the result of original research, is free of plagiarised materials, and has not been submitted for a higher degree to any other University or Institution. 28 May 2019 Date Lin Ye Supervisor Declaration Statement I have reviewed the content and presentation style of this thesis and declare it is free of plagiarism and of sufficient grammatical clarity to be examined. To the best of my knowledge, the research and writing are those of the candidate except as acknowledged in the Author Attribution Statement. I confirm that the investigations were conducted in accord with the ethics policies and integrity standards of Nanyang Technological University and that the research data are presented honestly and without prejudice. 28 May 2019 Date Tan Chuan Seng Authorship Attribution Statement This thesis contains material from 6 papers published in the following peer-reviewed journals and from papers accepted at conferences in which I am listed as an author. Chapter 3-5 are published in the following papers: [1] Y. Lin and C. S. Tan, "Modeling, Fabrication, and Characterization of 3-D Capacitor Embedded in Through-Silicon Via," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 8, no. 9, pp. 1524-1532, Sept. 2018 [2] Y. Lin and C. S. Tan, “Leakage current conduction mechanism of three- dimensional capacitors embedded in through-silicon vias,” Japanese Journal of Applied Physics, vol. 57, no. 7S2, p. 07MF01, Jul. 2018. [3] Y. Lin and C. S. Tan, “Dielectric Quality of 3-D Capacitor Embedded in Through- Silicon Via (TSV),” in 2018 IEEE 68th Electronic Components and Technology Conference (ECTC), 2018. [4] Y. Lin and C. S. Tan, “Leakage Current Conduction Mechanism of 3-D Capacitor Embedded in Through-Silicon Via (TSV),” in Advanced Metallization Conference 2017: 27th Asian Session, 2017, p. 12. [5] Y. Lin and C. S. Tan, “Physical and Electrical Characterization of 3-D Embedded Capacitor: A High-Density MIM Capacitor Embedded in TSV,” in 2017 IEEE 67th Electronic Components and Technology Conference (ECTC), 2017, pp. 1956–1961. [6] Y. Lin and C. Seng Tan, “Through-substrate via (TSV) with embedded capacitor as an on-chip energy storage element,” in 2016 IEEE International 3-D Systems Integration Conference (3-DIC), 2016, pp. 1–4. The contributions of the co-authors are as follows: • Assoc Prof Tan Chuan Seng provided the initial project direction and edited the manuscript drafts. • I prepared the manuscript drafts. • I performed all the design, modeling, fabrication, and characterization of 3-D embedded capacitors. 28 May 2019 Date Lin Ye Acknowledgement Foremost, I would like to express my greatest gratitude towards my supervisor Professor Tan Chuan Seng. This thesis would not have been completed without his patient guidance and continuous encouragement. The door to his office was always open whether I was stuck in the middle of the research process or wandering between career choices. I am truly honored to have worked with a dynamic research group, where every group member was versatile and helpful. I am grateful to Lee Yong Hean, Chua Shen Lin, Dr. Anantha, Lin Yiding, Wei Mengyao, Dr. Lee Kwang Hong, Bao Shuyu, Dr. Zhang Lin, Dr. Peng Lan, Marvin Chan, Zhu Ye, and Simon Goh. I benefitted greatly from their microfabrication experience and inspiring conversations. They are not only excellent colleagues but also life-long friends. The affable technicians in both Clean Room 1 (CR1) and Clean Room 2 (CR2) did a great job of training and keeping the equipment running in good condition. I owe many thanks to Dr. Chong Gang Yih, Ngo Ling Ling, Chung Kowk Fai, and Yang Xiaohong in CR1 and to Mohamad Shamsul Bin Mohamad and Zulkiflee Bin Abdullah in CR2. They extended their help and technical guidance in the course of my research project. My thesis advisor committee members, Professor Pang Hock Lye and Professor Kim Tae Hyoung, provided me with precious insight into research and industry. Many other professors have had an impact on my education via their excellent lectures. They are Professor Kantisara Pita, Professor Chen Tupei, Professor Tang Xiaohong, Professor Wang Hong, and Professor Wong Kin Shun. I am also thankful to Nanyang Technological University for a 4-year generous research scholarship to sponsor my PhD study. Last but not least, I thank my family, including my parents Lin Jie and Cai Jing Fang and my wife Qian Jin, for their unconditional and everlasting love. Their support gave me the strength to face the challenges and tackle the problems in the research. Table of Contents Acknowledgement I Table of Contents I Executive Summary V List of Tables IX List of Figures XI Chapter 1 Introduction 1 1.1 Background ........................................................................................... 1 1.2 Motivation for the Development of Thin Film-Based Passive Integration Technology ........................................................................ 3 1.3 Objectives ............................................................................................. 5 1.4 Major Contribution of the Thesis.......................................................... 6 1.5 Organization of the Thesis .................................................................... 7 1.6 References ............................................................................................. 8 Chapter 2 A Review on Integrated Capacitor Technologies for Three- Dimensional Integrated Circuits 11 2.1 Three-Dimensional Integrated Circuit ................................................ 11 Three-Dimensional Integration ..................................................... 11 Through-Silicon Via ..................................................................... 14 Power Integrity ............................................................................. 23 2.2 Integrated Capacitor Technologies ..................................................... 25 Laminate-based Integrated Capacitor ........................................... 25 Low Temperature Co-Fired Ceramic-Based Integrated Capacitor 26 I Thin film-based passive integrated capacitor ............................... 27 2.3 Summary ............................................................................................. 29 References ..................................................................................................... 30 Chapter 3 Design and Modeling of the Three-Dimensional Embedded Capacitor 39 3.1 Introduction ......................................................................................... 39 3.2 Proposed “Three-dimensional Embedded Capacitor” ........................ 40 3.3 Design of Three-Dimensional Embedded Capacitor .......................... 43 3.4 Electrical Modeling of Three-Dimensional Embedded Capacitor Using the Analytical Method ........................................................................ 47 3.5 Thermo-Mechanical Simulation of Three-Dimensional Embedded Capacitor Using Finite Element Analysis .......................................... 53 3.6 Summary ............................................................................................. 61 References ..................................................................................................... 62 Chapter 4 Fabrication of Three-Dimensional Embedded Capacitor 67 4.1 Introduction ......................................................................................... 67 4.2 Photomask Design .............................................................................. 68 4.3 Process Flow ....................................................................................... 71 4.4 Process Control and Optimization ...................................................... 74 Trench Formation ......................................................................... 74 Deposition of Stacked Layers ....................................................... 83 Patterning of the Top and Bottom Electrodes ............................... 91 4.5 Summary ............................................................................................. 93 References ..................................................................................................... 94 II Chapter 5 Electrical Characterization of Three-Dimensional Embedded Capacitor 99 5.1 Introduction ........................................................................................
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