DOCSLIB.ORG

Design, Fabrication, and Characterization of Three‑Dimensional Embedded Capacitor in Through‑Silicon Via

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text

Load more

This document is downloaded from DR‑NTU (https://dr.ntu.edu.sg) Nanyang Technological University, Singapore. Design, fabrication, and characterization of three‑dimensional embedded capacitor in through‑silicon via Lin, Ye 2019 Lin, Y. (2019). Design, fabrication, and characterization of three‑dimensional embedded capacitor in through‑silicon via. Doctoral thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/102666 https://doi.org/10.32657/10220/48586 Downloaded on 28 Sep 2021 02:52:36 SGT ( O n th e S p ine) DESIGN, FA BRICATION, AND CHARACTERIZATION OF 3 DESIGN, FABRICATION, AND CHARACTERIZATION OF THREE-DIMENSIONAL EMBEDDED CAPACITOR IN THROUGH-SILICON VIA - D EMBEDDED CAPACITOR IN TSV LIN YE LIN YE SCHOOL OF ELECTRICAL AND ELECTRONIC ENGINEERING 2019 2019 DESIGN, FABRICATION, AND CHARACTERIZATION OF THREE-DIMENSIONAL EMBEDDED CAPACITOR IN THROUGH-SILICON VIA LIN YE (B. Eng., Nanyang Technological University) SCHOOL OF ELECTRICAL AND ELECTRONIC ENGINEERING A thesis submitted to the Nanyang Technological University in partial fulfillment of the requirement for the degree of Doctor of Philosophy 2019 Statement of Originality I hereby certify that the work embodied in this thesis is the result of original research, is free of plagiarised materials, and has not been submitted for a higher degree to any other University or Institution. 28 May 2019 Date Lin Ye Supervisor Declaration Statement I have reviewed the content and presentation style of this thesis and declare it is free of plagiarism and of sufficient grammatical clarity to be examined. To the best of my knowledge, the research and writing are those of the candidate except as acknowledged in the Author Attribution Statement. I confirm that the investigations were conducted in accord with the ethics policies and integrity standards of Nanyang Technological University and that the research data are presented honestly and without prejudice. 28 May 2019 Date Tan Chuan Seng Authorship Attribution Statement This thesis contains material from 6 papers published in the following peer-reviewed journals and from papers accepted at conferences in which I am listed as an author. Chapter 3-5 are published in the following papers: [1] Y. Lin and C. S. Tan, "Modeling, Fabrication, and Characterization of 3-D Capacitor Embedded in Through-Silicon Via," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 8, no. 9, pp. 1524-1532, Sept. 2018 [2] Y. Lin and C. S. Tan, “Leakage current conduction mechanism of three- dimensional capacitors embedded in through-silicon vias,” Japanese Journal of Applied Physics, vol. 57, no. 7S2, p. 07MF01, Jul. 2018. [3] Y. Lin and C. S. Tan, “Dielectric Quality of 3-D Capacitor Embedded in Through- Silicon Via (TSV),” in 2018 IEEE 68th Electronic Components and Technology Conference (ECTC), 2018. [4] Y. Lin and C. S. Tan, “Leakage Current Conduction Mechanism of 3-D Capacitor Embedded in Through-Silicon Via (TSV),” in Advanced Metallization Conference 2017: 27th Asian Session, 2017, p. 12. [5] Y. Lin and C. S. Tan, “Physical and Electrical Characterization of 3-D Embedded Capacitor: A High-Density MIM Capacitor Embedded in TSV,” in 2017 IEEE 67th Electronic Components and Technology Conference (ECTC), 2017, pp. 1956–1961. [6] Y. Lin and C. Seng Tan, “Through-substrate via (TSV) with embedded capacitor as an on-chip energy storage element,” in 2016 IEEE International 3-D Systems Integration Conference (3-DIC), 2016, pp. 1–4. The contributions of the co-authors are as follows: • Assoc Prof Tan Chuan Seng provided the initial project direction and edited the manuscript drafts. • I prepared the manuscript drafts. • I performed all the design, modeling, fabrication, and characterization of 3-D embedded capacitors. 28 May 2019 Date Lin Ye Acknowledgement Foremost, I would like to express my greatest gratitude towards my supervisor Professor Tan Chuan Seng. This thesis would not have been completed without his patient guidance and continuous encouragement. The door to his office was always open whether I was stuck in the middle of the research process or wandering between career choices. I am truly honored to have worked with a dynamic research group, where every group member was versatile and helpful. I am grateful to Lee Yong Hean, Chua Shen Lin, Dr. Anantha, Lin Yiding, Wei Mengyao, Dr. Lee Kwang Hong, Bao Shuyu, Dr. Zhang Lin, Dr. Peng Lan, Marvin Chan, Zhu Ye, and Simon Goh. I benefitted greatly from their microfabrication experience and inspiring conversations. They are not only excellent colleagues but also life-long friends. The affable technicians in both Clean Room 1 (CR1) and Clean Room 2 (CR2) did a great job of training and keeping the equipment running in good condition. I owe many thanks to Dr. Chong Gang Yih, Ngo Ling Ling, Chung Kowk Fai, and Yang Xiaohong in CR1 and to Mohamad Shamsul Bin Mohamad and Zulkiflee Bin Abdullah in CR2. They extended their help and technical guidance in the course of my research project. My thesis advisor committee members, Professor Pang Hock Lye and Professor Kim Tae Hyoung, provided me with precious insight into research and industry. Many other professors have had an impact on my education via their excellent lectures. They are Professor Kantisara Pita, Professor Chen Tupei, Professor Tang Xiaohong, Professor Wang Hong, and Professor Wong Kin Shun. I am also thankful to Nanyang Technological University for a 4-year generous research scholarship to sponsor my PhD study. Last but not least, I thank my family, including my parents Lin Jie and Cai Jing Fang and my wife Qian Jin, for their unconditional and everlasting love. Their support gave me the strength to face the challenges and tackle the problems in the research. Table of Contents Acknowledgement I Table of Contents I Executive Summary V List of Tables IX List of Figures XI Chapter 1 Introduction 1 1.1 Background ........................................................................................... 1 1.2 Motivation for the Development of Thin Film-Based Passive Integration Technology ........................................................................ 3 1.3 Objectives ............................................................................................. 5 1.4 Major Contribution of the Thesis.......................................................... 6 1.5 Organization of the Thesis .................................................................... 7 1.6 References ............................................................................................. 8 Chapter 2 A Review on Integrated Capacitor Technologies for Three- Dimensional Integrated Circuits 11 2.1 Three-Dimensional Integrated Circuit ................................................ 11 Three-Dimensional Integration ..................................................... 11 Through-Silicon Via ..................................................................... 14 Power Integrity ............................................................................. 23 2.2 Integrated Capacitor Technologies ..................................................... 25 Laminate-based Integrated Capacitor ........................................... 25 Low Temperature Co-Fired Ceramic-Based Integrated Capacitor 26 I Thin film-based passive integrated capacitor ............................... 27 2.3 Summary ............................................................................................. 29 References ..................................................................................................... 30 Chapter 3 Design and Modeling of the Three-Dimensional Embedded Capacitor 39 3.1 Introduction ......................................................................................... 39 3.2 Proposed “Three-dimensional Embedded Capacitor” ........................ 40 3.3 Design of Three-Dimensional Embedded Capacitor .......................... 43 3.4 Electrical Modeling of Three-Dimensional Embedded Capacitor Using the Analytical Method ........................................................................ 47 3.5 Thermo-Mechanical Simulation of Three-Dimensional Embedded Capacitor Using Finite Element Analysis .......................................... 53 3.6 Summary ............................................................................................. 61 References ..................................................................................................... 62 Chapter 4 Fabrication of Three-Dimensional Embedded Capacitor 67 4.1 Introduction ......................................................................................... 67 4.2 Photomask Design .............................................................................. 68 4.3 Process Flow ....................................................................................... 71 4.4 Process Control and Optimization ...................................................... 74 Trench Formation ......................................................................... 74 Deposition of Stacked Layers ....................................................... 83 Patterning of the Top and Bottom Electrodes ............................... 91 4.5 Summary ............................................................................................. 93 References ..................................................................................................... 94 II Chapter 5 Electrical Characterization of Three-Dimensional Embedded Capacitor 99 5.1 Introduction ........................................................................................
Recommended publications
  • Run Capacitor Info-98582

    Run Capacitor Info-98582

    Run Cap Quiz-98582_Layout 1 4/16/15 10:26 AM Page 1 ® Run Capacitor Info WHAT IS A CAPACITOR? Very simply, a capacitor is a device that stores and discharges electrons. While you may hear capacitors referred to by a variety of names (condenser, run, start, oil, etc.) all capacitors are comprised of two or more metallic plates separated by an insulating material called a dielectric. PLATE 1 PLATE 2 A very simple capacitor can be made with two plates separated by a dielectric, in this PLATE 1 PLATE 2 case air, and connected to a source of DC current, a battery. Electrons will flow away from plate 1 and collect on plate 2, leaving it with an abundance of electrons, or a “charge”. Since current from a battery only flows one way, the capacitor plate will stay BATTERY + – charged this way unless something causes current flow. If we were to short across the plates with a screwdriver, the resulting spark would indicate the electrons “jumping” from plate 2 to plate 1 in an attempt to equalize. As soon as the screwdriver is removed, plate 2 will again collect a PLATE 1 PLATE 2 charge. + BATTERY – Now let’s connect our simple capacitor to a source of AC current and in series with the windings of an electric motor. Since AC current alternates, first one PLATE 1 PLATE 2 MOTOR plate, then the other would be charged and discharged in turn. First plate 1 is charged, then as the current reverses, a rush of electrons flow from plate 1 to plate 2 through the motor windings.
  • Switched-Capacitor Circuits

    Switched-Capacitor Circuits

    Switched-Capacitor Circuits David Johns and Ken Martin University of Toronto ([email protected]) ([email protected]) University of Toronto 1 of 60 © D. Johns, K. Martin, 1997 Basic Building Blocks Opamps • Ideal opamps usually assumed. • Important non-idealities — dc gain: sets the accuracy of charge transfer, hence, transfer-function accuracy. — unity-gain freq, phase margin & slew-rate: sets the max clocking frequency. A general rule is that unity-gain freq should be 5 times (or more) higher than the clock-freq. — dc offset: Can create dc offset at output. Circuit techniques to combat this which also reduce 1/f noise. University of Toronto 2 of 60 © D. Johns, K. Martin, 1997 Basic Building Blocks Double-Poly Capacitors metal C1 metal poly1 Cp1 thin oxide bottom plate C1 poly2 Cp2 thick oxide C p1 Cp2 (substrate - ac ground) cross-section view equivalent circuit • Substantial parasitics with large bottom plate capacitance (20 percent of C1) • Also, metal-metal capacitors are used but have even larger parasitic capacitances. University of Toronto 3 of 60 © D. Johns, K. Martin, 1997 Basic Building Blocks Switches I I Symbol n-channel v1 v2 v1 v2 I transmission I I gate v1 v p-channel v 2 1 v2 I • Mosfet switches are good switches. — off-resistance near G: range — on-resistance in 100: to 5k: range (depends on transistor sizing) • However, have non-linear parasitic capacitances. University of Toronto 4 of 60 © D. Johns, K. Martin, 1997 Basic Building Blocks Non-Overlapping Clocks I1 T Von I I1 Voff n – 2 n – 1 n n + 1 tTe delay 1 I fs { --- delay V 2 T on I Voff 2 n – 32e n – 12e n + 12e tTe • Non-overlapping clocks — both clocks are never on at same time • Needed to ensure charge is not inadvertently lost.
  • Kirchhoff's Laws in Dynamic Circuits

    Kirchhoff's Laws in Dynamic Circuits

    Kirchhoff’s Laws in Dynamic Circuits Dynamic circuits are circuits that contain capacitors and inductors. Later we will learn to analyze some dynamic circuits by writing and solving differential equations. In these notes, we consider some simpler examples that can be solved using only Kirchhoff’s laws and the element equations of the capacitor and the inductor. Example 1: Consider this circuit Additionally, we are given the following representations of the voltage source voltage and one of the resistor voltages: ⎧⎧10 V fortt<< 0 2 V for 0 vvs ==⎨⎨and 1 −5t ⎩⎩20 V forte>+ 0 8 4 V fort> 0 We wish to express the capacitor current, i 2 , as a function of time, t. Plan: First, apply Kirchhoff’s voltage law (KVL) to the loop consisting of the source, resistor R1 and the capacitor to determine the capacitor voltage, v 2 , as a function of time, t. Next, use the element equation of the capacitor to determine the capacitor current as a function of time, t. Solution: Apply Kirchhoff’s voltage law (KVL) to the loop consisting of the source, resistor R1 and the capacitor to write ⎧ 8 V fort < 0 vvv12+−=ss0 ⇒ v2 =−= vv 1⎨ −5t ⎩16− 8et V for> 0 Use the element equation of the capacitor to write ⎧ 0 A fort < 0 dv22 dv ⎪ ⎧ 0 A fort < 0 iC2 ==0.025 =⎨⎨d −5t =−5t dt dt ⎪0.025() 16−> 8et for 0 ⎩1et A for> 0 ⎩ dt 1 Example 2: Consider this circuit where the resistor currents are given by ⎧⎧0.8 A fortt<< 0 0 A for 0 ii13==⎨⎨−−22ttand ⎩⎩0.8et−> 0.8 A for 0 −0.8 e A fort> 0 Express the inductor voltage, v 2 , as a function of time, t.

  • Three-Dimensional Integrated Circuit Design: EDA, Design And

    Integrated Circuits and Systems Series Editor Anantha Chandrakasan, Massachusetts Institute of Technology Cambridge, Massachusetts For other titles published in this series, go to http://www.springer.com/series/7236 Yuan Xie · Jason Cong · Sachin Sapatnekar Editors Three-Dimensional Integrated Circuit Design EDA, Design and Microarchitectures 123 Editors Yuan Xie Jason Cong Department of Computer Science and Department of Computer Science Engineering University of California, Los Angeles Pennsylvania State University [email protected] [email protected] Sachin Sapatnekar Department of Electrical and Computer Engineering University of Minnesota [email protected] ISBN 978-1-4419-0783-7 e-ISBN 978-1-4419-0784-4 DOI 10.1007/978-1-4419-0784-4 Springer New York Dordrecht Heidelberg London Library of Congress Control Number: 2009939282 © Springer Science+Business Media, LLC 2010 All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights. Printed on acid-free paper Springer is part of Springer Science+Business Media (www.springer.com) Foreword We live in a time of great change.
  • Capacitive Voltage Transformers: Transient Overreach Concerns and Solutions for Distance Relaying

    Capacitive Voltage Transformers: Transient Overreach Concerns and Solutions for Distance Relaying

    Capacitive Voltage Transformers: Transient Overreach Concerns and Solutions for Distance Relaying Daqing Hou and Jeff Roberts Schweitzer Engineering Laboratories, Inc. Revised edition released October 2010 Previously presented at the 1996 Canadian Conference on Electrical and Computer Engineering, May 1996, 50th Annual Georgia Tech Protective Relaying Conference, May 1996, and 49th Annual Conference for Protective Relay Engineers, April 1996 Previous revised edition released July 2000 Originally presented at the 22nd Annual Western Protective Relay Conference, October 1995 CAPACITIVE VOLTAGE TRANSFORMERS: TRANSIENT OVERREACH CONCERNS AND SOLUTIONS FOR DISTANCE RELAYING Daqing Hou and Jeff Roberts Schweitzer Engineering Laboratories, Inc. Pullman, W A USA ABSTRACT Capacitive Voltage Transformers (CVTs) are common in high-voltage transmission line applications. These same applications require fast, yet secure protection. However, as the requirement for faster protective relays grows, so does the concern over the poor transient response of some CVTs for certain system conditions. Solid-state and microprocessor relays can respond to a CVT transient due to their high operating speed and iflCreased sensitivity .This paper discusses CVT models whose purpose is to identify which major CVT components contribute to the CVT transient. Some surprises include a recom- mendation for CVT burden and the type offerroresonant-suppression circuit that gives the least CVT transient. This paper also reviews how the System Impedance Ratio (SIR) affects the CVT transient response. The higher the SIR, the worse the CVT transient for a given CVT . Finally, this paper discusses improvements in relaying logic. The new method of detecting CVT transients is more precise than past detection methods and does not penalize distance protection speed for close-in faults.
  • Aluminum Electrolytic Vs. Polymer – Two Technologies – Various Opportunities

    Aluminum Electrolytic Vs. Polymer – Two Technologies – Various Opportunities

    Aluminum Electrolytic vs. Polymer – Two Technologies – Various Opportunities By Pierre Lohrber BU Manager Capacitors Wurth Electronics @APEC 2017 2017 WE eiCap @ APEC PSMA 1 Agenda Electrical Parameter Technology Comparison Application 2017 WE eiCap @ APEC PSMA 2 ESR – How to Calculate? ESR – Equivalent Series Resistance ESR causes heat generation within the capacitor when AC ripple is applied to the capacitor Maximum ESR is normally specified @ 120Hz or 100kHz, @20°C ESR can be calculated like below: ͕ͨ͢ 1 1 ͍̿͌ Ɣ Ɣ ͕ͨ͢ ∗ ͒ ͒ Ɣ Ɣ 2 ∗ ∗ ͚ ∗ ̽ 2 ∗ ∗ ͚ ∗ ̽ ! ∗ ̽ 2017 WE eiCap @ APEC PSMA 3 ESR – Temperature Characteristics Electrolytic Polymer Ta Polymer Al Ceramics 2017 WE eiCap @ APEC PSMA 4 Electrolytic Conductivity Aluminum Electrolytic – Caused by the liquid electrolyte the conductance response is deeply affected – Rated up to 0.04 S/cm Aluminum Polymer – Solid Polymer pushes the conductance response to much higher limits – Rated up to 4 S/cm 2017 WE eiCap @ APEC PSMA 5 Electrical Values – Who’s Best in Class? Aluminum Electrolytic ESR approx. 85m Ω Tantalum Polymer Ripple Current rating approx. ESR approx. 200m Ω 630mA Ripple Current rating approx. 1,900mA Aluminum Polymer ESR approx. 11m Ω Ripple Current rating approx. 5,500mA 2017 WE eiCap @ APEC PSMA 6 Ripple Current >> Temperature Rise Ripple current is the AC component of an applied source (SMPS) Ripple current causes heat inside the capacitor due to the dielectric losses Caused by the changing field strength and the current flow through the capacitor 2017 WE eiCap @ APEC PSMA 7 Impedance Z ͦ 1 ͔ Ɣ ͍̿͌ ͦ + (͒ −͒ )ͦ Ɣ ͍̿͌ ͦ + 2 ∗ ∗ ͚ ∗ ͍̿͆ − 2 ∗ ∗ ͚ ∗ ̽ 2017 WE eiCap @ APEC PSMA 8 Impedance Z Impedance over frequency added with ESR ratio 2017 WE eiCap @ APEC PSMA 9 Impedance @ High Frequencies Aluminum Polymer Capacitors have excellent high frequency characteristics ESR value is ultra low compared to Electrolytic’s and Tantalum’s within 100KHz~1MHz E.g.
  • Measurement Error Estimation for Capacitive Voltage Transformer by Insulation Parameters

    Measurement Error Estimation for Capacitive Voltage Transformer by Insulation Parameters

    Article Measurement Error Estimation for Capacitive Voltage Transformer by Insulation Parameters Bin Chen 1, Lin Du 1,*, Kun Liu 2, Xianshun Chen 2, Fuzhou Zhang 2 and Feng Yang 1 1 State Key Laboratory of Power Transmission Equipment & System Security and New Technology, Chongqing University, Chongqing 400044, China; [email protected] (B.C.); [email protected] (F.Y.) 2 Sichuan Electric Power Corporation Metering Center of State Grid, Chengdu 610045, China; [email protected] (K.L.); [email protected] (X.C.); [email protected] (F.Z.) * Correspondence: [email protected]; Tel.: +86-138-9606-1868 Academic Editor: K.T. Chau Received: 01 February 2017; Accepted: 08 March 2017; Published: 13 March 2017 Abstract: Measurement errors of a capacitive voltage transformer (CVT) are relevant to its equivalent parameters for which its capacitive divider contributes the most. In daily operation, dielectric aging, moisture, dielectric breakdown, etc., it will exert mixing effects on a capacitive divider’s insulation characteristics, leading to fluctuation in equivalent parameters which result in the measurement error. This paper proposes an equivalent circuit model to represent a CVT which incorporates insulation characteristics of a capacitive divider. After software simulation and laboratory experiments, the relationship between measurement errors and insulation parameters is obtained. It indicates that variation of insulation parameters in a CVT will cause a reasonable measurement error. From field tests and calculation, equivalent capacitance mainly affects magnitude error, while dielectric loss mainly affects phase error. As capacitance changes 0.2%, magnitude error can reach −0.2%. As dielectric loss factor changes 0.2%, phase error can reach 5′.
  • Negative Capacitance in a Ferroelectric Capacitor

    Negative Capacitance in a Ferroelectric Capacitor

    Negative Capacitance in a Ferroelectric Capacitor Asif Islam Khan1, Korok Chatterjee1, Brian Wang1, Steven Drapcho2, Long You1, Claudy Serrao1, Saidur Rahman Bakaul1, Ramamoorthy Ramesh2,3,4, Sayeef Salahuddin1,4* 1 Dept. of Electrical Engineering and Computer Sciences, University of California, Berkeley 2 Dept. of Physics, University of California, Berkeley 3 Dept. of Material Science and Engineering, University of California, Berkeley 4 Material Science Division, Lawrence Berkeley National Laboratory, Berkeley, *To whom correspondence should be addressed; E-mail: [email protected] The Boltzmann distribution of electrons poses a fundamental barrier to lowering energy dissipation in conventional electronics, often termed as Boltzmann Tyranny1-5. Negative capacitance in ferroelectric materials, which stems from the stored energy of phase transition, could provide a solution, but a direct measurement of negative capacitance has so far been elusive1-3. Here we report the observation of negative capacitance in a thin, epitaxial ferroelectric film. When a voltage pulse is applied, the voltage across the ferroelectric capacitor is found to be decreasing with time–in exactly the opposite direction to which voltage for a regular capacitor should change. Analysis of this ‘inductance’-like behavior from a capacitor presents an unprecedented insight into the intrinsic energy profile of the ferroelectric material and could pave the way for completely new applications. 1 Owing to the energy barrier that forms during phase transition and separates the two degenerate polarization states, a ferroelectric material could show negative differential capacitance while in non-equilibrium1-5. The state of negative capacitance is unstable, but just as a series resistance can stabilize the negative differential resistance of an Esaki diode, it is also possible to stabilize a ferroelectric in the negative differential capacitance state by placing a series dielectric capacitor 1-3.
  • Advanced MOSFET Structures and Processes for Sub-7 Nm CMOS Technologies

    Advanced MOSFET Structures and Processes for Sub-7 Nm CMOS Technologies

    Advanced MOSFET Structures and Processes for Sub-7 nm CMOS Technologies By Peng Zheng A dissertation submitted in partial satisfaction of the requirements for the degree of Doctor of Philosophy in Engineering - Electrical Engineering and Computer Sciences in the Graduate Division of the University of California, Berkeley Committee in charge: Professor Tsu-Jae King Liu, Chair Professor Laura Waller Professor Costas J. Spanos Professor Junqiao Wu Spring 2016 © Copyright 2016 Peng Zheng All rights reserved Abstract Advanced MOSFET Structures and Processes for Sub-7 nm CMOS Technologies by Peng Zheng Doctor of Philosophy in Engineering - Electrical Engineering and Computer Sciences University of California, Berkeley Professor Tsu-Jae King Liu, Chair The remarkable proliferation of information and communication technology (ICT) – which has had dramatic economic and social impact in our society – has been enabled by the steady advancement of integrated circuit (IC) technology following Moore’s Law, which states that the number of components (transistors) on an IC “chip” doubles every two years. Increasing the number of transistors on a chip provides for lower manufacturing cost per component and improved system performance. The virtuous cycle of IC technology advancement (higher transistor density lower cost / better performance semiconductor market growth technology advancement higher transistor density etc.) has been sustained for 50 years. Semiconductor industry experts predict that the pace of increasing transistor density will slow down dramatically in the sub-20 nm (minimum half-pitch) regime. Innovations in transistor design and fabrication processes are needed to address this issue. The FinFET structure has been widely adopted at the 14/16 nm generation of CMOS technology.
  • Surface Mount Ceramic Capacitor Products

    Surface Mount Ceramic Capacitor Products

    Surface Mount Ceramic Capacitor Products 082621-1 IMPORTANT INFORMATION/DISCLAIMER All product specifications, statements, information and data (collectively, the “Information”) in this datasheet or made available on the website are subject to change. The customer is responsible for checking and verifying the extent to which the Information contained in this publication is applicable to an order at the time the order is placed. All Information given herein is believed to be accurate and reliable, but it is presented without guarantee, warranty, or responsibility of any kind, expressed or implied. Statements of suitability for certain applications are based on AVX’s knowledge of typical operating conditions for such applications, but are not intended to constitute and AVX specifically disclaims any warranty concerning suitability for a specific customer application or use. ANY USE OF PRODUCT OUTSIDE OF SPECIFICATIONS OR ANY STORAGE OR INSTALLATION INCONSISTENT WITH PRODUCT GUIDANCE VOIDS ANY WARRANTY. The Information is intended for use only by customers who have the requisite experience and capability to determine the correct products for their application. Any technical advice inferred from this Information or otherwise provided by AVX with reference to the use of AVX’s products is given without regard, and AVX assumes no obligation or liability for the advice given or results obtained. Although AVX designs and manufactures its products to the most stringent quality and safety standards, given the current state of the art, isolated component failures may still occur. Accordingly, customer applications which require a high degree of reliability or safety should employ suitable designs or other safeguards (such as installation of protective circuitry or redundancies) in order to ensure that the failure of an electrical component does not result in a risk of personal injury or property damage.
  • Very High Frequency Integrated POL for Cpus

    Very High Frequency Integrated POL for Cpus

    Very High Frequency Integrated POL for CPUs Dongbin Hou Dissertation submitted to the Faculty of the Virginia Polytechnic Institute and State University in partial fulfillment of the requirements for the degree of DOCTOR OF PHILOSOPHY in Electrical Engineering Fred C. Lee, Chair Qiang Li Rolando Burgos Daniel J. Stilwell Dwight D. Viehland March 23rd, 2017 Blacksburg, Virginia Keywords: Point-of-load converter, integrated voltage regulator, very high frequency, 3D integration, ultra-low profile inductor, magnetic characterizations, core loss measurement © 2017, Dongbin Hou Dongbin Hou Very High Frequency Integrated POL for CPUs Dongbin Hou Abstract Point-of-load (POL) converters are used extensively in IT products. Every piece of the integrated circuit (IC) is powered by a point-of-load (POL) converter, where the proximity of the power supply to the load is very critical in terms of transient performance and efficiency. A compact POL converter with high power density is desired because of current trends toward reducing the size and increasing functionalities of all forms of IT products and portable electronics. To improve the power density, a 3D integrated POL module has been successfully demonstrated at the Center for Power Electronic Systems (CPES) at Virginia Tech. While some challenges still need to be addressed, this research begins by improving the 3D integrated POL module with a reduced DCR for higher efficiency, the vertical module design for a smaller footprint occupation, and the hybrid core structure for non-linear inductance control. Moreover, as an important category of the POL converter, the voltage regulator (VR) serves an important role in powering processors in today’s electronics.
  • Coverage Layout Design Rules and Insertion Utilities for CMP-Related Processes

    Coverage Layout Design Rules and Insertion Utilities for CMP-Related Processes

    Journal of Low Power Electronics and Applications Review Coverage Layout Design Rules and Insertion Utilities for CMP-Related Processes Eitan N. Shauly 1,2,* and Sagee Rosenthal 1 1 Tower Semiconductor, Migdal Ha’Emek 10556, Israel; [email protected] 2 The Faculty of Materials Science and Engineering, Technion-Israel Institute of Technology, Haifa 32000, Israel * Correspondence: [email protected] Abstract: The continuous scaling needed for higher density and better performance has introduced some new challenges to the planarity processes. This has resulted in new definitions of the layout coverage rules developed by the foundry and provided to the designers. In advanced technologies, the set of rules considers both the global and the local coverage of the front-end-of line (FEOL) dielectric layers, to the back-end-of-line (BEOL) Cu layers and Al layers, to support high-k/Metal Gate process integration. For advance technologies, a new set of rules for dummy feature insertion was developed by the integrated circuit (IC) manufacturers in order to fulfill coverage limits. New models and utilities for fill insertion were developed, taking into consideration the design coverage, thermal effects, sensitive signal line, critical analog and RF devices like inductors, and double patterning requirements, among others. To minimize proximity effects, cell insertion was also introduced. This review is based on published data from leading IC manufacturers with a careful integration of new experimental data accumulated by the authors. We aim to present a typical foundry perspective. The review provides a detailed description of the chemical mechanical polishing (CMP) process and the coverage dependency, followed by a comprehensive description of coverage rules needed for dielectric, poly, and Cu layers used in advanced technologies.