Coverage Layout Design Rules and Insertion Utilities for CMP-Related Processes

Journal of Low Power Electronics and Applications

Review Coverage Layout Design Rules and Insertion Utilities for CMP-Related Processes

Eitan N. Shauly 1,2,* and Sagee Rosenthal 1

1 Tower Semiconductor, Migdal Ha’Emek 10556, Israel; [email protected] 2 The Faculty of Materials Science and Engineering, Technion-Israel Institute of Technology, Haifa 32000, Israel * Correspondence: [email protected]

Abstract: The continuous scaling needed for higher density and better performance has introduced some new challenges to the planarity processes. This has resulted in new definitions of the layout coverage rules developed by the foundry and provided to the designers. In advanced technologies, the set of rules considers both the global and the local coverage of the front-end-of line (FEOL) dielectric layers, to the back-end-of-line (BEOL) Cu layers and Al layers, to support high-k/Metal Gate process integration. For advance technologies, a new set of rules for dummy feature insertion was developed by the integrated circuit (IC) manufacturers in order to fulfill coverage limits. New models and utilities for fill insertion were developed, taking into consideration the design coverage, thermal effects, sensitive signal line, critical analog and RF devices like inductors, and double patterning requirements, among others. To minimize proximity effects, cell insertion was also introduced. This review is based on published data from leading IC manufacturers with a careful integration of new experimental data accumulated by the authors. We aim to present a typical foundry perspective. The review provides a detailed description of the chemical mechanical polishing (CMP) process and the coverage dependency, followed by a comprehensive description of coverage rules needed for dielectric, poly, and Cu layers used in advanced technologies. Coverage rules verification data are

then presented. RF-related aspects of some rules, like the size and the distance of dummy features from inductors, are discussed with additional design-for-manufacturing layout recommendations as developed by the industry. Citation: Shauly, E.N.; Rosenthal, S. Coverage Layout Design Rules and Insertion Utilities for CMP-Related Keywords: layout design rules; coverage rules; dummy ﬁll insertion; dishing; erosion; dummy Processes. J. Low Power Electron. Appl. insertion efﬁciency; coverage uniformity 2021, 11, 2. https://doi.org/10.3390/ jlpea11010002

Received: 7 August 2020 1. Introduction Accepted: 4 December 2020 The 0.25 µm FEOL (front end of line) technology node was the first to replace the Published: 31 December 2020 LOCOS (local oxidation; see, e.g., [1]) integration scheme with shallow trench isolation (STI). The three main reasons for that were as follows: Publisher’s Note: MDPI stays neutral with regard to jurisdictional clai- 1. There was a need for a reduction in spacing between devices. However, due to the ms in published maps and institutio- formation of the bird’s beak, the conventional LOCOS isolation structure does not nal affiliations. scale well. 2. Limited depth of focus (DOF) for the gate patterning, due to the relatively large step height of the field oxide above the active area (AA) surface (Figure1a). 3. Stresses from the nitride layer over the pad oxide induced dislocations into the silicon Copyright: © 2020 by the authors. Li- and led to junction leakage. censee MDPI, Basel, Switzerland. These limitations enhanced the STI integration development (Figure1b): a shallow This article is an open access article trench is etched into the silicon substrate and then filled with a deposited oxide. The surface distributed under the terms and conditions of the Creative Commons At- is then planarized by CMP (chemical mechanical polishing) to complete the isolation tribution (CC BY) license (https:// structure. By this integration scheme, the three limitations listed above are minimized. creativecommons.org/licenses/by/ 4.0/).

J. Low Power Electron. Appl. 2021, 11, 2. https://doi.org/10.3390/jlpea11010002 https://www.mdpi.com/journal/jlpea J. Low Power Electron. Appl. 2021, 11, x FOR PEER REVIEW 2 of 46 J. Low Power Electron. Appl. 2021, 11, 2 2 of 44

Figure 1. Front end of line (FEOL) field isolation and the challenge for poly patterning. (a) SEM (scanning electron Figuremicroscope) 1. Front cross-section end of line (FEOL) of Tower field 0.5 isolationµm technology and the localchallenge oxidation, for poly with patterning. a step height (a) SEM of around(scanning 250 electron nm, (b micro-) high- scope)resolution cross-section SEM cross-section of Tower of0.5 Tower µm technology 65 nm technology local oxidation, shallow with trench a step isolation height (STI), of around with a 250 step nm, height (b) high-resolution < 20 nm. SEM cross-section of Tower 65 nm technology shallow trench isolation (STI), with a step height < 20 nm. The 0.35 µm BEOL (back end of line) was the first technology that implemented CMP for dielectricThe 0.35 planarizationum BEOL (back with end Al of metal line) was lines. the The first 0.13 technologyµm technology that implemented node was the CMP first forthat dielectric replaced planarization the Al interconnect with Al (Figure metal2 lines.a) with The planarized 0.13 µm technology Cu (Figure2 nodeb). The was two the main first thatreasons replaced for that the wereAl interconnect as follows: (Figure 2a) with planarized Cu (Figure 2b). The two main reasons for that were as follows: 1. Limitation of the circuit performances due to high resistance capacitance (RC) delay. 1. LimitationAlong the of scaling the circuit path, performances the minimum due metal to high line resistance width was capacitance reduced by (RC a factor) delay. of Along≈0.7 fromthe scaling generation path, to the generation minimum to metal maintain linehigh width density, was reduced and the by line a thicknessfactor of ≈was0.7 from reduced generation by a similar to generation factor to to avoid maintain the high high aspect density, ratio, and which the line might thickness cause wasgap reduced fill issues. by Thea similar result factor was to higher avoid line the resistance.high aspect The ratio, advantage which might of using cause Cu gap is fillthe issues. lower The bulk result resistivity was comparedhigher line to resi Alstance. (approximately The advantage 40% lower), of using together Cu is with the lowersuperb bulk electromigration resistivity compared (EM) performance. to Al (approximately 40% lower), together with su- J. Low Power Electron. Appl. 2021, 11, x2. FOR PEERThe reductionREVIEW in the interconnect cross-section area along the scaling reduced the3 max-of 46 perb electromigration (EM) performance. 2. Theimum reduction current densityin the interconnect (Jmax), which cross-section was limited duearea to along EM. Forthe thescaling same reduced temperature the maximumand cross-section current area,density a Cu (Jmax line), can which handle wasJmax limited> 3.5 due times to EM. that ofFor Al. the same temperature and cross-section area, a Cu line can handle Jmax > 3.5 times that of Al. In Cu integration, the intermetal dielectric (IMD) layer is first patterned and etched and is then filled with Cu. The surface is then fully planarized by CMP to complete the interconnect formation (Figure 2b). To achieve good CMP planarization, the coverage of the material to be polished should be within certain limits. The term “coverage” refers to the pattern density, that is, the percentage of material at a certain checking window; a more detailed definition is provided later. When the design has a low coverage, dummy features of the material to be polished are inserted manually or by automatic insertion thus increasing the coverage. The insertion methods are also discussed in detail in this paper. The examples shown in Figure 2 are formed with oxide or Cu CMP processes. However, advanced technologies also require Al-CMP. At the 28 nm technology, Poly/SION for gate structures was used for the last time for low power (LP) applications. The same technology was also used in High-k/Metal Gate (HKMG) for applications such as high performance for mobiles (HPM). The most popular integration for 28HPM is gate-last that consists of replacement of the poly gate and the gate oxide underneath with HKMG. This replacement of metal Figure 2. Back end of line (BEOL) interconnect and the challenge for metal patterning. (a) SEM cross-section of Tower Figure 2. Back end of line (BEOL)gate (RMG) interconnect takes place and the after challenge interlayer-dielectri for metal patterning.c (ILD) planarization, (a) SEM cross-section prior to ofthe Tower contact 0.5 mod- µ um0.5 technologym technology M1 M1and and M2, M2,ule. showing showingAfterwards, limited limited theplanarization, planarization, metal gate ( btrench ()b SEM) SEM iscross-section cross-sectionfilled with of low-resistance of Towe Towerr 130nm 130nm AlCu Cu followed technology technology by using usingAl-CMP. chemicalchemical mechanical polishing Intel (CMP). used the same integration for 45 nm technology [2].

Precise control of the gate height and gate height uniformity is a primary challenge for the HKMG Al-CMP process. Beyond the DOF limitation, non-uniform gate height can cause gate resistance variation, and improper gate heights can result in contact etch problems. In CMOS platforms prior to Al-CMP integration (e.g., 45 nm technology), the gate height is approximately 60 nm. Such a large gate height strongly affects the transistor performance. Researchers from UMC [3] learned the affect of the metal gate area and pattern density on gate height loss due to Al dishing: The loss increases with increasing metal gate area and pattern density. Adding dummy gate lines reduced the gate height loss. Based on their study, we can set a simple design rule (DR), i.e., at least one (recommended two) dummy poly line is needed at both sides of each metal gate to effectively reduce metal gate height loss. In addition, optimized dummy metal gate structures are needed to reduce variability. The insertion of dummy features increases the coverage and improves the coverage uniformity across the die and the wafer. With regard to the dummy fill insertion methods and utilities developed for technology scaling, a previous study [4] shows that for 180 nm technologies down to 90 nm technologies, in most cases, dummy insertion is based on a single size dummy feature. Afterwards, based on some basic elimination rules, some of the dummies are removed. At the scale of 65–40 nm technologies, and mostly for Cu BEOL, the fill insertion was based on “analysis-driven fill”—each local window in the design is filled based on the local coverage and the gradient coverage to the neighbors around (explained later in this paper). A cell-based fill was introduced for the 28 nm platforms by leading IC manufacturers. The cell is composed of several layers, with a pattern matching that of a transistor (e.g., for AA and poly coverage) and a net grid for BEOL. This method is also explained later in this paper. The most recent fill insertion run-sets for 20 nm technologies and below also handle double or triple patterning (DP/TP). For 16 and 10 nm technology, the cell-based fill’s target is to maximize the insertion efficiency for better uniformity. The insertion takes into consideration the tight alignment requirements of the tile to the fins, DP integration, voltage-aware design, and more. All these topics are explained in detail in this review. Finally, <28 nm technology, engineering change orders (ECO) for design fixes become increasingly complicated due to the heavy duty of the dummy fill. This is also discussed herein.

J. Low Power Electron. Appl. 2021, 11, 2 3 of 44

In Cu integration, the intermetal dielectric (IMD) layer is first patterned and etched and is then filled with Cu. The surface is then fully planarized by CMP to complete the interconnect formation (Figure2b). To achieve good CMP planarization, the coverage of the material to be polished should be within certain limits. The term “coverage” refers to the pattern density, that is, the percentage of material at a certain checking window; a more detailed definition is provided later. When the design has a low coverage, dummy features of the material to be polished are inserted manually or by automatic insertion thus increasing the coverage. The insertion methods are also discussed in detail in this paper. The examples shown in Figure2 are formed with oxide or Cu CMP processes. How- ever, advanced technologies also require Al-CMP. At the 28 nm technology, Poly/SION for gate structures was used for the last time for low power (LP) applications. The same technology was also used in High-k/Metal Gate (HKMG) for applications such as high performance for mobiles (HPM). The most popular integration for 28HPM is gate-last that consists of replacement of the poly gate and the gate oxide underneath with HKMG. This replacement of metal gate (RMG) takes place after interlayer-dielectric (ILD) planarization, prior to the contact module. Afterwards, the metal gate trench is filled with low-resistance Al followed by Al-CMP. Intel used the same integration for 45 nm technology [2]. Precise control of the gate height and gate height uniformity is a primary challenge for the HKMG Al-CMP process. Beyond the DOF limitation, non-uniform gate height can cause gate resistance variation, and improper gate heights can result in contact etch problems. In CMOS platforms prior to Al-CMP integration (e.g., 45 nm technology), the gate height is approximately 60 nm. Such a large gate height strongly affects the transistor performance. Researchers from UMC [3] learned the affect of the metal gate area and pattern density on gate height loss due to Al dishing: The loss increases with increasing metal gate area and pattern density. Adding dummy gate lines reduced the gate height loss. Based on their study, we can set a simple design rule (DR), i.e., at least one (recommended two) dummy poly line is needed at both sides of each metal gate to effectively reduce metal gate height loss. In addition, optimized dummy metal gate structures are needed to reduce variability. The insertion of dummy features increases the coverage and improves the coverage uniformity across the die and the wafer. With regard to the dummy fill insertion methods and utilities developed for technology scaling, a previous study [4] shows that for 180 nm technologies down to 90 nm technologies, in most cases, dummy insertion is based on a single size dummy feature. Afterwards, based on some basic elimination rules, some of the dummies are removed. At the scale of 65–40 nm technologies, and mostly for Cu BEOL, the fill insertion was based on “analysis-driven fill”—each local window in the design is filled based on the local coverage and the gradient coverage to the neighbors around (explained later in this paper). A cell-based fill was introduced for the 28 nm platforms by leading IC manufacturers. The cell is composed of several layers, with a pattern matching that of a transistor (e.g., for AA and poly coverage) and a net grid for BEOL. This method is also explained later in this paper. The most recent fill insertion run-sets for 20 nm technologies and below also handle double or triple patterning (DP/TP). For 16 and 10 nm technology, the cell-based fill’s target is to maximize the insertion efficiency for better uniformity. The insertion takes into consideration the tight alignment requirements of the tile to the fins, DP integration, voltage-aware design, and more. All these topics are explained in detail in this review. Finally, <28 nm technology, engineering change orders (ECO) for design fixes become increasingly complicated due to the heavy duty of the dummy fill. This is also discussed herein. This review paper is organized as follows: first, the dependency of CMP and reactive ion etch (RIE) processes on the patterning coverage will be discussed. Next, an explanation for different local coverage rules will be given with many examples for the reason and the sensitivity of each rule. Several methods for dummy fill insertion will be presented, i.e., single-size, rule-based, and model-based, along with the special care required for filling J. Low Power Electron. Appl. 2021, 11, x FOR PEER REVIEW 4 of 46

This review paper is organized as follows: first, the dependency of CMP and reactive ion etch (RIE) processes on the patterning coverage will be discussed. Next, an explanation for different local coverage rules will be given with many examples for the reason and the sensitivity of each rule. Several methods for dummy fill insertion will be presented, i.e., single-size, rule-based, and model-based, along with the special care required for filling near a net wire. Finally, metal slits rules will be explained. The aim of this review is to provide the typical foundry and leading IC manufacturer’s perspective for coverage layout rules and the supported utilities. For this review, we used published data from J. Low Power Electron. Appl. 2021, 11,foundries 2 and leading integrated device manufacturers (IDMs), together with our own4 of 44 experimental process and device characteristics accumulated over the years.

2. CMP Process Integration near a net wire. Finally, metal slits rules will be explained. The aim of this review is to provideIn a theCMP typical process, foundry the wafer and leading being ICplanarized manufacturer’s is pressed perspective face down for coverageon a polymer- layout basedrules pad and and the supportedis polished utilities. with a slurry For this that review, contains we usedboth active published chemicals data from and foundriesabrasive particles.and leading In general, integrated the deviceprocess manufacturers of removing material (IDMs), togetherfrom the with wafer our surface own experimental is based on aprocess combination and device of both characteristics the mechanical accumulated energy induced over the by years. the polish head and abrasives and the chemical reaction from the slurry. 2. CMP Process Integration 2.1. CMPIn a Planarizatio CMP process,n for theOxide wafer and beingCu planarized is pressed face down on a polymer- basedThe pad local and polish is polished rate has with a strong a slurry dependenc that containsy on the both feature’s active pattern chemicals density. and abrasive Figure 3aparticles. shows how In general, the polish the rate process decreases of removing with increased material fromAA density the wafer [5]. surface The reason is based for this on a iscombination that for a given of both applied the mechanicalforce on a smaller energy ar inducedea, there by will the be polish an increase head and in the abrasives pressure, and whichthe chemical will lead reaction to higher from removal the slurry. rate. When features are eliminated, the polish rate then reduces to the rate of a planar surface. The time to reach this transition to planarity de- creases2.1. CMP with Planarization decreasing for density. Oxide andThis Cu is because the local polish rate increases with de- creasingThe AA local pattern polish density. rate has a strong dependency on the feature’s pattern density. Figure3a showsThe how process the polish of ILD rate planarization decreases with in Al increased BEOL involves AA density oxide [5 ].CMP The of reason the dielectric for this is thatthat takes for aplace given after applied metal forcesputtering on a smallerand metal area, etch. there A high will metal be an (Al) increase pattern in density the pressure, means thatwhich more will oxide lead needs to higher to be planarized. removal rate. For a When given featurespolish time, are high eliminated, density areas the polish will have rate athen higher reduces dielectric to thethickness rate of post a planar CMP surface. above the The metal time lines. to reach The thisILD transitionthickness is to measured planarity ondecreases top of the with Al features, decreasing and in density. this example This is(Figure because 3b) thehas locala target polish of 900 rate ± 100 increases nm. with decreasing AA pattern density.

6000 Data after: M. R. Oliver, Chemical-Mechanical Planarization of Semiconductor Materials, Springer, 2003.

5000 Pattern Density: (AA width) / (AA Pitch)

4000

3000

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d 2000

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R 20 30 40 50 60 70 80 a

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FigureFigure 3. 3. TheThe dependency dependency of of chemical chemical mechanical mechanical polishi polishingng (CMP) (CMP) removal removal rate rate on on pattern pattern density. density. (a (a) )Oxide Oxide polish polish rate rate withwith a a silica silica slurry slurry as as a a function function of of the the active active area area (AA) (AA) density density [5]. [5]. (b (b) )interlayer-dielectric interlayer-dielectric (ILD (ILD)) thickness thickness reduction reduction as as a a functionfunction of of Al Al metal metal pattern pattern density density [6]. [6].

2.2. DishingThe process and Erosion of ILD planarization in Al BEOL involves oxide CMP of the dielectric that takes place after metal sputtering and metal etch. A high metal (Al) pattern density means that more oxide needs to be planarized. For a given polish time, high density areas will have a higher dielectric thickness post CMP above the metal lines. The ILD thickness is measured on top of the Al features, and in this example (Figure3b) has a target of 900 ± 100 nm.

2.2. Dishing and Erosion In a case were local uniform coverage is available on the wafer, local planarization can be achieved (see Figure3b for dielectric CMP over Al lines). However, a large coverage difference between two nearby locations will create a dielectric step with a range that depends on the coverage differences, the amount of polished ﬁlm that has been removed, and the planarized material. The ILD over low coverage Al pattern will be removed faster compared to the ILD over a high coverage area. J. Low Power Electron. Appl. 2021, 11, x FOR PEER REVIEW 5 of 46

In a case were local uniform coverage is available on the wafer, local planarization can be achieved (see Figure 3b for dielectric CMP over Al lines). However, a large coverage difference between two nearby locations will create a dielectric step with a range that depends on the coverage differences, the amount of polished film that has been removed, J. Low Power Electron. Appl. 2021, 11, 2 5 of 44 and the planarized material. The ILD over low coverage Al pattern will be removed faster compared to the ILD over a high coverage area. Dishing is the thickness loss at the Cu line in comparison to the oxide nearby. For STI, itDishing is the thickness is the thickness loss compared loss at the to Cuthe lineSi or in SiN comparison surface. Erosion to the oxide is the nearby. amount For of oxideSTI, it lost is the between thickness Cu lines loss comparedin comparison to the to Sia field or SiN oxide surface. far from Erosion the lines. is the Dishing amount and of erosionoxide lost (Figure between 4b) Cuoccur lines in indamascene comparison processes to a ﬁeld during oxide the far fromclearing the and lines. overpolishing Dishing and stages.erosion Dishing (Figure 4occursb) occur due in to damascene differences processes in the polishing during therates clearing of the andtwo overpolishingexposed materials.stages. For Dishing copper occurs technology, due to differencesthe low-k ILD in the removal polishing rate rates is much of the twolower exposed than the materials. Cu re- movalFor copper rate. technology,Figure 4c shows the low-k an example ILD removal of severe rate copper is much dishing lower for than a 3.3 the µm Cu thickness removal (15rate. µm Figure wide)4c copper shows inductor. an example The of erosion severe is copper a result dishing of polishing for a 3.3 dissimilarµm thickness materials (15 thatµm varywide) in copper pattern inductor. density. The Oxide erosion loss is amore result dependent of polishing on dissimilarthe pattern materials layout and that takes vary placein pattern in cases density. of high Oxide metal loss coverage is more dependentand with narrow on the dielectric pattern layout spaces. and The takes polish place will in reducecases of and high potentially metal coverage damage and the with narrow narrow dielec dielectrictric fins spaces. and yield The di polishelectric will erosion reduce with and metalpotentially loss. damage the narrow dielectric ﬁns and yield dielectric erosion with metal loss.

Figure 4. Cu dishing and oxide erosion. (aa)) LocalLocal planarizationplanarization withwith aa ﬁnalfinal global global step step height height along along the the density density interaction interac- distancetion distance (or “planarization (or “planarization length” length” or “global or “global planarization planarization distance”; distance”; in short—“CMP in short—“CMP Range”) Range”) between between locations locations with largewith large coverage coverage differences. differences. (b) Typical (b) Typical cross-section cross-section showing showing copper copper dishing, dishing, in the in case the case of excessive of excessive local local coverage, coverage, and dielectricand dielectric erosion, erosion, in the in case the ofcase insufﬁcient of insufficient coverage coverage with narrowwith narrow lines andlines spaces. and spaces. (c) Our (c) SEM Our cross-sectionSEM cross-section of 3.3 µofm 3.3 Cu (ultra-thickµm Cu (ultra-thick metal) withoutmetal) without slits, with slits, severe with dishing. severe dishing. L/S = 15 L/Sµm/2 = 15 µµm/2m with µm a with local a coverage local coverage of 15/17 of =15/17 88%. = 88%.

An example of the erosion dependencydependency onon CuCu patternpattern densitydensity andand CuCu line/spaceline/space widths is presented in Figure 55,, inin which,which, forfor thethe samesame metalmetal density,density, thethe oxideoxide erosionerosion decreases with increasedincreased lineline width. width. There There are are two two reasons reasons for for the the rapid rapid increase increase in erosionin ero- sionwith with pattern pattern density: density: a longer a longer overpolishing overpolishi timeng time and and higher higher pressure pressure since since there there is less is lessoxide oxide area area to polish to polish [7]. [7].

J. Low Power Electron. Appl. 2021, 11, x 2 FOR PEER REVIEW 6 6of of 46 44

Figure 5. ExperimentalFigure 5. Experimental data of oxide data erosion of oxide as aerosion function as ofa function copper patternof copper density pattern [7]. density [7].

DishingDishing and and erosion erosion are controlled by the lo localcal pressure on features [[8].8]. The process parameters are are downward force, slurry removal rate, selectivity of the slurry to barriers andand dielectric, and and pad condition. Polishing Polishing pads pads are are quite quite flexible ﬂexible and have a surface roughnessroughness inin thethe samesame scale scale as as the the metal metal line line dimensions dimensions (pad (pad asperity asperity heights heights are are typically typi- cally1–3 µ 1–3m) µm) [5]. The[5]. The slurry slurry particle particle of fumedof fumed silica silica has has a a mean mean aggregate aggregate size size inin thethe range ofof 100–300 nm. Figure Figure 66 illustratesillustrates erosionerosion dependencydependency onon thethe coveragecoverage andand lineline widthwidth (higher(higher coverage results in more erosion). The result of dishing and erosion, in addition to the general CMP non-uniformity, is Cu thickness variations [7]. The maximal line thickness variation at a typical foundry process is ±15%. Higher variations yield non-optimized photo depth of focus (DOF), high BEOL resistance capacitance (RC) variation, and topography that can lead to Cu residues in the upper layers. During Cu CMP, recessing can also take place. A recess (Figure7) is characterized by a small sharp vertical step at the edge of metal features, unlike dishing and erosion, which are characterized by gradual changes in vertical dimensions and a relatively smooth topography. Recesses can be understood as a degradation of the ﬁnal planarity arising from the complete removal of the metal overburden. However, unlike dishing, recessing affects features regardless of size. The exact source of recessing is not entirely clear in every case. However, it can generally be attributed to chemical attack or corrosion of the metal surface, either during over-polishing or during post-polish cleaning.

J. Low Power Electron. Appl. 2021, 11, x FOR PEER REVIEW 7 of 46

J.J. Low Low Power Power Electron. Electron. Appl. Appl. 20212021,, 1111,, x 2 FOR PEER REVIEW 7 7of of 46 44

Figure 6. Illustration of dishing and erosion for Cu densities (metal coverage) of 0–100%.

The result of dishing and erosion, in addition to the general CMP non-uniformity, is Cu thickness variations [7]. The maximal line thickness variation at a typical foundry process is ±15%. Higher variations yield non-optimized photo depth of focus (DOF), high BEOL resistance capacitance (RC) variation, and topography that can lead to Cu residues in the upper layers. During Cu CMP, recessing can also take place. A recess (Figure 7) is characterized by a small sharp vertical step at the edge of metal features, unlike dishing and erosion, which are characterized by gradual changes in vertical dimensions and a relatively smooth topography.Figure 7. Recess Recesses of a Cu can line. be understood as a degradation of the final planarity arising from the complete removal of the metal overburden. However, unlike dishing, recessing affects featuresIn processes regardless with of size. low copperThe exact coverage, source likeof recessing Via CMP is for not single entirely Damascene clear in every integration, case. However,a severe recess it can maygenerally yield be an attributed open via (Figureto chemical8). To attack eliminate or corrosion that, the of process the metal should surface,be optimized either during and splitover-polishing into several or steps. during Isolated post-polish vias tendcleaning. to suffer more than arrays of vias. Therefore, design rules for via coverage were introduced into the foundry design rule manual (DRM). Short over-polish times should be used for lonely vias. Finally, the slurry chemistry has a very large impact, i.e., insufﬁcient corrosion inhibitor will lead to large recesses. Thick and wide Cu lines are sensitive to recessing, especially when a long polish time is required to clear the Cu overburden. Figure9 shows such a case, in which a metal line recess created topography which caused poor patterning of the following via photo resist. This led to an “undeﬁned via.” Process improvements solved this problem.

J. Low Power Electron. Appl. 2021, 11, x FOR PEER REVIEW 8 of 46

Figure 7. Recess of a Cu line. In processes with low copper coverage, like Via CMP for single Damascene integration, a severe recess may yield an open via (Figure 8). To eliminate that, the process should be optimized and split into several steps. Isolated vias tend to suffer more than arrays of vias. Therefore, design rules for via coverage were introduced into the foundry design J. Low Power Electron. Appl. 2021, 11,rule 2 manual (DRM). Short over-polish times should be used for lonely vias. Finally,8 ofthe 44 slurry chemistry has a very large impact, i.e., insufficient corrosion inhibitor will lead to large recesses.

J. LowFigure FigurePower Electron. 8. 8. ViaVia recess recessAppl. 2021 (for (for, 11single single, x FOR Damascene Damascene PEER REVIEW integration) integration) and and process process sensitivity. sensitivity. ( (aa)) A A dense dense via via and and ( (bb)) isolated isolated via. via. Both Both9 of 46

((aa)) and and ( (bb)) are are from from non-optimized non-optimized processes. processes. ( (cc)) Dense Dense via via and and ( (dd)) isolated isolated via via with with optimized optimized processes processes and and improved improved slurryslurry material. material.

Thick and wide Cu lines are sensitive to recessing, especially when a long polish time is required to clear the Cu overburden. Figure 9 shows such a case, in which a metal line recess created topography which caused poor patterning of the following via photo resist. This led to an “undefined via.” Process improvements solved this problem.

Figure 9. Recess of a wide/thick Cu Cu line. line. (a (a) )The The metal metal recess recess has has a a multilevel multilevel effect, effect, causing causing the the following following via via to to be be poorly poorly defined;deﬁned; (b) close-up image of the metal recess;recess; andand ((cc)) thethe samesame structure,structure, butbut withwith anan optimizedoptimized process.process.

FigureFigure 10 showsshows our our experimental experimental data rega regardingrding the dependency of erosion on local CuCu density. density. Using Using a aset set of of test test chips chips with with different different coverages coverages (all (allwith with L = L2 µm), = 2 µ them), die- the lectricdielectric erosion erosion was was measured. measured. Using Using an upper an upper limit limit of 600 of 600 A, the A, themaximal maximal coverage coverage can can be extractedbe extracted as asaround around 80%. 80%. Naturally, Naturally, longer longer over-polish over-polish times times yield yield larger larger erosion. erosion. M1 sheetsheet resistance resistance (Figure 10b)10b) showed the same dependency to coverage as erosion. Setting anan upper limit of 100 mOhm/sq yields yields a a maximal maximal coverage coverage of of around around 80%. The The structures structures with coverage >80% also also showed showed high high Sheet Sheet Resistance Resistance (Rs) (Rs) distribution.

(a) (b)

Figure 10. Cu pattern density impact on (a) dielectric erosion and (b) sheet resistance. Both graphs are for M1, with a metal thickness of 4500 A, L = 2 µm, and with different over-polish times.

2.3. Oxide CMP Process In oxide CMP, the water diffuses into the oxide network and causes the rupturing of Si–O bonds [9]. Oxide surface weakening occurs by the following equation:

Si–O–Si + H2O –> Si–OH.

Once all the Si–O bonds for a given Si atom are hydrated, Si(OH)4 is formed, which is highly soluble in water at high pH levels. These reactions are accelerated by the com- pressive stress imposed on the surface by abrasive particles [9]. The hydrated Si surface is much softer than the initial SiO2 net and is therefore much more easily removed by abrasive particles. The most basic material removal model is described by Preston’s equation, which was initially introduced for glass polishing:

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Figure 9. Recess of a wide/thick Cu line. (a) The metal recess has a multilevel effect, causing the following via to be poorly defined; (b) close-up image of the metal recess; and (c) the same structure, but with an optimized process.

Figure 10 shows our experimental data regarding the dependency of erosion on local Cu density. Using a set of test chips with different coverages (all with L = 2 µm), the dielectric erosion was measured. Using an upper limit of 600 A, the maximal coverage can be extracted as around 80%. Naturally, longer over-polish times yield larger erosion. M1 sheet resistance (Figure 10b) showed the same dependency to coverage as erosion. Setting J. Low Power Electron. Appl. 2021, 11, 2 an upper limit of 100 mOhm/sq yields a maximal coverage of around 80%. The9 structures of 44 with coverage >80% also showed high Sheet Resistance (Rs) distribution.

(a) (b)

FigureFigure 10. Cu 10. pattern Cu pattern density density impact impact on (a) dielectricon (a) dielectric erosion erosion and (b )and sheet (b) resistance. sheet resistance. Both graphs Both graphs are for are M1, for with M1, a with metal a metal thicknessthickness of 4500 of A, 4500 L = A, 2 µ Lm, = and2 µm, with and different with different over-polish over-polish times. times.

2.3. Oxide2.3. Oxide CMP CMP Process Process In oxideIn oxide CMP, CMP, the water the water diffuses diffuses into the into oxide the oxide network network and causes and causes the rupturing the rupturing of of Si–O bondsSi–O bonds [9]. Oxide [9]. Oxide surface surface weakening weakening occurs occurs by the by following the following equation: equation:

2 Si-O-SiSi–O–Si + H2 O+ H→OSi-OH. –> Si–OH.

Once all the Si–O bonds for a given Si atom are hydrated, Si(OH)4 is formed, which Once all the Si–O bonds for a given Si atom are hydrated, Si(OH) is formed, which is is highly soluble in water at high pH levels. These reactions are4 accelerated by the com- highly soluble in water at high pH levels. These reactions are accelerated by the compres- pressive stress imposed on the surface by abrasive particles [9]. The hydrated Si surface is sive stress imposed on the surface by abrasive particles [9]. The hydrated Si surface is much much softer than the initial SiO2 net and is therefore much more easily removed by abra- softer than the initial SiO net and is therefore much more easily removed by abrasive sive particles. The most2 basic material removal model is described by Preston’s equation, particles. The most basic material removal model is described by Preston’s equation, which which was initially introduced for glass polishing: was initially introduced for glass polishing:

RR = KePV,

where RR is the material removal rate of the polished material, Ke is a calibration coefficient, P is the downward pressure, and V is the relative velocity between the wafer and pad. The equation demonstrates the linear dependency of the material removal rate on the pressure and velocity [7]. The equation does not represent all dependencies (e.g., on slurry and pad properties), and in many cases, it does not perfectly correlate with experimental data. Brown and Cook [6] developed a physical model that takes consumable and wafer parameters into account: RR = PV/2E, where E is the Young’s modulus of the wafer materials. This model proposes an interaction between the abrasive particles and the wafer surface that is proportional to the particle penetration of the oxide. Some researchers assume that a fluid film exists between the wafer and pad interface. Runnel [10] developed an erosion-based model in which erosion/material removal rates at each single point are given through fluid stress tensors:

RR = Ceσtσn,

where Ce is a calibration coefficient, σt is the sheer stress due to the slurry flow and σn is the normal stress. When pattern wafers are polished, the wafer pattern density, feature size, and pitch has a large impact on the RR at different die locations. A model was developed at MIT by Stine et al. [11] and the experimental data indicated that the pattern density ρ(x, y), defined J. Low Power Electron. Appl. 2021, 11, 2 10 of 44

as the ratio of the raised area to the total area as measured in a window of a given size, has the strongest impact on the within-die non-uniformity (WIDNU). This is explained by the relationship between pattern density and pressure. In the high-density area, where the oxide area contacted by the pad is larger, the effective pressure P/ρ(x, y) is lower and the material removal is reduced. Equations for the material removal rate based on Preston’s equation were developed by Stine et al. [12]:  MRRit ρ(x,y)z1  z0 − t < = ρ(x,y) MRRi z ρ(x,y)z ,  z − z − MRR + ρ(x, y)z t > 1 0 1 it 1 MRRi

where Z is the height of the oxide pattern feature to the substrate, Zl is the as-deposited step height, ρ(x, y) is the effective pattern density, MRRi = KePV is the blanket wafer polishing rate (based on Preston’s equation), and t is the polishing time. For time t < ρ(x, y)z1/MRRi, there is still a step height, and once t > ρ(x, y)z1/MRRi, the RR is of a blanket wafer. Using this model enables researchers to consider the impact of pattern density.

2.4. STI CMP Process At STI CMP, the process needs to planarize the dielectric that ﬁlls the trenches with good uniformity and minimal process defects. The main challenges of STI CMP are as follows: Clearing all of the oxide above the SiN: The STI CMP needs to remove all of the oxide above the SiN, which serves as a “stopping” layer. Large areas with high coverage are close to a blanket wafer. The result is a very low RR, and there is a high risk of leaving J. Low Power Electron. Appl. 2021, 11, x oxideFOR PEER residues. REVIEW This problem depends on the STI ﬁll process, since different deposition11 of 46

processes will result in different overﬁlls. Soft stop on the SiN: Polish should not damage the Si surface. Scratches or lattice defects lead to a degradation of reliability. To address this concern, it is common to use Ceria (CeO2) as the abrasive particle instead of silica. Ceria has a high RR and higher se- Ceria (CeO ) as the abrasive particle instead of silica. Ceria has a high RR and higher lectivity between2 oxide to SiN. In addition, the SiN needs to be thick enough to prevent selectivity between oxide to SiN. In addition, the SiN needs to be thick enough to prevent scratches that occur during the CMP process from reaching the Si surface. The CMP pro- scratches that occur during the CMP process from reaching the Si surface. The CMP process cess is faster at corners and along edges of topography. Therefore, the SiN at the edge of is faster at corners and along edges of topography. Therefore, the SiN at the edge of the the AA region near the STI will be polished faster than areas far from the STI (Figure 11). AA region near the STI will be polished faster than areas far from the STI (Figure 11). This This problem is more severe for large AA spaces (wide STI). problem is more severe for large AA spaces (wide STI).

FigureFigure 11. 11. NitrideNitride erosion erosion in in dense STI areas (low AA coverage). The erosion at the STI/AA edge edge might might degrade degrade the the gate gate oxideoxide integrity. integrity.

STISTI Dishing Dishing:: Since Since the the SiN SiN has has a a lower lower RR RR than than the the oxide, oxide, dishing dishing in in the the STI STI occurs. occurs. InIn severe severe cases, cases, poly poly located located over over STI STI will will be be poorly poorly defined deﬁned due due to to limited limited DOF. DOF.

2.5. W and Cu CMP Kaufman et al. proposed a model for tungsten CMP after the contact fill, which was widely accepted [13]. According to this model, a passivation layer of tungsten oxide is created by the slurry chemicals and the aqua solution. This layer is softer than the bulk of the W; therefore, it is more easily removed by the slurry abrasives and polishing pad mechanical abrasion. A fresh tungsten surface is exposed, passivated, and removed, and so on. The passivation layer also prevents dissolution of the tungsten film in the low areas in cases when the slurry chemistry has a high static etch rate [9]. Hydrogen peroxide is used in all metal CMP slurries as an oxidizer [7]. The removal of Cu consists of several steps [8]: (1) dissolution of Cu to form thin atomic layers of oxides of Cu, (2) mechanical removal of the material using slurry particle abrasives, and (3) sweeping away the abraded material suspended in the solution by slurry flow. An example of the slurry components and the interactions with the Cu surface during polishing can be seen in Figure 12.

J. Low Power Electron. Appl. 2021, 11, 2 11 of 44

2.5. W and Cu CMP Kaufman et al. proposed a model for tungsten CMP after the contact fill, which was widely accepted [13]. According to this model, a passivation layer of tungsten oxide is created by the slurry chemicals and the aqua solution. This layer is softer than the bulk of the W; therefore, it is more easily removed by the slurry abrasives and polishing pad mechanical abrasion. A fresh tungsten surface is exposed, passivated, and removed, and so on. The passivation layer also prevents dissolution of the tungsten film in the low areas in cases when the slurry chemistry has a high static etch rate [9]. Hydrogen peroxide is used in all metal CMP slurries as an oxidizer [7]. The removal of Cu consists of several steps [8]: (1) dissolution of Cu to form thin atomic layers of oxides of Cu, (2) mechanical removal of the material using slurry particle abrasives, and (3) sweeping away the abraded material suspended in the solution by slurry J. Low Power Electron. Appl. 2021, 11, x FOR PEER REVIEW 12 of 46 flow. An example of the slurry components and the interactions with the Cu surface during polishing can be seen in Figure 12.

------Wafer (face down)------

Copper film

Copper Oxide (2-3 atomic layers)

Slurry solution

Corrosion inhibitor, absorbed on the Cu Pad

Figure 12. SchematicSchematic illustration illustration of of the the Cu Cu surface surface during during CMP CMP (wafer face down). The The complex complex surface surface is removed removed by the abrasive slurry particles. abrasive slurry particles.

TheThe hardness ofof coppercopper (1–3 (1–3 GPa) GPa) falls falls between between that that of tungsten of tungsten and aluminum.and aluminum. Thus, Thus,Cu is easierCu is easier to abrade to abrade than W.than The W. hardness The hardness of Cu isof signiﬁcantlyCu is significantly lower thanlower the than slurry the slurryabrasive abrasive particles, particles, which which are usually are usually silica. Thus,silica. chemicalThus, chemical action onaction Cu toon formCu to a form harder a harderoxide is oxide essential is essential before thebefore mechanical the mechanical abrasion abrasion of Cu to of prevent Cu to prevent the formation the formation of defects of defectsduring during the CMP the process CMP process [9]. [9]. TheThe layer layer formation formation on on the the surface can be explained by electrochemical reactions suchsuch as as + − Cu𝐶𝑢2 + +2𝑒2e ↔ ↔Cu 𝐶𝑢 2𝐶𝑢+ +𝐻 𝑂+ −2𝑒 ↔ 𝐶𝑢 𝑂+2𝐻+. 2Cu2 + H2O + 2e ↔ Cu2O + 2H . OxidizerOxidizer:: For For metal metal CMP, CMP, an oxidizingoxidizing chemical environment isis required.required. During coppercopper oxidation, oxidation, neutral neutral metal metal atoms atoms lose lose el electronsectrons and and take take on on a a net net positive positive charge. charge. TheThe metal metal atom atom loses loses the the valence valence electrons electrons to to atmospheric atmospheric oxygen oxygen to to form form metal metal oxide. oxide. TheThe oxidizer oxidizer species species contained contained in in the the slurry slurry undergo undergo reduction reduction when the metal surface is oxidized. Both the static etch rate and dynamic removal rate of Cu depend on the H2O2 oxidized. Both the static etch rate and dynamic removal rate of Cu depend on the H2O2 oxidizeroxidizer concentration concentration in in the the acidic acidic medium medium (Figure (Figure 13).13). The The removal removal rate rate increases increases with increase in H2O2 concentration up to a certain point [8]. The decrease in removal rate is increase in H2O2 concentration up to a certain point [8]. The decrease in removal rate is attributedattributed to to an an increase increase in in surface surface passivation. passivation. A A typical typical slurry slurry used used in in the the field ﬁeld includes includes aboutabout 1% 1% hydrogen hydrogen peroxide peroxide concentration.

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FigureFigure 13. Cu 13. staticCu staticetch rate etch and rate removal and removal rate dependency rate dependency on peroxide on peroxide concentration. concentration. Based Based on data on from data from[8]. [8]. Buffering: Cu slurry is typically held close to neutral pH to control the removal chem- Buffering: Cu slurry is typically held close to neutral pH to control the removal istry. For pH > 7, a buffer system based on a solution of a weak base and a corresponding chemistry. For pH > 7, a buffer system based on a solution of a weak base and a corre- salt (e.g., ammonium hydroxide and ammonium chloride) is used. sponding salt (e.g., ammonium hydroxide and ammonium chloride) is used. Corrosion inhibitors: Added to the slurry to suppress Cu corrosion and dissolution. Corrosion inhibitors: Added to the slurry to suppress Cu corrosion and dissolution. The inhibitors are adsorbed onto the metal surface to form a protective coating, which The inhibitors are adsorbed onto the metal surface to form a protective coating, which causes the inhibition of oxidation of the metal surface to some degree. Corrosion inhibitors causes the inhibition of oxidation of the metal surface to some degree. Corrosion inhibitors are crucial to prevent dishing and post-CMP corrosion of Cu lines. are crucialSurfactants to prevent: A surfactant dishing and is apost-CMP dissolved corrosion chemical of agent Cu lines. that reduces the surface or interfacialSurfactants tension: A of surfactant a liquid phase, is a dissolved typically chemical water, in agent contact that with reduces some the second surface phase. or interfacialThe surface tension tension of of a aqueous liquid phase, media typically containing water, surfactants in contact is significantly with some lowered, second phase. which Theresults surface in better tension wetting. of aqueous That is, surfactantsmedia containing change thesurfactants interaction is betweensignificantly abrasive lowered, parti- whichcles and results the solution. in better This wetting. provides That better is, surfactants particle suspension change the and interaction a collateral between reduction abra- in siveparticle particles agglomeration. and the solution. It is particularly This provides important better forparticle copper suspension CMP, since and copper a collateral is soft reductionand easily in scratched. particle agglomeration. It is particularly important for copper CMP, since copperComplexing is soft and agentseasily scratched.: Metals containing complexes can be formed in aqueous media. A metalComplexing complex agents is a chemical: Metals speciescontaining that complexes has a metal can atom be formed in a central in aqueous position, media. to Awhich metal various complex atoms is a chemical or molecules species are chemicallythat has a metal bonded. atom In in general, a central complexation position, to resultswhich variousin dissolved atoms metallic or molecules species are that chemically are thermodynamically bonded. In general, more stablecomplexation than simple results aquo in dissolvedions. For metalmetallic CMP, species complexation that are thermodyna can be generallymically expected more stable to increase than simple the removal aquo ions. rate; Fortherefore, metal complexingCMP, complexation agents are can sometimes be generally added expected intentionally to increase to the slurrythe removal [5]. rate; therefore, complexing agents are sometimes added intentionally to the slurry [5]. 2.6. Cu CMP Modeling 2.6. CuCMP CMP nonuniformity Modeling can be classified as short-range, long-range or wafer scale [14]. The modelCMP nonuniformity described below can is forbe classified long range. as Theshor factt-range, that thelong-range slurry is or amulti-component wafer scale [14]. Themakes model the theoreticaldescribed below modeling is for of long Cu CMPrange. more The complicated.fact that the slurry The model is a multi-component should take into makesconsideration the theoretical the different modeling pattern of Cu densities CMP more and complicated. feature sizes, The the removalmodel should rate selectivity take into considerationbetween Cu and the the different liner (usually pattern Ta/TaN),densities andand thefeature removal sizes, of the the removal dielectric rate antireflective selectivity betweencoating (DARC), Cu and the which liner requires (usually an Ta/TaN), additional and CMP the removal step. of the dielectric antireflective coatingMost (DARC), of the models which forrequires copper an CMP additional are based CMP on Preston’sstep. equation. Tugbawa et al. [15] modeledMost the of the pattern models dependency for copper of CMP the Cu are CMP based by on dividing Preston’s the equation. process into Tugbawa three stages: et al. [15](1) Bulk modeled Cu removal, the pattern (2) barrierdependency removal of (wherethe Cu CMP dishing by evolves),dividing andthe process (3) the overpolish into three stages:step (where (1) Bulk erosion Cu removal, evolves). (2) Usingbarrier removal removal rate(where data dishing from blanket evolves), wafers, and (3) the the model over- polishestablishes step an(where empirical erosion relationship evolves). between Using re themoval material rate removal data from rate blanket and polish wafers, pressure. the modelThis data establishes is then used an empirical to calculate relationship the polish between pressure the and material removal removal rates as rate a result and polish of the

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J. Low Power Electron. Appl. 2021 11 , , 2pressure. This data is then used to calculate the polish pressure and removal rates13 as of 44a result of the step height and pattern density. For each of the above three steps, a set of equations represent the removal rate of the high-density areas and the low-density areas. Tugbawastep height et andal. used pattern MIT-SEMATECH density. For each test of mask the aboves, which three came steps, to be a the set ofcommon equations industry repre- vehiclesent the for removal modeling rate a of copper the high-density CMP process. areas Th ande mask the low-densityhas a variety areas. of structuresTugbawa with et al. differentused MIT-SEMATECH densities and pitches test masks, to retrieve which the came empirical to be the data common of dishing industry and erosion. vehicle Fi- for nally,modeling the experimental a copper CMP data process. is used to The calibrate mask hasthe aCMP variety model of for structures the exact with consumable different set.densities and pitches to retrieve the empirical data of dishing and erosion. Finally, the experimentalThe change data in isstep used height to calibrate along with the CMPpolish model time is for described the exact by consumable set. The change in step height along𝑑𝐻 with polish time is described by =𝑅𝑅 −𝑅𝑅 , 𝑑𝑡 dH = RR − RR , where dt down up 1−𝜌 where ⎧𝑟 + 𝑟 0𝐻 <𝐻 ( 𝜌 𝑅𝑅 = 1−ρcu rcu + rcu 𝑟ρ 0 ≤ H < Hex RRup = ⎨ cu 𝐻 > 𝐻 rcu H > H ⎩ ρcu𝜌 ex ( 𝐻 𝑟 1− −H ≤0𝐻< <𝐻 𝑅𝑅 = rcu 1 H 𝐻0 H Hex , RRdown = ex , 0 H0 𝐻> H >ex 𝐻 where 𝑟 is the blanket Cu removal rate, 𝜌 is the pattern density, and 𝐻 is the step where r is the blanket Cu removal rate, ρ is the pattern density, and H is the step height fromcu which the down pressure area removalcu rate starts to be significant.ex The 𝐻 height from which the down pressure area removal rate starts to be signiﬁcant. The H data is obtained from the test masks. ex data is obtained from the test masks.

2.7.2.7. Cu Cu Electroplating Electroplating TheThe Cu Cu electroplating electroplating process process is is also also depe dependentndent on on the the feature feature size size and and density. density. The The processprocess filling ﬁlling is is “bottom-up,” “bottom-up,” which which helps helps to toprevent prevent void void formation formation in high in high aspect aspect features.features. This This is achieved is achieved by additive by additive chemicals chemicals known known as accelerators, as accelerators, suppressors, suppressors, and lev- and elers,levelers, which which are added are added to the to plating the plating solution solution [5]. However, [5]. However, it leads it to leads substantial to substantial thicknessthickness variations variations of the of copper the copper overburden overburden (“overfill”). (“overﬁll”). In Inparticular, particular, copper copper is is relatively relatively thickthick over over densedense arraysarrays ofof minimum minimum dimension dimension features features and and is thinneris thinner over over wider wider features. features.Figure Figure 14 presents 14 presents a schematic a schematic example exampl of thee of Cu the thickness Cu thickness post-electroplating post-electroplating deposition deposition(ECD) of(ECD) different of different Cu line Cu widths line widths and densities. and densities.

FigureFigure 14. 14. A Atypical typical topography topography after after post-electroplating post-electroplating depositi depositionon (ECD), (ECD), for for different different Cu Cu coverage coverage and and line line widths. widths.

Longer polish times are needed to remove the thicker copper deposition over small dense features. However, this would cause over-polishing for wide features. In addition, it

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J. Low Power Electron. Appl. 2021, 11, 2 14 of 44 Longer polish times are needed to remove the thicker copper deposition over small dense features. However, this would cause over-polishing for wide features. In addition, it can result in severe dishing, erosion, and field loss [5]. Figure 15 shows our results for thecan erosion result independency severe dishing, on coverage erosion, under and ﬁeld three loss different [5]. Figure process 15 shows conditions. our results For forover- the polisherosion conditions, dependency higher on coverage density underincreases three the different erosion. process In addition, conditions. at a similar For over-polish density (e.g.,conditions, 50%), wider higher dielectric density increasesspaces result the erosion.in less erosion. In addition, A positive at a similar erosion density value (e.g., (usually 50%), referredwider dielectric to as “negative spaces resulterosion”) in less means erosion. that Athe positive dielectric erosion thickness value of (usually the measured referred structureto as “negative is higher erosion”) than the means field thatoxide the refere dielectricnce level. thickness This is of explained the measured by the structure plating is process,higher thanwhich the has ﬁeld a higher oxide referenceCu plating level. thic Thiskness is (overburden). explained by theWhen plating polished, process, the which low coveragehas a higher areas Cu are plating cleared thickness from copper (overburden). before the high When coverage polished, areas, the lowso the coverage dielectric areas is exposedare cleared sooner, from resulting copper before in higher the highlevels coverage of erosion. areas, so the dielectric is exposed sooner, resulting in higher levels of erosion.

Figure 15. Cu erosion vs. coverage for different polishing times. Figure 15. Cu erosion vs. coverage for different polishing times. Another aspect that needs special attention is post-CMP cleaning. The low-k materials Another aspect that needs special attention is post-CMP cleaning. The low-k materi- are more hydrophobic than SiO2, which results in less effective cleaning and can leave alswater are more marks. hydrophobic Wafer drying than usingSiO2, which isopropyl results alcohol in less (IPA) effective is more cleaning effective and can than leave spin waterdrying marks. at removing Wafer drying all of theusing water isopropyl from the alcohol dielectric (IPA) surface is more and effective eliminating than spin the waterdry- ingdrying at removing marks. all of the water from the dielectric surface and eliminating the water drying marks. 3. Global and Local Planarization—CMP Range 3. GlobalGlobal and planarization Local Planarization—CMP depends on coverage Range difference of neighboring areas. Therefore DummyGlobal ﬁll planarization insertion is depends used to achieveon coverage as uniform difference coverage of neighboring as possible. areas. This Therefore is done Dummywith dummy fill insertion AA (DAA), is used dummy to achieve poly as (DGC), uniform and coverage dummy as metal possible. (DM). This The is done distance with of dummythe inserted AA (DAA), tiles to neighboringdummy poly features (DGC), hasand andummy impact metal on the (DM). polish The rate distance at the location of the insertedof interest tiles (see to neighboring Figure4a). The features planarization has an im lengthpact on also the depends polish rate on at the the CMP location process of interestparameters (see Figure such as 4a). head The pressure, planarization pad condition, length also polish depends time, etc. on Forthe CuCMP technology process pa- that rametersincludes such a Ta/TaN as head barrier, pressure, the CMP pad conditio involvesn, the polish removal time, of etc. different For Cu materials technology that that also includesaffect the a Ta/TaN CMP range barrier, [16]. the CMP involves the removal of different materials that also affect theTypical CMP values range for [16]. oxide CMP have been estimated as 0.5–2 mm [17] and 3–5 mm [18]. A typicalTypical value values used for by oxide the CMP industry have is been about estimated 500 µm. Foras 0.5–2 Cu CMP, mm [17] the and interaction 3–5 mm length [18]. Awas typical estimated value used as 100–200 by the industryµm [17] is and about 50–100 500 µm.µm [For16]. Cu The CMP, typical the interaction range used length in the wasindustry estimated is 25–100 as 100–200µm, varying µm [17] depending and 50–100 on µm the [16]. metal The thickness—the typical range thicker used in the the line in- is, dustrythe larger is 25–100 the interaction µm, varying length. depending Lakshminarayanan on the metal et al.thickness—the [16] studied thethicker effective the line pattern is, theinteraction larger the distance interaction using length. a set Lakshminarayan of structures withan differentet al. [16] coveragesstudied the and effective measured pattern the interactionline resistance. distance Figure using 16a ashows set of thestructures median with resistance different of acoverages structure and with measured L/S = 3/1 theµm lineand resistance. 75% coverage Figure as 16a a function shows the ofthe median position resistance on the of array. a structure The resistance with L/S at = the 3/1 arrayµm edge increases rapidly, proceeding inwards (due to dielectric erosion), and stabilized about 30 µm from the edge. We can conclude that the range is about 30 µm and resistance is stable beyond that range. Figure 16b shows the spatial change in median resistance of

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and 75% coverage as a function of the position on the array. The resistance at the array edge increases rapidly, proceeding inwards (due to dielectric erosion), and stabilized J. Low Power Electron. Appl. 2021, 11, 2 15 of 44 about 30 µm from the edge. We can conclude that the range is about 30 µm and resistance is stable beyond that range. Figure 16b shows the spatial change in median resistance of 0.5 µm lines from step pitch structures. These structures contain two adjacent arrays at a constant0.5 µm lines coverage from stepof 50% pitch (L structures.= S) but differin Theseg line structures width. contain The array two on adjacent the right arrays contains at a 0.5constant µm lines coverage and an of abrupt 50% (L change = S) but occurs differing when line the width. line width The array on the on left the array right switches contains to0.5 2,µ 10,m lines50, or and 100 an µm. abrupt The impact change of occurs altering when the theline line width width at a on fixed the global left array density switches was analyzedto 2, 10, 50, by or measuring 100 µm. Thethe resistance impact of alteringof the 0.5 the µm line lines width as a function at a ﬁxed of global the distance density from was theanalyzed last wide by measuringline. We can the conclude resistance from of thethe 0.5chartµm that lines the as higher a function the difference of the distance in the from line widththe last outside wide line. the Wearray can from conclude the line from inside the chartthe array, that the the higher higher the the difference resistance in and the linethe interactionwidth outside length the for array the fromlines theinside line the inside array. the For array, line width the higher < 10 µm, the resistancethe resistance and was the stabilizedinteraction after length 20 µm. for theHowever, lines inside for a theline array. width For of 50 line µm, width the interaction < 10 µm, the length resistance increased was tostabilized around after60 µm. 20 Figureµm. However, 16c also forshows a line the width effect of of 50 abruptµm, the coverage interaction change length for increased a step in patternto around coverage 60 µm. from Figure 10% 16 (L/Sc also = 1/9 shows µm) theto 90% effect (L/S of = abrupt 9/1 µm). coverage Figure change16b shows for athat step if thein pattern line width coverage ≤ 15 µm from and 10% the (L/Smaximum = 1/9 coverageµm) to 90% difference (L/S = 9/1betweenµm). arrays Figure is 16 <30–45%,b shows thethat resistance if the line variation width ≤ will15 µ bem <10% and the and maximum controllable. coverage This type difference of information, between translated arrays is <30–45%,into a set of the DRs, resistance is presented variation later. will be <10% and controllable. This type of information, translated into a set of DRs, is presented later.

(a) (b)

(c)

Figure 16. Pattern interaction distance for Cu. ( a)) Median Median resistance resistance of lines in an array consisting from line width of 3 µmµm and coverage of 75% 75% as as a a function function of of location location from from the the array array edge. edge. (b (b) )Changes Changes in in resistance resistance in in 0.5 0.5 µmµm line/space line/space array array as asa function a function of ofdistance distance from from a step a step in in line line width width (at (at the the same same global global density). density). ( (cc)) Median Median sheet sheet resistance resistance variation variation as a function of distance from a step in pattern density (from 10% to 90%) [16]. function of distance from a step in pattern density (from 10% to 90%) [16].

4. AA, Poly, and Al Global Coverage Rules

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4. AA, Poly, and Al Global Coverage Rules Density rules were introduced into the DRM by the manufacturers to manage variation in the line height caused by the CMP process, as well as differences in the line width caused by RIE processes. The primary solution to minimize this variation is to add a nonfunctional and electrically meaningless AA, poly, and metal polygons in order to try and achieve an even global coverage of AA or metal across the die. For DRC (DR checking) purposes, the global coverage is mostly calculated (e.g., for poly) as Drawing Poly OR Dummy Poly Global Coverage = . Overall Chip Area The RIE process used for patterning is sensitive to the density over the wafer. In this case, the etch process was designed to maximize the etch rate, and regions with a large open area (clear on mask or low coverage) will be faced with local low plasma densities and low etch rates. The simple process explanation for Al etch is that the lower the pattern density, the higher the amount of Al to be etched. For Cl-based RIE, it means higher consumption of Al atoms during etching, which decreases the Cl atom density and etch rate. Insertion of dummy patterns is one of the ways to reduce the macro-loading that takes place due to overall depletion of the reactants with more exposed etch areas. The level of macro-loading also depends on the process chamber design and the process parameters, mostly the gases and the power. Naturally, thicker layers (e.g., >1.5 µm Al layer) require longer processing times and therefore suffer from larger variations. During Al RIE, polymer generation protects the sidewalls. However, excessive polymers due to the long process time may cause the profile to become sloped. The micro-loading effect means that dense lines will have lower etch rates than isolated lines. A “ground-rule” for data leading to dark layers (e.g., poly or Al, where the drawn data mean chrome on the mask and positive photoresist on the wafer) is that isolated lines will have higher etch rates, so there are lower critical dimensions (CDs) vs. dense lines. This also leads to iso-dense CD bias. In many cases of Al etch, polymers generated during the RIE process protect the sidewalls and yield larger CDs for isolated lines. A team from X-FAB [19] studied the impact of different global densities on the 3 µm Al profile and line width dimensions. A 3 µm Al line is also typical in Cu technologies and is located below the passivation. The layer is used for bonding purposes as well as for connecting different bonding pads as RDL. Global coverage lower than RDL.C.1 (see Table1) may induce fewer polymers due to there being less photoresist available, which leads to sidewall attacks and potential bottom notching. Low coverage also causes large CD bias. Coverage higher than RDL.C.2 yields low etch rate and risks an incomplete etch with potential short and high CD bias. A way to set the global coverage limits is to measure the dependency of the sheet resistance—for the same coverage, wider lines will have lower sheet resistance due to their larger grains. The higher the coverage or larger the line CDs and lower the sheet resistance. To satisfy upper specified limit for all line widths, the minimal coverage should be set to 10–15%. For a poly etch, typical numbers for GC.C.1 and GC.C.2 are about 10% and 45%, respectively. J. Low Power Electron. Appl. 2021, 11, 2 17 of 44

Table 1. Active area (AA), Poly, and Al metal global coverage rules.

Rule Rule Description Action Rule Related to: AA.C.1 Active area coverage min To eliminate STI dishing, which can cause GC or CS DOF issues. To ensure a complete oxide removal from nitride over the AA, which can AA.C.2 Active area coverage max have gate oxide integrity issues. GC.C.1 Poly coverage min To eliminate over-etch, overly narrow poly CDs, and sidewall damage. To eliminate micro-loading effects during etch that can cause incomplete GC.C.2 Poly coverage max etch and poly shorts. To eliminate over-etch, very narrow isolated lines, sidewall attack, etc. RDL.C.1 Al coverage min Around 30% for 3 µm [19]. To eliminate micro-loading effects during Al etch, which can yield RDL.C.2 Al coverage max incomplete etch and metal shorts. Around 60–70% for 3 µm [19].

5. AA and Copper Local Coverage Rules Local coverage rules (Table2) were introduced by manufacturers to support the CMP process. For DRC purposes, the checking window is stepped in most cases, by half-size of the window size. e.g., a window of 200 µm × 200 µm will step by 100 µm, that is, each location on the wafer is included in four different checks.

Table 2. AA and copper local coverage rules.

Rule Rule Description Action Rule Related to: Active area coverage in a AA.C.3 min To eliminate STI dishing, which can cause GC or CS DOF issues. window of A × A step (A/2) Active area coverage in a To ensure a complete oxide and Nitride removal from the AA, AA.C.4 max window of A × A step (A/2) to eliminate Gate oxide integrity issues. To eliminate an accumulated planarized degradation due to Metal coverage in a window M.C.3 min development of a step. Typical value is around 20% [20] or of M × M step (M/2) 30% [18], depending on the window size (M: 20–150 µm). To eliminate local dishing. The amount of dishing also depends Metal coverage in a window M.C.4 max on the line width. Typical value is about 80% [20] or 70% [18], of M × M step (M/2) window size and line width dependent (M: 20–150 µm). Metal coverage gradient of a To eliminate thickness variation and potential shorts. Typical M.C.34 window to max value is 35–45%. surrounding windows Effective emissivity in a To eliminate temperature variation, mostly at S/D rapid anneal. AAGC.C.3 min window of R × R Step R Typical value can be 0.50. See Section 10.10 for details. Effective emissivity in a To eliminate large temperature variation, mostly at S/D rapid AAGC.C.4 max window of R × R Step R anneal. Typical value can be 0.70. See Section 10.10 for details. Effective emissivity gradient To eliminate large temperature variation, mostly at S/D rapid AAGC.C.34 of a window to max anneal. Typical value can be 0.15. See Section 10.10 for details. surrounding windows

The coverage range between maximal and minimal density is reduced as technology advances. For copper technology, a typical minimal coverage is 10–15%. The typical maximum coverage is 80%, but this is reduced for advanced technologies to about 73% or even <70%. In many cases, instead of or in addition to the maximum coverage reduction, the window size is also reduced. Typical windows of 200 µm × 200 µm with a step of 100 µm have been reduced to 100 µm × 100 µm with a step of 50 µm or even lower. For example, coverage ranged from 35% to 70% in a window of 10 µm × 10 µm [21]. In addition, the gradient requirement (see rule M.C.34) was introduced, seeking a maximal value of 30–50%. J. Low Power Electron. Appl. 2021, 11, 2 18 of 44

6. Minimum and Maximum Copper Coverage Design Rule Setting Setting both minimal and maximal coverage rules can be based on line resistance measurements combined with SEM analysis. The sheet resistance is inversely proportional to the line thickness (t); thus, a line located at a high coverage area will face dishing and higher resistance, similar to the pattern interaction distance study described earlier [16]. The line resistance depends on surface and interface scattering, which becomes domi- nant as the relative thickness of the diffusion barrier increases with technology scaling and due to the reduction in the film thickness that becomes comparable to the mean free path (which is ≈40 nm at room-temperature). In addition, the line width and film thickness reduction lead to smaller grain sizes and a short distance between scattering barriers. The result is more scattering from the sidewalls and from the grain boundaries. More details on the line width resistivity dependency are given in [22,23]. Therefore, setting the coverage rules needs to take into consideration the line width. For this purpose, dedicated test chips were developed, i.e., the MIT vehicle [24] described earlier that was also used by IDMs [16] and foundries [18]. This test chip contains several modules, where each module is larger than the copper CMP range. Using the test chip, we found the dependency of sheet resistance on line width at different densities (Figure 17a). For narrow lines (<1–3 µm), the scattering effect is seen clearly with a negligible coverage dependency. For wide lines (>5–10 µm), the dishing effect yields higher sheet resistance, with a clear coverage dependency—the higher the coverage for the same line width, the stronger the dishing. Using the maximum/minimum sheet resistance limits, as defined for the technology, and taking into consideration the process variability, rules M.C.3 and M.C.4 can be extracted without any dependency on line width. Afterwards, the maximal line width that can be used with the technology (without metal slits) can be extracted, using the upper limit of the sheet resistance and the upper density limit. Analysis should also take into consideration that thicker metal lines have larger grain sizes that slightly reduce the sheet resistance. In Figure 17, line width where dishing begins is easily observable. Sheet resistance charts, like the one shown in Figure 17a, are used to enhance the accuracy of RC extraction of interconnects. For each segment of a metal line, the number of squares (width/segment length) is calculated. Then, a local window is defined around the segment and the local coverage is extracted. This local coverage, together with the line width, is used to define the local effective sheet resistance. Finally, the segment resistance is calculated by multiplying the number of squares with the local effective sheet resistance. The team from LG Electronics developed a very similar process that consists of CMP modeling for accurate RC extraction [25]. Analysis of Figure 17 shows that an array consisting of narrow lines only has a higher coverage limit than an array with wide lines only. The definition of a “wide” line can also be extracted from Figure 17a, and it depends on process parameters like the metal thickness, slurry type, the amount of CMP overpolish, and the R range. A typical value for a wide line can be >4–8 µm. Lines with a width below the figure taken for a wide line are referred to as “narrow.” In Figure 17b, we describe the minimal and maximal line width and space, based on the coverage limitations. For narrow lines, a fine space can be used, delimited by M.C.4narrow. Using wide lines demands larger spaces limited by M.C.4wide. The line/space domain is limited by the minimal and maximal line width as well as the minimal line space. This coverage dependency on line width is integrated into the coverage rules. J.J. Low Low Power Power Electron. Electron. Appl. Appl.2021 2021,11 11, x FOR PEER REVIEW 20 of 46 , , 2 19 of 44

FigureFigure 17.17.Setting Setting coverage coverage limits limits considering considering line line width. width. (a) ( Oura) Our results results for sheetfor sheet resistance resistan vs.ce line vs. widthline width at different at different local densitieslocal densities and (b and) schematic (b) schematic illustration illustration showing showing the allowed the allowed line/space/coverage line/space/coverage envelope. envelope.

WithSheet theseresistance dependencies, charts, like we the can one set shown a simplified in Figure design 17a, guideline—it are used to enhance is better the to replaceaccuracy a singleof RC wideextraction line with of interconnects. several narrow For lines. each This segment costs more of a metal design line, area the but number allows aof higher squares maximum (width/segment local coverage length) to is be calculated. used. Then, a local window is defined around 7.the Dummy segment AA and (DAA), the local Dummy coverage Poly is extracted. (DGC), and This Dummy local coverage, Metal (DM) together Rules with the line width, is used to define the local effective sheet resistance. Finally, the segment resistance The dummy rules were set by the integration team for two main reasons: first, to be is calculated by multiplying the number of squares with the local effective sheet resistance. able to conduct quality assurance (QA) on the dummy insertion utility in order to ensure The team from LG Electronics developed a very similar process that consists of CMP mod- that a proper fill was done; and second, to guide the designer in case manual dummy eling for accurate RC extraction [25]. insertion is required at local spots that faced with poor insertion efficiency. Table3 lists Analysis of Figure 17 shows that an array consisting of narrow lines only has a higher some of these rules. coverage limit than an array with wide lines only. The definition of a “wide” line can also Setting rule DAA.D.1 needs to consider stress induced into the MOSFET by the STI be extracted from Figure 17a, and it depends on process parameters like the metal thick- due to the length of oxide diffusion (LOD) and oxide space effects (OSE). Researchers ness, slurry type, the amount of CMP overpolish, and the R range. A typical value for a from AMD [27] showed an example using the DAA to improve 65 nm standard cell library wide line can be >4–8 µm. Lines with a width below the figure taken for a wide line are performance. From this example, we can list the following guidelines: referred to as “narrow.” In Figure 17b, we describe the minimal and maximal line width Guideline 1: Insertion of DAA next to NMOSFET regions should be in the lateral and space, based on the coverage limitations. For narrow lines, a fine space can be used, direction only. Then, the STIW (STI width) parallel to the poly gate will be reduced, resultingdelimited in by higher M.C.4narrow. electron mobility. Using wide lines demands larger spaces limited by M.C.4wide.Guideline The 2: line/spaceFor the PMOSFET, domain is regionslimited nearby the the minimal P+ AA regionand maximal should line be left width blank as inwell the as lateral the minimal direction line and space. DAA This insertion coverage should dependency occur in on the line orthogonal width is directionintegrated only. into Bythe that, coverage the STIL rules. (STI length) orthogonal to the gate is reduced, resulting in higher hole mobility.With Following these dependencies, these guidelines we can improves set a simp the overalllified design circuit guideline—it performance byis better 8% [27 to]. replace a single wide line with several narrow lines. This costs more design area but allows a higher maximum local coverage to be used.

7. Dummy AA (DAA), Dummy Poly (DGC), and Dummy Metal (DM) Rules

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Table 3. Dummy AA (DAA) and dummy metal (DM) rules.

Rule Rule Description Rule Related to: Minimum/maximum width of DAA. For setting, need to consider DAA.W.1 Width of DAA coverage, utility CPU time and overall file size and insertion efficiency. Typical value of 90 nm is 0.4–0.6 µm [26]. Minimum/maximum space of DAA. For setting, need to consider DAA.S.1 Space between two DAA coverage, stress induced (LOD, OSE), and insertion efficiency. To eliminate any effect on the device: junction leakage, change in length DAA.D.1 Distance between DAA to AA(dg) of oxide diffusion (LOD) or oxide space effect (OSE) modeling. DAA.D.2 Distance between DAA to WN(dg) To eliminate low voltage N–well junction breakdown. Minimum/maximum width of DM. For setting, need to consider DM.W.1 Width of DM coverage, multilayer coverage, utility CPU time, and overall file size and insertion efficiency. Typical width for 65 nm is 0.4–0.55 µm [26]. Minimum/maximum width of DM. For setting, need to consider DM.S.1 Space between two DMs coverage, multilayer coverage, utility CPU time, and overall file size and insertion efficiency. Typical number for 65 nm is 0.1–0.55 µm [26]. To eliminate performances degradation due to fringe parasitic DM.D.1 Distance between DM to M(dg) capacitance or low coverage (priority 1, see text). Typical number of 65 nm (not to signal line) is 0.3–0.7 µm [26]. Distance between DM below or DM.D.2 To eliminate degradation due to fringe capacitance (priority 2, see text). above metal signal line To eliminate inductor degradation: Q-factor degradation due to coupling capacitance and inductance degradation due to eddy currents. See text. DM.D.4 Distance between DM to Inductor. Typical value is >30 µm. DM.D.41 is for distance at the center of the inductor DM.D.42 is for distance outside the inductor.

If DAA is too close to the WN (N-Well) junction (rule DAA.D.2), it will degrade the WN/PW and the WN/Psub junction breakdown [28]. The team from Tower found that without dummies, the intrinsic WNH/Psub (high-voltage WN)/Psub) junction breakdown (BV) was about 22 V. However, after DAA insertion, a soft leakage current was observed, which increased as the EXWELL (a native layer to block the P-Well implant) grew. The explanation for this is that the DAA located close to the WN edge (DAA.D.2 < 1 µm) introduced a leakage path from the Ntap, through the depletion region at the EXWELL into the silicide dummy and to the substrate. The larger the EXWELL, the larger the WNH depletion region and the higher the leakage. The metal dummy’s width and space are set based on the desired coverage under the limitations of the insertion efficiency. Another limitation for having fine dummy features is the overall file size, which can increase significantly with finer dummy features. For analog and RF circuits, both DM.D.1 and DM.D.2 are critical rules. The distance setting is a balance between insertion efficiency and coupling capacitance to active metal lines at the same layer or the wire below or above. A smaller distance means there are more dummies and a higher coupling capacitance, which slows down the IC. In most cases, the common practice is to set a very conservative distance (>1–5 µm), so that the coupling capacitance is negligible compared to the total capacitance of the line.

8. Multilevel Coverage Integration Effects Low local AA coverage (750 A, and the bias between wide and narrow STI (at the same site location on the wafer) was >1500 A. The high dishing introduced a focus limitation during GC J. Low Power Electron. Appl. 2021, 11, 2 21 of 44

photo, and because of that, the GC CDs were very narrow (>20% compared to the regular case), yielding a high leakage of current. In many cases, an anti-reﬂecting coating (ARC) layer is placed above the poly. This layer is very sensitive to topography, so in the case of severe STI dishing, the ARC thickness over the AA will be thinner and yield narrow poly lines. The introduction of DAA together with CMP process optimization resolved the dishing problem and led to regular transistor behavior (Figure 18b). Another potential problem is with the contact landing on poly located over a large STI area—the contact etch is not deep enough to reach the poly line. An example of another issue we faced was with a set of interdigitized M1 lines with a long parallel length of around 3 m, drawn with the minimal L/S allowed by the platform DRM. The structure was located over a large area of STI only (without dummy AA) and showed a low yield of 40% due to M1 shorts. The same structure (at the same mask setting) located over STI after DAA insertion (local coverage ≈45%) exhibited a 100% yield. Figure 18c schematically shows that due to the severe dishing in STI, the ILD1 also suffered from non-planarity, as well as the IMD1 layer deposited afterwards. Due to the single damascene integration, the copper CMP did not completely remove the metal and the Ta/TaN barrier metal located below the Cu in between the lines, causing a short. Excessive AA coverage (>AA.C.4) can introduce defects such as oxide leftovers on the AA, as a result of insufﬁcient polishing during AA CMP. These defects may degrade the gate oxide integrity. The level of the defect depends on the design type: Figure 18d shows a typical design of a switch we manufactured, organized with four columns with >90% of large AA strips, 15–25 µm width and a narrow STI (<1 µm) between them. The result was highly defective along these columns, as seen in the KLA defect map. The analog module and the digital library showed much less defectivity. The design solution for such a layout J. Low Power Electron. Appl. 2021, 11, x FOR PEER REVIEW 23 of 46 is to slightly increase the AA space and to limit the AA strip width so that local coverage is only 85–90%.

Figure 18.FigureMultilevel 18. Multilevel coverage integrationcoverage integration effects of STI/Poly effects of andSTI/Poly STI/M1. and (aSTI/M1.) An example (a) An ofexample an inverter of an surrounded by a wide STI area,inverter a low surrounded gate width, by and a wide high transistorSTI area, a leakage; low gate (b width,) with regularand high AA transistor coverage leakage; and optimized (b) with AA CMP process; (c) a simpleregular explanation AA coverage of the M1 and mechanism optimized for AA shorts CMP due process; to low (c AA) a simple coverage; explanation and (d) an of examplethe M1 mecha- of excessive local AA coverage,nism leading for to shorts very due high to levels low AA of nitride coverage; residues. and (d) an example of excessive local AA coverage, leading to very high levels of nitride residues.

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Similar to the problem described for M1 regarding low AA coverage area (with STI dishing), dual damascene integration can also accumulate non-planarity from previous metal layers. CMP at each layer at the BEOL can eliminate some of the non-planarity. How- ever, for severe cases, or in the absence of an intermediate dielectric CMP, the topography created by pattern-dependent polishing is transferred to the next metal level [16]. This is illustrated schematically in Figure 19, showing the topography along different process steps. The IMD deposited after copper CMP on the lower level is conformal with the underlying surface proﬁle. The non-planarity persists after dual-damascene patterning, etch, and Cu plating. It is subsequently removed during the initial stage of the copper CMP (bulk Cu removal). When the copper is removed completely from the raised areas on the IMD, some copper and mostly Ta/TaN residues remain in the depressions created by dishing and erosion of the underlying layer. Further CMP to clear the residue can cause the lines on the raised regions to suffer from over-polishing. The resistance of a dual-damascene conductor is therefore determined by a complex interaction of its layout environment on both the layer being polished as well as the underlying layers [16]. Figure 19 provides further explanation of the process integration. The effect of the multilevel metal coverage on resistance was demonstrated by the Tower team ([29]; Figure 20) using a dedicated test chip that was internally designed with three separated long M5 resistors, and with two conﬁgurations—without any M1–M4 dummies underneath, and with dummies that had a coverage of 36%. The lack of dummies increased the resistance by around 40% in all three cases. In addition, the resistance distribution was almost doubled, as the height of the copper line strongly depended on the Cu CMP over polish. Note that Figure 20 refers to resistance (not sheet resistance). The differences in resistance between the three different structures are related to the layout J. Low Power Electron. Appl. 2021, 11, x FOR PEER REVIEW 24 of 46 of the test chip (different length of connection lines) and not to coverage dependency or process effects.

FigureFigure 19. 19.Multilevel Multilevel coverage coverage integration integration effectseffects (BEOL).(BEOL). ( aa)) After After the the M1 M1 trench trench etch, etch, whic whichh has has an anarea area with with very very low low coveragecoverage and and an an area area with with high high coverage; coverage; ( b(b)) followingfollowing M1 Cu Cu CMP, CMP, the the high high coverage coverage area area is isfaced faced with with dielectric dielectric erosion erosion andand M1 M1 dishing; dishing; (c ()c after) after ILD2 ILD2 and and inter-metalinter-metal dielectric dielectric 2 2(IMD2) (IMD2) depo deposition,sition, the the non-planarity non-planarity from from M1 is M1 now is nowcopied copied to the IMD2 and M2 trench etch. The M2 trenches at the high M1 coverage area are deeper than those over the M1 low to the IMD2 and M2 trench etch. The M2 trenches at the high M1 coverage area are deeper than those over the M1 low coverage area; (d) after M2 electroplating; (e) after M2 Cu CMP. Due to IMD2 non-planarity, there is a strong possibility coverageof M2 shorts area; (ind) the after high M2 M1 electroplating; coverage area. (e ()f after) A longer M2 Cu polish CMP. time Due reduces to IMD2 the non-planarity, possibility of M2 there shorts. is a strongHowever, possibility the M2 of M2lines shorts over in the the M1 high low M1 coverage coverage area area. now ( fhave) A longer high resistance polish time [16]. reduces the possibility of M2 shorts. However, the M2 lines over the M1 low coverage area now have high resistance [16]. The effect of the multilevel metal coverage on resistance was demonstrated by the Tower team ([29]; Figure 20) using a dedicated test chip that was internally designed with three separated long M5 resistors, and with two configurations—without any M1–M4 dummies underneath, and with dummies that had a coverage of 36%. The lack of dummies increased the resistance by around 40% in all three cases. In addition, the resistance distribution was almost doubled, as the height of the copper line strongly depended on the Cu CMP over polish. Note that Figure 20 refers to resistance (not sheet resistance). The differences in resistance between the three different structures are related to the layout of the test chip (different length of connection lines) and not to coverage dependency or process effects. The sheet resistance of Cu lines depends on three layout factors that affect both the overall thickness and the line CDs. The following are the result of a systematic experiment that was done in order to characterize each of the factors (see Figure 20):

• The topography depends on the layers under the line (K1). A lack of metal structures or dummies under wires will lead to thinner metal lines. This degradation is due to the accumulated topography and depends on the number of metal lines and low coverage at the area under the line in-use, as explained at the left side of the structure in Figure 19. Figure 20b shows the change in metal sheet resistance of a dense resistor, located at level 8 of a metal test chip. The resistor was placed at each metal line with a local coverage of about 45%. However, the metal dummies underneath were removed, leading to very low local coverage (<10%). The resistance for each metal resistor was normalized to the M2 resistance, as M1 dummies have been included. The higher the non-planarity, the higher the sheet resistance, and it is saturated ~20%. Similar isolated metal resistors showed the same dependency.

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The sheet resistance of Cu lines depends on three layout factors that affect both the overall thickness and the line CDs. The following are the result of a systematic experiment that was done in order to characterize each of the factors (see Figure 20):

• The topography depends on the layers under the line (K1). A lack of metal structures J. Low Power Electron. Appl. 2021, 11, x orFOR dummies PEER REVIEW under wires will lead to thinner metal lines. This degradation25 of 46 is due

to the accumulated topography and depends on the number of metal lines and low coverage at the area under the line in-use, as explained at the left side of the structure •in FigureThe local 19 .coverage Figure 20variabilityb shows around the change the line in (K metal2). The sheet high resistancelocal coverage of aaround dense resistor, locatedthe line at levelcaused 8 dishing of a metal and testyielded chip. thinner The resistormetal. Figure was 20c placed shows at the each metal metal sheet line with a localresistance coverage of ofa set about of short 45%. resistors, However, having the a uniform metal dummies (45%) coverage underneath underneath were but removed, with different local coverage around the line. With higher coverage around the line, leading to very low local coverage (<10%). The resistance for each metal resistor was the sheet resistance increased by up to 25%. For this experiment, only narrow lines normalized(width < 0.5 to µm) the that M2 have resistance, limited dependency as M1 dummies on line dishing have beenwere used. included. The higher •the The non-planarity, regular photolithography the higher conditions the sheet du resistance,ring resistance and patterning it is saturated such as ~20%. focus Similar isolatedand exposure. metal resistors For this experiment, showed the we same used dependency.the optimal conditions. • TheThe local above coverage data enable variability us to predict around with the high line accuracy (K2). what The highthe effective local coverage sheet re- around sistancethe line will caused be based dishing on the and three yielded dependenci thinneres listed. metal. For example Figure 20(Figurec shows 20d), the an ex- metal sheet perimentalresistance comparison of a set of of short two resistors resistors, with having the layout a uniform and coverage (45%) conditions coverage listed underneath in but Figurewith different20 showedlocal [29] (i) coverage for M5 resistor, around with the vs. line. without With any higher metal coverage coverage at M1–M4, around the line, thethe K sheet1 is ≈1.176 resistance and (ii) for increased a very high by M5 up local to coverage, 25%. For due this to experiment,the 7 µm line around only narrow and lines with(width space < 0.5of 0.2µ m)µm that(97% havelocal coverage), limited dependency K2 is ≈1.27. To on account line dishingfor both dependencies, were used. K1 × K2 = 1.176 × 1.27 = 1.49, which is close to the experimental result of 1.54. The difference • The regular photolithography conditions during resistance patterning such as focus may be related to the fact that the K2 chart was not normalized to yield 1 at a local coverage ofand 45%. exposure. For this experiment, we used the optimal conditions.

0.15 L/S=0.20/0.24 L/S=0.20/1.05 L/S=1.0/0.21 0.14 M5 Cov=45% M5 Cov=16% M5 Cov=82.6%

0.13

0.12

0.11

0.1

0.09

0.08

0.07

0.06

0.05 w/o With Dummy's w/o With Dummy's w/o With Dummy's

(a) (b)

1.3

1.25 Increase due to local dishing 1.2

1.15

1.1

1.05 M

e 1

s i

s 0.95 t

a 5 20 35 50 65 80 95

n c

e Local Metal Coverage around the resistor (%)

Figure 20.FigureThe dependency20. The dependency of sheet of sheet resistance resistance on on the the local local coveragecoverage under under and and around around the line. the ( line.a) M5( resistancea) M5 resistance with- without out and with M1–M4 (36% coverage) dummies under the M5 resistor; (b) the dependency (K1) of metal sheet resistance and with M1–M4 (36% coverage) dummies under the M5 resistor; (b) the dependency (K1) of metal sheet resistance on the on the number of metal layers below, which do not have metal structures; (c) the dependency (K2) of metal sheet re- number of metal layers below, which do not have metal structures; (c) the dependency (K ) of metal sheet resistance on the sistance on the local coverage around the line; and (d) a final test case considering both effects2 (K1 × K2) [29]. local coverage around the line; and (d) a ﬁnal test case considering both effects (K1 × K2)[29].

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The above data enable us to predict with high accuracy what the effective sheet resistance will be based on the three dependencies listed. For example (Figure 20d), an experimental comparison of two resistors with the layout and coverage conditions listed in Figure 20 showed [29] (i) for M5 resistor, with vs. without any metal coverage at M1–M4, the K1 is ≈1.176 and (ii) for a very high M5 local coverage, due to the 7 µm line around and with space of 0.2 µm (97% local coverage), K2 is ≈1.27. To account for both dependencies, K1 × K2 = 1.176 × 1.27 = 1.49, which is close to the experimental result of 1.54. The difference may be related to the fact that the K2 chart was not normalized to yield 1 at a local coverage of 45%.

9. Design for Manufacturing Copper Lines Based on the dependencies described in Section8, we developed some guidelines in an attempt to minimize the defectivity and reduce variability. These guidelines can be easily coded to recommend layout rules and/or can be implemented in the Place and Rout (P&R) tool. The ﬁrst guideline is for checking the coverage around sensitive signal lines. The coverage limits can be much tighter than the platform limits. Another option is to check the metal coverage of the metal line below. However, in many cases, the routing is done automatically by the P&R tool, which is limited by the number of boundary conditions. The second guideline is related to the high potential for metal shorts between two lines, due to poor planarity of the metal layers below, as explained in Figure 19e. A larger space is recommended between two lines that cross above a high coverage metal area located below. The coverage of the metal underneath is checked and, if the coverage is above the recommended limit, the space between the two lines above should be increased. The third guideline is related to the metal line width, which should be greater if the line crosses a locally low coverage area (

10. Different Methods for Dummy Fill Insertion 10.1. Dummy Shapes, Tools, and Insertion Efficiency In mature technologies (65 nm and above), dummies are relatively large polygons that do not get any optical proximity correction (OPC) to save computing resources. However, for advance technologies, such as 28–14 nm or lower, with a very high density of dummies that have strong proximity to the drawing data, the dummies should also receive OPC to achieve a high design accuracy [30]. The dummy fill polygons can have different shapes and spaces that set the density. The simple polygon has a square shape placed in a simple array or staggered array fill pattern. More complex dummies are based on a donut having an octagon shape or a multipolygon as an octagon donut with a square dummy inside. For some of the methods, like single-size dummy insertion or rule-base dummy insertion, the regular DRC tools can also be used. For more advanced insertion methods, more sophisticated tools are needed [31]. There is no formal method to quantify the insertion efficiency. One simple way might be to compare the number of DRC violations before and after insertion. However, this method does not provide any information on the average and distribution of the coverage for proper support of the CMP processes. Here, we propose a simple expression for insertion efficiency (or “insertion yield”):

f illed 2 ∑ (Cij − Ctarget) Insertion_E f f iciency = 1 − , drawing 2 ∑ (Cij − Ctarget) J. Low Power Electron. Appl. 2021, 11, 2 25 of 44

f illed drawning where Cij and Cij are the coverage at each window located at the design at ij coordinates after and before insertion, respectively; Ctarget is the desired average coverage, and at many cases is set as 0.5 × (M.C.3 + M.C.4).

10.2. Single-Size Tile Filling The first and most simple way of automatic pattern generation was noted first by Mentor Graphics [32] and later on together with TSMC [33]. The basic fill algorithm consists of the creation of a full array of dummies, followed by the elimination of dummies that are in violation of the manufacturing design rules. The main steps are as follows: Step 1: Drawing data. Step 2: Creation of a blindly flat cartesian array of dummies, based on the following inputs: dummy width, length, and space. For example, a tile array having W × L = 0.8 µm × 0.8 µm and 1 µm spacing will have a coverage at large “open area” of

(0.8)2 = 19%. (1 + 0.8)2

Step 3: The original data are sized-up by the minimal space of the drawing data to the dummy. The output is the “no-fill area” that dummies should not overlap with. Step 4: In the dummy array, dummies that overlap with the “no-fill area” are clipped and dummies within the no-fill area are removed. Step 5: Any dummy with an area below the minimum as defined by the IC manufac- tures (see rule DM.A.1) is removed. An alternative is to remove any dummy that interacts with the “no-fill area.” Another option in Step 1 is to scan the design for local coverage through a stepping window, e.g., with dimensions of 500 µm × 500 µm and a step of 250 µm. Later, dummies will be included only in windows that have an initial coverage below the minimum specified by the IC manufacturers (M.C.3). Step 3 is as above, and in Step 4, any window with a coverage > M.C.3 will also be part of the “no-fill area.” Step 5 would remain the same. This simple method is the one used in 0.25–0.13 µm technologies for AA, GC, and Al BEOL. However, this method often adds more fill than necessary. This is due to the single-sized tile and the algorithm that does not take into consideration the initial local coverage nor the coverage gradient between two neighboring spots. The impact on timing might be significant.

10.3. Rule-Based (Linear-Programing) Dummy-Fill Rule-based tiling is based on the STI dielectric thickness being directly proportional to the local pattern density. Hence, the physical design rules require a local pattern density as listed in Tables1 and2. Wherever there is an open space large enough, tiles should be inserted to increase the local pattern density within the bounds [34]. The density rule can consider a single layer only, or a multilayer (one or even two layers below), in order to eliminate the introduction of tiles over sensitive signal lines or RF devices located below or above. However, the multilayer approach yields many cases of unfilled locations. The basic fill algorithm consists of a local coverage calculation followed by a selective tile insertion at each window. The last step is to eliminate the dummies that violate the IC manufacturers’ design rules. Figure 21 shows the coverage density of the M1 layer before and after the dummy fill. All windows that have no metal (around 25% from the total chip area) and violate M.C.3 would now be filled. The statistics before filling showed an average coverage of 26% and 1σ of 17.7%. After filling, the average goes up to 36% and there is a much tighter distribution across the chip, with 1σ of 7%. J. Low Power Electron. Appl. 2021, 11, x FOR PEER REVIEW 28 of 46

J. Low Power Electron. Appl. 2021, 11,dow 2 is defined [35]. Then, the minimum variation formulation seeks to maximize the 26min- of 44 imal window density. A detailed mathematical explanation on the minimum variation interactive method can be found in [17].

500 500

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(a) (b)

FigureFigure 21. 21. AnAn example example of of M1 M1 coverage coverage statistics: statistics: (a ()a )before before dummy dummy fill ﬁll and and (b (b) )after after the the minimum minimum variation variation rule-based rule-based dummydummy fill, ﬁll, using using the the Tian Tian method method [34]. [34].

TheAnother dummy similar fill method approach is optimized is the minimal by adjusting variation the methodsettings for [17 ,the35], tile which dimensions seeks to maximize the minimal window density. The method first calculates the effective density of and space for each type of dummy. The goal is to achieve high insertion efficiency, that is, the layout based on the local coverage and the material thickness after CMP (based on the to eliminate spots with low coverage and without dummies due to fine drawing lines CMP model). It then calculates a target-effective density as the mean of the effective density. having space that is slightly below DM.W.1 + 2 × M.S.1 (see Table 3). Figure 22 shows an Based on the difference between the local effective density value and the target effective example of an optimized dummy fill run-set, with several different sizes of square tiles. density value, tiles are prioritized and several are selected simultaneously for filling. The The IC (integrated circuit) is a full analog-specific IC (ASIC) including a large array of method then assigns dummy features in low-effective-density areas or removes the already single port SRAM (SP-SRAM), several blocks of standard cell libs, several analog modules, filled dummy features from high-effective-density areas. The process is repeated until and a phase shift lock (PLL) in an overall area of 5.5 mm × 5.5 mm. The chart shows the the uniformity of the effective density cannot be further improved or until the maximal coverage before and after filling for every window. The solid line represents X = Y, so each number of iterations is reached [17]. Based on the maximum density coverage (M.C.4), point on the chart is a window with or without dummies. defined by the IC manufacturers, the dummy tile inserted in any window is defined [35]. Then,The the main minimum success variation criteria of formulation the dummy seeks fill run-set to maximize optimization the minimal are as window follows: density. 1.A detailedAll windows mathematical that are explanationbelow the minimal on the minimum local coverage variation must interactive include dummies method canwith be founda coverage in [17]. ≥ M.C.3, 2. AllThe windows dummy fillthat method have a iscoverage optimized close by adjustingto or above the M.C.4 settings should for the not tile receive dimensions any anddummies. space for each type of dummy. The goal is to achieve high insertion efficiency, that 3.is, toThe eliminate overall spotscoverage with distribution low coverage after and filling without (see Figure dummies 21b) due should to fine have drawing an average lines havingthat spacefits with that the is slightlypolishing below process. DM.W.1 In addi + 2tion,× M.S.1 the distribution (see Table3). should Figure be 22 as shows tight as an examplepossible. of an From optimized a practical dummy point-of-view, fill run-set, the with insertion several should different be differential, sizes of square i.e., win- tiles. Thedows IC (integrated that are 1–5% circuit) higher is a than full analog-specificM.C.3 should have IC (ASIC) relatively including large tiles a large with array small of singlespaces port in SRAM order (SP-SRAM), to increase several the coverage. blocks ofHowever, standard windows cell libs, several that are analog very modules,close to andthe a phase target shift or even lock slightly (PLL) in above an overall the target area should of 5.5 mm get relatively× 5.5 mm. small The charttiles with shows large the coveragespaces before to minimize and after the filling coverage for every increase window. or should The solid receive line no represents tiles. The X =optimized Y, so each pointrun-set on the yielded chart is insertion a window efficiency with or withoutof 56% and dummies. was achieved by carefully setting the distance between dummy metal tiles to metal lines at the same level and above or below. A larger distance minimizes the coupling capacitance but may yield limited increase in coverage. 4. The run-set should block the insertion of tiles based on a predefined list of marking layers (blocking layers).

J. Low Power Electron. Appl. 2021, 11, x FOR PEER REVIEW 29 of 46

5. It should require minimum CPU resources, minimum running time, and not too large GDS file size after filling. Too large a file size will slow down the mask data preparation (MDP)/optimal proximity correction (OPC) process, the reticle enhancement technique (RET) activity, the file transfer to the mask shop, and the fracturing, among others. 6. For 20 nm technologies and below, the run-set should be able to support design with J. Low Power Electron. Appl. 2021, 11, 2 DP (double patterning) and TP (triple patterning). See, e.g., the work of the Samsung27 of 44 team, for a M2 layer with a self-aligned DP (SADP) process [36].

FigureFigure 22.22. DummyDummy fillfill run-setrun-set optimization:optimization: ((aa)) AnAn optimizedoptimized 1212 stepstep min-variationmin-variation rule-basedrule-based dummydummy fill. fill. ResultsResults areare forfor intermediate metal; (b) an example of non-optimized filling, with a too large distance from the dummy metal to drawing intermediate metal; (b) an example of non-optimized filling, with a too large distance from the dummy metal to drawing metals located below, at the same level and above; (c) an example of non-optimized filling, using a too long rectangle that metals located below, at the same level and above; (c) an example of non-optimized filling, using a too long rectangle leads to poor coverage; (d) non-orthogonal (shift) dummy insertion; and (e) shift dummy fill with an equal fringe capaci- thattance leads to drawing to poor lines. coverage; (d) non-orthogonal (shift) dummy insertion; and (e) shift dummy fill with an equal fringe capacitance to drawing lines. Figure 22a is our example for optimized filling with 56% insertion efficiency, and in The main success criteria of the dummy fill run-set optimization are as follows: it, we also explain “differential filling,” that is, high coverage tiles with a low coverage 1.windowAll windowsand low coverage that are belowtiles (or the no minimal tiles) for local high coverage coverage must windows. include Figure dummies 22b shows with an examplea coverage of a non-optimized≥ M.C.3, insertion run-set with an insertion efficiency of only 21.9%. 2.To eliminateAll windows performance that have adegradation coverage close due to to or fringe above M.C.4capacitance should between not receive the any dummy dum- lines mies.and the drawing metal lines, the boundary condition for M2 insertion was set con- 3.servatively,The overall by keeping coverage 3 distributionµm from drawing after filling M2 metal (see Figure lines 21andb) 1 should µm from have drawing an average M1 and M3that below fits with or above, the polishing respectively. process. As Ina result addition, of this the “stack distribution fill consideration,” should be as a tightlarge as possible. From a practical point-of-view, the insertion should be differential, i.e., amount of low-coverage windows did not fill and yield M2.C.3 violations. Figure 22c is windows that are 1–5% higher than M.C.3 should have relatively large tiles with small another example of non-optimized insertion, with an efficiency of 39%. Some of the 12 tile spaces in order to increase the coverage. However, windows that are very close to types were set to be long rectangles, not squares, with a small space. The idea was to fill the target or even slightly above the target should get relatively small tiles with large areas that need special shapes or orientation to maximize the fill density. However, the spaces to minimize the coverage increase or should receive no tiles. The optimized results showed a lack of coverage in many windows. The optimization process repeated run-set yielded insertion efficiency of 56% and was achieved by carefully setting the with different scenarios and included at least 10 different ICs for different applications as distance between dummy metal tiles to metal lines at the same level and above or the amount of blocking layers depend on the % of analog, RF, and other sensitive circuits below. A larger distance minimizes the coupling capacitance but may yield limited increase in coverage. 4. The run-set should block the insertion of tiles based on a predefined list of marking layers (blocking layers). 5. It should require minimum CPU resources, minimum running time, and not too large GDS file size after filling. Too large a file size will slow down the mask data preparation (MDP)/optimal proximity correction (OPC) process, the reticle enhancement technique (RET) activity, the file transfer to the mask shop, and the fracturing, among others. J. Low Power Electron. Appl. 2021, 11, 2 28 of 44

6. For 20 nm technologies and below, the run-set should be able to support design with DP (double patterning) and TP (triple patterning). See, e.g., the work of the Samsung team, for a M2 layer with a self-aligned DP (SADP) process [36]. Figure 22a is our example for optimized filling with 56% insertion efficiency, and in it, we also explain “differential filling,” that is, high coverage tiles with a low coverage window and low coverage tiles (or no tiles) for high coverage windows. Figure 22b shows an example of a non-optimized insertion run-set with an insertion efficiency of only 21.9%. To eliminate performance degradation due to fringe capacitance between the dummy lines and the drawing metal lines, the boundary condition for M2 insertion was set conservatively, by keeping 3 µm from drawing M2 metal lines and 1 µm from drawing M1 and M3 below or above, respectively. As a result of this “stack fill consideration,” a large amount of low-coverage windows did not fill and yield M2.C.3 violations. Figure 22c is another example of non-optimized insertion, with an efficiency of 39%. Some of the 12 tile types were set to be long rectangles, not squares, with a small space. The idea was to fill areas that need special shapes or orientation to maximize the fill density. However, the results showed a lack of coverage in many windows. The optimization process repeated with different scenarios and included at least 10 different ICs for different applications as the amount of blocking layers depend on the % of analog, RF, and other sensitive circuits that have a tight specification of timing. Products with different area sizes were also selected. The same optimization and QA were used for the cases when the dummy fill was done by the P&R tool. The foundry test element group (TEG) or technology qualification vehicle (TQV) dedicated a mask-set that included all test-chips for technology calibration, and qualification could not be used in most cases due to the large difference in overall topography compared to a regular IC. This was due to the many test chips and the number of bonding pads, which were not proportional to the IC area/application. Furthermore, many types of devices were grouped and placed in one area and were almost not included in other areas. Another criterion of success is that long conductors of the same metal level will have an identical (and minimal) coupling capacitance induced by the dummy tile. One of the ways to achieve this is to set the filling utility to not be on a regular grid but include an offset in both x and y directions that breaks the symmetry of the pattern. This offset also simplified the photolithography process by eliminating false alignment during wafer setting at the stepper or defect metrology tools. Figure 22d is an example of the popular dummy shift. Figure 22e presents a shift that also has the advantage of having the same fringe capacitance as any horizontal and vertical lines located nearby. More complex tiles (cell-based) are described later in this paper. Another important success criterion for optimal filling is the coverage gradient between each window and the surrounding neighbors (M.C.34). If there is too great a difference, then it impacts the polish rate and may yield metal residues with high potential for shorts. Another method for the dummy metal fill was proposed by the team from SMIC [37]. Their method was based on the fact that both the total pattern perimeter and the pattern density control the final topography. For the same local coverage, patterns with a longer perimeter will have smaller height differences.

10.4. Model-Based Driven Dummy Fill Model-based methods provide more accuracy and efﬁciency [34]. The method is based on analytical expressions formulated above (see Section 2.6) and describe the relationship between local patterns and ILD thickness. The method used a CMP model to identify locations (hotspots) where planarity was worse. Examples for CMP models are listed in [6]. The initial oxide density is not only proportional to the local pattern but also can be calculated as the summation of weighed local pattern density within a weighting region. The size of the weighting region depends on the CMP processing, similar to the CMP range. Based on these models, a two-step solution for dummy feature placement is proposed as J. Low Power Electron. Appl. 2021, 11, 2 29 of 44

follows: first, the minimum variation should compute the number of dummy features required in each small window. Second, place the calculated amount into each rectangle while optionally optimizing certain local properties. The team from TSMC used a similar approach but with some modifications [18]—their first two steps were similar, but they used a random generator to choose the pattern type such as rectangles, stripes, etc. In contrast to the Tian method [34], which uses square dummies to easily handle cases with vertical and horizontal lines, TSMC’s approach uses a randomized-shape dummy feature, thereby a spatial signature produced by the dummy feature will not be presented in the whole chip layout. Using this method, the mean coverage increased from ≈30% to ≈65%. Analysis of the coverage histogram before and after filling showed that the number of windows that had low coverage (50% compared to the rule base [38]. They used two types of tiles, i.e., “background” tiles that have a small feature size and pitch (≈50%), with the ability to have high yield of insertion, and the second tile that was 10 µm × 10 µm for large open regions.

10.5. Net-Aware and Timing-Aware Dummy Metal Fill A dummy fill can have undesirable impacts on the net capacitance yield path delays. An estimation for the timing impact of a 65 nm design is ≈4% [39]. A timing-aware (automatic annotation) track fill insertion flow, which was proposed by a team from the foundry Chartered (now GF) and Magma, consists of dummy fills by the router. The flow is shown in Figure 23. First, the routed database feeds into the router, which analyzes the density violations based on the density rules. After detecting the locations of density violations, a timing engine is invoked to do timing analysis while inserting the metal fills. The insertion is into the standard cell area only and will not touch any other IP (intellectual property) area or IOs (input/output). Based on that, we can set a ground-rule that inserted dummies near critical signal lines will have larger spaces than noncritical lines: ≥2–3 µm for clock paths and even ≥5 µm for critical paths. Finally, the timing was analyzed again to ensure performance was acceptable. The next step is to use the manufacture insertion utility to complete the coverage needs around IPs, IOs, and the overall IC. Using this hybrid approach, there is a minimal impact on design trimming with a uniform coverage across the IC. For the design of 65 nm technology with an area of 9 mm2, the maximum slack degradation value was improved from −101 psec (for the case of using only the foundry insertion utility) to −19 psec with the hybrid approach. A different and simpler work flow was proposed by the team from SEMTECH [40]. The workflow can prevent fill insertion around identified nets by setting larger space requirements or by removing inserted tiles around identified nets. The manufacturer insertion utility was also used. A floating fill, in comparison to a grounded fill, offers a smaller increase in the total capacitance and does not require power/ground routes for the fill geometry. However, a floating fill increases the coupling capacitance, which can cause signal integrity issues. A ground fill, despite its larger impact on the total capacitance and high routing costs that often lead to ECOs (engineering change orders), can be used as a substitute [41]. Shielding is widely used in integrated circuits to mitigate cross talk between coupled lines. In “passive” shielding, the power/ground (P/G) lines are routed as shield lines between critical signals interconnects to minimize the noise coupled from an aggressor to a victim line. Inserting shield lines between the aggressor and victim lines reduces the capacitive and inductive coupling between adjacent blocks [42]. It is difficult and consumes resources to connect the shield to the reference net. However, the metal fill can use whatever resources are left over and minimize the impact. This approach was experimentally tested by Intel [43] and yielded promising improvements. J. Low Power Electron. Appl. 2021, 11, x FOR PEER REVIEW 31 of 46

the ability to have high yield of insertion, and the second tile that was 10 µm × 10 µm for large open regions.

10.5. Net-Aware and Timing-Aware Dummy Metal Fill A dummy fill can have undesirable impacts on the net capacitance yield path delays. An estimation for the timing impact of a 65 nm design is ≈4% [39]. A timing-aware (automatic annotation) track fill insertion flow, which was proposed by a team from the foundry Chartered (now GF) and Magma, consists of dummy fills by the router. The flow is shown in Figure 23. First, the routed database feeds into the router, which analyzes the density violations based on the density rules. After detecting the locations of density violations, a timing engine is invoked to do timing analysis while inserting the metal fills. The insertion is into the standard cell area only and will not touch any other IP (intellectual property) area or IOs (input/output). Based on that, we can set a ground-rule that inserted dummies near critical signal lines will have larger spaces than noncritical lines: ≥2–3 µm for clock paths and even ≥5 µm for critical paths. Finally, the timing was analyzed again to ensure performance was acceptable. The next step is to use the manufacture insertion utility to complete the coverage needs around IPs, IOs, and the overall IC. Using this hybrid approach, there is a minimal impact on design trimming with a uniform coverage across the IC. For the design of 65 nm technology with an area of 9 mm2, the maximum J. Low Power Electron. Appl. 2021,slack11, 2 degradation value was improved from −101 psec (for the case of using only the30 of 44 foundry insertion utility) to −19 psec with the hybrid approach.

FigureFigure 23. Timing-driven 23. Timing-driven metal metal fill. The fill. flow The flowdiagram diagram includes includes a second a second step of step dummy of dummy insertion insertion usingusing the foundry the foundry utility utility fill. Based fill. Based on data on datafrom from [39]. [39]. 10.6. More Advance Fill Methods—Cell Fill The cell-based fill method was introduced by CSR and Mentor Graphics for 28 nm technology and below [44]. The cell uses several layers to handle multilevel density rules. For the FEOL, the cell consists of AA and poly to support the coverage needs around MOSFETs. For the BEOL, the cell includes all metals and vias in the design to generate a fine metal grid with vias in between metal lines, which also supports the via coverage rules listed at the manufacture DRM. The cell fill can be followed with other rule-based or model-based fill shapes that have the advantage of higher fill insertion (vs. the cell fill). Figure 24 shows examples of cell fill for the FEOL and BEOL. To support DAA and DGC density DRs, the cell is like a typical MOSFET but without any contacts, to eliminate conflicts with M1. All DGC lines have a fixed width and a fixed pitch, as required by the regularity DRs. The placement of two cells is without any space in between. For the BEOL, two options are shown with the same metal layers and vias in between. The first option has higher metal coverage. However, the second option, as the metals at adjacent cells are not touching each other, has the ability to “shift” cells in case a cell is placed near a signal or a clock line. J. Low Power Electron. Appl. 2021, 11, 2 31 of 44 J. Low Power Electron. Appl. 2021, 11, x FOR PEER REVIEW 33 of 46

Figure 24.24. CellCell fill.fill. ((aa)) AnAn exampleexample for for a a FEOL FEOL cell cell that that looks looks like like a typicala typical regular regular MOSFET. MOSFET. The The layers layers seen seen are dummyare dummy AA (DAA)AA (DAA) and and dummy dummy poly poly (DGC), (DGC), (b) ( firstb) first example example of aof BEOL a BEOL cell cell consists consists of of a a metal metal grid grid without without any any space space inin betweenbetween inserted cells, and (c) the second option of a BEOL cell. Based on data from [44]. inserted cells, and (c) the second option of a BEOL cell. Based on data from [44]. 10.7. Capacitive Coupling of Dummies 10.7. Capacitive Coupling of Dummies The capacitance of a signal line located in between two dummies and over a single The capacitance of a signal line located in between two dummies and over a single ground plane can be calculated as a function of DM.D.1. The calculation can use textbook ground plane can be calculated as a function of DM.D.1. The calculation can use textbook equations (e.g., [45]). Based on such a dependency, we can define a simple rule-of-thumb equations (e.g., [45]). Based on such a dependency, we can define a simple rule-of-thumb for DM.D.1: >~25 × M.S.1 (minimum metal–metal space). In fact, the exact value can be set for DM.D.1: >~25 × M.S.1 (minimum metal–metal space). In fact, the exact value can be based on the dummy length and the parallel length with the signal line (a large dummy set based on the dummy length and the parallel length with the signal line (a large dummy size should have a larger space compared with a small dummy). size should have a larger space compared with a small dummy). The team team from from Renesas Renesas [46] [46 ]analyzed analyzed the the impact impact of ofthe the dummy dummy fill fillon onparasitic parasitic ca- capacitancepacitance by by employing employing a 3D a 3D field field solver, solver, with with intermediate intermediate layer layer parameters parameters based based on on90 90nm nm technology. technology. Their Their first first example example (Figure (Figure 25a) 25a) was was a asignal signal line line located located at Mi, having unrelated routing layers layers at at Mi Mi −− 2 2and and Mi Mi + 2. + 2.Dummy Dummy metals metals were were located located on onMi Mi− 1,− Mi,1, Mi,and andMi + Mi 1. The + 1. capacitance The capacitance of the of signal the signal line with line withdummy dummy fill increased fill increased by 15–35% by 15–35% for a fordummy a dummy density density of 20–70%. of 20–70%. Note that Note no that dummy no dummy neighbors neighbors were located were located around around the metal the metalsignal signalat the atsame the samemetalmetal level. level.Therefore, Therefore, the increase the increase in the in capacitance the capacitance was wasfrom from the thedummies dummies above above and and below below (see (see rule rule DM.D.2). DM.D.2). Their Their next next example example was was for for the coupling capacitance with with a a dummy dummy fill fill between between signal signal lines lines (Figure (Figure 25b). 25b). When When the thedistance distance be- betweentween the the signal signal line line and and the thedummy dummy metal metal (DM.D.1) (DM.D.1) was was≈Wmin,≈Wmin, the capacitance the capacitance of the ofmiddle the middle signal line signal went line up went by around up by 60%, around and 60%,for DM.D.1 and for = 10DM.D.1 × Wmin, = 10 the× capacitanceWmin, the capacitancewent up by wentonly up20%. by This only demonstrates 20%. This demonstrates the “insertion the “insertionpriority,” priority,”that is, a thatlarge is, DM.D.1 a large DM.D.1is more important is more important than DM.D.2. thanDM.D.2.

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Figure 25. The effecteffect ofof dummydummy ﬁlling filling around around a a signal signal line line (one (one layer layer above, above, same same layer, layer, and and one one layer layer below) below) on capacitance. on capaci- (tance.a) Side (a view) Side [ 46view]; (b [46];) a recommended (b) a recommended dummy dummy ﬁll for a fill signal for a line, signal in whichline, in dummy which dummy from the fr signalom the line signal (DM.D.1) line (DM.D.1) is higher priorityis higher (>10 priority× M.W.1), (>10 × butM.W.1), DM.D.2 but >DM.D.2 0 is recommended. > 0 is recommended.

Kahng et al. [41] [41] also studied the impact of various floatingfloating fillfill configurationconfiguration parame-param- etersters on on coupling coupling capacitance capacitance such such as fillas size,fill size fill, location, fill location, distance distance from interconnectfrom interconnect edges, edges,and multiple and multiple fill columns fill columns and rows. and Using rows. this Using information, this information, we can list we a setcan of list guidelines a set of guidelinesas follows: as follows: Guideline 1—tile location: For lineslines AA andand B B (Figure (Figure 26 26a),a), the the coupling coupling capacitance capacitance is isonly only affected affected by dummiesby dummies located located at the atarea the definedarea defined by the by (metal the (metal space) ×space)(parallel × (parallel length +length 2 × metal + 2 × space).metal space). It is best It notis best to place not to dummies place dummies between between the two linesthe two and lines far from and thefar fromparallel the length parallel area. length Insertion area. Insertion close to but close outside to but the outside parallel the length parallel is possible. length is However,possible. However,the area defined the area by defined the parallel by the length parallel will le yieldngth will the highestyield the coupling highest capacitance.coupling capaci- The tance.relative The change relative in capacitance change in capacitance for the five locationsfor the five shown locations in Figure shown 26 bin is Figure×100 for26b location is ×100 for#2 (comparedlocation #2 with (compared location with #1)and location×380, #1)×414, and and ×380,× 376×414, for and locations ×376 for 3–5, locations respectively. 3–5, respectively.Guideline 2—tile orientation: For a dummy inserted between two lines (Figure 26c), it is betterGuideline to have 2—tile a narrow orientation and long: For tile a located dummy along inserted the lines.between The two worst-case lines (Figure scenario 26c), is itto is have better wide to have and shorta narrow tiles. and long tile located along the lines. The worst-case scenario is to haveGuideline wide and 3—tile short width tiles.: For dummies along the lines (Figure 26d), it is better to haveGuideline several thin 3—tile dummies width than: For one dummies thick dummy. along The the dummylines (Figure width 26d), should it beis better DM.W.1, to haveallowed several by DRs thin with dummies a maximum than one number thick dummy. of dummy The columns. dummy width For the should same tilebe DM.W.1, area and allowedcoverage, by it DRs is better with to a havemaximum a centralized number longof du tilemmy with columns. a minimum For the width. same tile area and coverage,Guideline it is better 4: For to dummies have a centralized perpendicular long tile to the with lines a minimum (Figure 26 width.e), it is better to have one thickGuideline dummy 4: For than dummies several thin perpendicular dummies; minimizeto the lines the (Figure number 26e), of dummiesit is better rows.to have one thickGuideline dummy 5: than Large several width thin wires dummies are more; minimize susceptible the to number increased of capacitancedummies rows. due to fill. ItGuideline is preferred 5: Large to have width thinner wires wires are aroundmore susceptible dummies. to increased capacitance due to fill. It is preferred to have thinner wires around dummies.

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J. Low Power Electron. Appl. 2021, 11, 2 33 of 44

Similar work was done by the team from Synopsys [47] for 32 nm DRs.

FigureFigure 26.26. MetalMetal ﬁllfill insertioninsertion guidelinesguidelines basedbased onon A.A. B.B. KahngKahng etet al.al. [[41]:41]: ((aa)) prioritizationprioritization forfor dummydummy metalmetal placement,placement, ((bb)) locationslocations 11 (best)(best) toto 55 (worse)(worse) forfor dummydummy insertion,insertion, ((cc)) betterbetter havehave narrownarrow andand longlong tilestiles parallelparallel toto thethe lines,lines, ((dd)) betterbetter maximizemaximize thethe numbernumber ofof columns,columns, andand (e(e)) better better have have single single wide wide tile tile perpendicular perpendicular to to the the lines. lines.

10.8.Similar The Effect work of Dummy was done Filling by the on Wire team Resistance from Synopsys and Inductance [47] for 32 nm DRs. Since the dummy fills are floating conductors, the current flow in the dummy is neg- 10.8. The Effect of Dummy Filling on Wire Resistance and Inductance ligible at low frequencies. However, at high frequencies, the eddy current induced in the dummySince fills the becomes dummy significant fills are floating (Figure conductors, 27a) and increases the current the resistance flow in the and dummy magnetic is negligiblecoupling between at low frequencies. the signal wire, However, while atit highdecreases frequencies, the wire the inductance. eddy current The induced team from in theKyoto dummy university fills becomes performed significant a detailed (Figure study 27 [48,49]a) and increasesof this. Figure the resistance 27b shows and an magnetic example couplingof the 3D betweenfield-solver the signalfrequency wire, characteristics while it decreases of a G–S–G the wire (Ground–Signal–Ground) inductance. The team from co- Kyotoplanar university transmission performed line (TL). a detailed For the study TLs [with48,49 ]the of this.dimensions Figure 27 listedb shows in Figure an example 27, the of thedifference 3D field-solver in resistance frequency becomes characteristics larger at high of aer G–S–G frequencies, (Ground–Signal–Ground) at 50 GHz, and the resistance coplanar transmission line (TL). For the TLs with the dimensions listed in Figure 27, the difference increases by around 10% due to the eddy current in the dummy fill. In terms of the inin resistance becomes larger at higher frequencies, at 50 GHz, and the resistance increases ductance, the effect of the dummy fill is relatively small (<4% at 50 GHz). by around 10% due to the eddy current in the dummy fill. In terms of the inductance, the The effect on the ground wires was also evaluated using a near-ground and far-from- effect of the dummy fill is relatively small (<4% at 50 GHz). ground structure with M2 G-S-G wires of 4 µm width and spacing. For this structure, the The effect on the ground wires was also evaluated using a near-ground and far-from- dummy metals were located only outside the GSG. The far-from-ground structure had 20 ground structure with M2 G-S-G wires of 4 µm width and spacing. For this structure, the µm G–S space and dummies in between the wires as well as outside. In all cases, the dummy metals were located only outside the GSG. The far-from-ground structure had dummy tiles were 2 µm × 2 µm, staggered, with a local density of 36% and placed with 20 µm G–S space and dummies in between the wires as well as outside. In all cases, the DM.D.1 = 2.5 µm. The resistance change compared with the case without dummies at 50 dummy tiles were 2 µm × 2 µm, staggered, with a local density of 36% and placed with GHz is shown in Figure 27c. For the near-ground structure, the resistance change began DM.D.1 = 2.5 µm. The resistance change compared with the case without dummies at at >10 GHz and for the far-from-ground structure, it began at >20 GHz. For both cases, the 50 GHz is shown in Figure 27c. For the near-ground structure, the resistance change began atdummies >10 GHz at and M1 for and the M3 far-from-ground have a big impact structure, on the it resistance. began at >20 The GHz. adjacent For both ground cases, wires the dummies(near-ground at M1 structure) and M3 can have shield a big the impact effect on of the the resistance. dummy fills The in adjacent the same ground metal wireslayer. (near-groundHowever, the structure)ground wires can shieldcannot the suppress effect of the the effect dummy from fills the in upper/lower the same metal dummies layer. However,[48]. the ground wires cannot suppress the effect from the upper/lower dummies [48].

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(a) (b)

(c)

Figure 27. The effect of dummies on wire resistance and inductance at a high frequency. (a) Conceptual figure of the current Figure 27. The effect of dummies on wire resistance and inductance at a high frequency. (a) Conceptual figure of the flowcurrent in dummyflow in fills;dummy (b) wirefills; resistance(b) wire resistance and inductance and inductance vs. frequency vs. freque with andncy withoutwith and dummies without neardummies a signal near wire a signal for a far-from-groundwire for a far-from-ground structure; (cstructure;) resistance (c) increasesresistance at increases 50 GHz (relativeat 50 GHz to the(relative case withoutto the case dummies) without for dummies) near-ground for near- and far-from-groundground and far-from-ground structures. Based struct onures. data Based from on [48 data]. from [48].

The effecteffect ofof dummy dummy size size and and distance distance of of a dummya dummy from from the the signal signal line (DM.D.1)line (DM.D.1) was alsowas analyzedalso analyzed [49]. [49]. Figure Figu 28rea shows28a shows the far-from-ground the far-from-ground structure structure that wasthat usedwas withused differentwith different sizes ofsizes dummy of dummy tiles and tiles with and DM.D.1 with DM.D.1 of 1 and of 31µ andm. As3 µm. the dummyAs the dummy fill size be-fill camesize became larger and larger distance and distance from the from line decreasedthe line decreased (smaller DM.D.1),(smaller DM.D.1), the resistance the resistance increased (seeincreased Figure (see 28b). Figure Using 28b). these Using data, these we extracted data, we aextracted related DRa related to be usedDR to by be the used insertion by the ≤ utility—forinsertion utility—for high-speed high-speed applications, applications, assuming assuming∆R% 3% ∆R% as a ≤ success 3% as a criterion, success criterion, DM.W.1 ≥ µ × µ µ ≥ µ × µ µ shouldDM.W.1 be should0.8 bem ≥0.80.8 µmm × for0.8 DM.D.1µm for DM.D.1 = 1 m or= 1 µm2 mor ≥22 µmm × for 2 µm DM.D.1 for DM.D.1 = 3 m. = 3 µm. The multilevel effect of the dummies checked by the structures can be seen in Figure 28c. The far-from-ground structure also included DM1 and DM2 dummies below and above, The multilevel effect of the dummies checked by the structures can be seen in Figure respectively, with the shown dimensions. A signal line thickness of 1 µm is typical for 28c. The far-from-ground structure also included DM1 and DM2 dummies below and semi-global lines at 65 nm technologies and below. Due to the magnetic coupling, the eddy above, respectively, with the shown dimensions. A signal line thickness of 1 µm is typical currents flow in the dummy tiles in the upper and lower layers. The increase in resistance for semi-global lines at 65 nm technologies and below. Due to the magnetic coupling, the (Figure 28d) is almost doubled by the dummy fills in the upper and lower layers. Since eddy currents flow in the dummy tiles in the upper and lower layers. The increase in the thickness of the ILD is relatively smaller than DM.D.1, the effect of the dummy fills resistance (Figure 28d) is almost doubled by the dummy fills in the upper and lower lay- is significant [49]. Using these data, we can define a guideline (DR) to be used by the ers. Since the thickness of the ILD is relatively smaller than DM.D.1, the effect of the insertion utility—for high-speed applications, signal lines should not have dummies below dummy fills is significant [49]. Using these data, we can define a guideline (DR) to be used

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by the insertion utility—for high-speed applications, signal lines should not have dum- miesand abovebelow them.and above In addition, them. In DM.D.2addition, should DM.D.2 be should set to atbe least set to 15 at times least more15 times than more the thanILD thickness.the ILD thickness.

Figure 28. TheThe effect effect of of dummy dummy size size and and distance distance of the the du dummymmy from the signal line (DM.D.1) at 50 GHz. ( (aa)) Cross-section Cross-section and dimensions of the far far-from-ground-from-ground structure; ((bb)) resistanceresistance changechange vs.vs. thethe dummydummy widthwidth × lengthlength at at different different DM.D.1; DM.D.1; and ( (cc)) cross-section cross-section and and dimensions dimensions for for the the multilevel multilevel structure; structure; (d) (resistanced) resistance change change vs. DM.D.1 vs. DM.D.1 with and with without and without dummies below and above the signal line. Based on data from [49]. dummies below and above the signal line. Based on data from [49].

10.9. The Effect of Dummy Filling on Inductors 10.9. The Effect of Dummy Filling on Inductors For passive devices in RF circuits, the quality factor (Q-factor) parameter is defined For passive devices in RF circuits, the quality factor (Q-factor) parameter is defined as the ratio between the energy stored to the energy dissipated per cycle. The higher the as the ratio between the energy stored to the energy dissipated per cycle. The higher the Q-factor, the lower the loss of a passive device. To maximize the Q-factor, the inductor is Q-factor, the lower the loss of a passive device. To maximize the Q-factor, the inductor is made using the top metal layer (to minimize capacitance coupling), which should be as made using the top metal layer (to minimize capacitance coupling), which should be as thick as possible to minimize resistance. Based on this, any dummies around and below thick as possible to minimize resistance. Based on this, any dummies around and below thethe inductors inductors will will degrade degrade the the Q-factor. Q-factor. TheThe team team from from Tower Tower calculated calculated Q-factor Q-factor degradation degradation due due to inductor to inductor thickness thickness reduction.reduction. The The results results were were for for a asymmetrical symmetrical inductor inductor made made using using 3.3 3.3 µmµm Cu Cu metal. An exampleexample for thicknessthickness reductionreduction in in this this layer layer due du toe dishingto dishing is seen is seen in Figure in Figure4c. At 4c. 2.7 At GHz, 2.7 GHz,every every 1% reduction 1% reduction in thickness in thickness represented represented about a 0.33%about degradationa 0.33% degradation of the Q-factor of the [ 50Q-]. factorDummies [50]. located near or below the spiral inductor increase the capacitance and reduce the self-resonantDummies located frequency. near Inor addition,below the for spiral high inductor frequencies increase (>10 Ghz, the capacitance see Figure 27 andb), there- duceeddy the current self-resonant in the dummy frequency. fill becomes In addition significant., for high The frequencies eddy current (>10 Ghz, (see Figuresee Figure 27a) 27b),increases the eddy the losscurrent and in the the magnetic dummy fill coupling becomes between significant. the signalThe eddy current current and (see decreases Figure 27a)the wireincreases inductance the loss [51 ].and A typicalthe magnetic spiral inductorcoupling is between seen in Figure the signal 29a. Dummiescurrent and can de- be creasesplaced outsidethe wire the inductance inductor and[51]. possiblyA typical also spiral at the inductor center, is but seen in bothin Figure cases 29a. should Dummies not be

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can be placed outside the inductor and possibly also at the center, but in both cases should not be overlapped with the inductor marking layer ring. DM.D.4 is the enclosure of the marking layer around the inductor. The team from STMicroelectronics [52,53] reported results of a systematic work that checked the effects of dummies located at the center and below Cu inductors. The process included six Cu layers and the inductor was located at M6, stacked with the Al layer above, which was used for bonding. M3–M6 square dummies with a fixed width of 0.46 µm and a density of 25–80% were inserted at the center of the spiral, keeping a DM.D.41 of from 1 to 10 µm. Figure 29b shows the results. For a low density (25%), DM.D.41 had a limited effect on Qmax degradation. However, if an aggressive design rule was used (80% density, DM.D.41 = 1 µm), the effect on the Q-factor was drastic, with a 30% degradation in Qmax, due to the increase in the parasitic capacitance. At any density, high DM.D.41 led to less degradation, and in many cases, it was set to 30 µm or more. Analysis showed that the configuration of the dummies—stacked or crossed—had little real effect. Having dummies only below the inductor (M3 and M4 only) did not yield a significant improvement in Qmax. A later work from STMicroelectronics [53] analyzed the Qmax degradation considering dummies located both at the inside area (set by DM.D.41) and outside area (DM.D.42) of the inductor, with similar density. Qmax degradation was almost doubled with a similar sensitivity to the distance of dummies inside and outside. Based on that, we recommend a single value for DM.D.4. The stacked configuration of the dummies under the inductor (aligned or crossed) was found to be a negligible factor on the Qmax. The orientation of the tiles at the inductor’s center is not an important factor; this was experimentally verified by the team from Philips [54]. To maximize the Q-factor, the dummy size should be kept small (<3 µm × 3 µm). Using 10 µm × 10 µm dummies degraded the Q-factor by around 10% compared to the case of 3 µm × 3 µm dummies [55]. J. Low Power Electron. Appl. 2021, 11, 2 Smaller dummies mean smaller magnetic coupling with limited flow of eddy currents36 of and 44 limited Q-factor degradation. Recently, the common team of GLOBALFOUNDRYS and Mentor Graphics reported [56] on orientation-aware dummy fill that was mostly made to enhance inductor performance at the 14 nm platform by a symmetrical filling. All of these overlapped with the inductor marking layer ring. DM.D.4 is the enclosure of the marking data have been used to set dummy rules related to inductors. layer around the inductor.

(a) (b)

FigureFigure 29. 29.The The effect effect of of metal metal dummies dummies on on inductors. inductors. (a )(a A) A typical typical 1.5 1.5 turn turn square square inductor; inductor; the the inductor inductor marking marking layer layer (ring)(ring) deﬁnes defines the the area area that that dummy dummy metal metal (DM) (DM) should should not not be be placed placed on; on; (b )(b Qmax) Qmax vs. vs. DM.D.4 DM.D.4 at at different different densities densities of of dummiesdummies located located at at the the center, center, in M3–M6,in M3–M6, based based on on STM’s STM’s work work [52 [52].].

10.10.The RTA-Aware team from Dummy STMicroelectronics Fill Insertion [ 52,53] reported results of a systematic work that checked the effects of dummies located at the center and below Cu inductors. The process Rapid thermal annealing (RTA) is widely used during FEOL manufacturing to re- included six Cu layers and the inductor was located at M6, stacked with the Al layer above, duce the overall thermal budget and ensure that there are shallow junctions with high which was used for bonding. M3–M6 square dummies with a ﬁxed width of 0.46 µm and a density of 25–80% were inserted at the center of the spiral, keeping a DM.D.41 of from 1 to 10 µm. Figure 29b shows the results. For a low density (25%), DM.D.41 had a limited effect

on Qmax degradation. However, if an aggressive design rule was used (80% density, DM.D.41 = 1 µm), the effect on the Q-factor was drastic, with a 30% degradation in Qmax, due to the increase in the parasitic capacitance. At any density, high DM.D.41 led to less degradation, and in many cases, it was set to 30 µm or more. Analysis showed that the configuration of the dummies—stacked or crossed—had little real effect. Having dummies only below the inductor (M3 and M4 only) did not yield a significant improvement in Qmax. A later work from STMicroelectronics [53] analyzed the Qmax degradation considering dummies located both at the inside area (set by DM.D.41) and outside area (DM.D.42) of the inductor, with similar density. Qmax degradation was almost doubled with a similar sensitivity to the distance of dummies inside and outside. Based on that, we recommend a single value for DM.D.4. The stacked configuration of the dummies under the inductor (aligned or crossed) was found to be a negligible factor on the Qmax. The orientation of the tiles at the inductor’s center is not an important factor; this was experimentally verified by the team from Philips [54]. To maximize the Q-factor, the dummy size should be kept small (<3 µm × 3 µm). Using 10 µm × 10 µm dummies degraded the Q-factor by around 10% compared to the case of 3 µm × 3 µm dummies [55]. Smaller dummies mean smaller magnetic coupling with limited flow of eddy currents and limited Q-factor degradation. Recently, the common team of GLOBALFOUNDRYS and Mentor Graphics reported [56] on orientation-aware dummy fill that was mostly made to enhance inductor performance at the 14 nm platform by a symmetrical filling. All of these data have been used to set dummy rules related to inductors.

10.10. RTA-Aware Dummy Fill Insertion Rapid thermal annealing (RTA) is widely used during FEOL manufacturing to reduce the overall thermal budget and ensure that there are shallow junctions with high activation. The high temperature annealing time has gradually reduced from seconds, using halogen lamps, to milliseconds by ﬂash lamp anneals (FLA). The ﬁrst reported work on inter-die J. Low Power Electron. Appl. 2021, 11, 2 37 of 44

variation of CMOS inverter delay correlated the millimeter scale variation in the device reflectivity with the pattern density [57]. In that study, a shift of >15% was observed in the sheet resistance of an unsalicided polyline located over the STI at different coverages. The larger the STI exposed area around the poly resistor, the higher the effective temperature that improved the dopant activation and reduced the sheet resistance. Additionally, the faster the temperature ramp rates, the higher the variation was, due to the higher dependency on the thermal diffusion distance at the wafer surface, as explained below. The mechanism for RTA involved heating the top-side of the wafer surface by exposure to an array of lamps that was pulsed rapidly to transfer radiative heat to the wafer surface [58]. However, during this time, the entire silicon substrate does not reach thermal equilibrium due to the extremely short heating period. The surface emissivity of various material stacks determines the amount of absorption energy and the final annealing temperature. As a result, different layout pattern densities lead to different annealing temperatures and device characteristics. The length scale of such variations is determined√ by the thermal diffusion distance in the wafer surface, which is proportional to Dt, where D is the thermal conductivity of silicon and t is the annealing time. In millisecond RTA processing times, the typical length is around hundreds of microns. This is one of the parameters used to define a window size for analysis, as will be explained later. As an example, researchers from IBM [59] analyzed a realistic layout of a 45 nm test chip. Due to the layout style, various components exhibited a pronounced difference in pattern density. By the thermal simulation tool, the fluctuation in the annealing temperature which directly induced threshold voltage variation by more than 30 mV could be seen. The largest difference was observed close to the boundary of different components, where the non-uniformity of the circuit layout reaches the maximum. The team from TSMC [60] checked how to optimize the emissivity uniformity for the FLA process by DAA filling. The emissivity for the STI, AA (N+ or P+), Poly over STI, and Poly over Gate oxide are 0.80, 0.43, 0.46, and 0.55, respectively. To minimize the temperature variation, the “equivalent emissivity,” which takes into consideration the emissivity and the area of each location, is calculated as

n Equivalent emissivity = ∑ εi·(Ai/Awindow), i=1

where n is the four locations described above and εi and Ai are the emissivity and the area, respectively. To identify the appropriate window area (Awidnow), the team from IBM [59] simulated a sample 45 nm design with various sizes of simulation window. The exact value depends on the RTA conditions, such as the annealing time and temperature. For the purposes of DR definition and dummy fill insertion, a typical window of 30 µm × 30 µm is reasonable. For an “open area,” without any design data and before the dummy fill, the equivalent emissivity will be exactly 0.8, as the entire area is covered with STI only. After the fill with DAA (45%, for this example) and DGC located over STI (25%, for this example), the equivalent emissivity will drop to about 0.55. To minimize RTA variability, this number can be used as the emissivity equivalent “target” for windows in the design data. In Table4 and Figure 30, we provide our example for the dummy fill insertion with consideration given to minimizing RTA variation. The original design had four MOSFETs organized in two rows. Each transistor included three fingers and a DGC at each side, to satisfy the regularity requirements. Different types of DAA were inserted together with DGC, which increased the coverage and reduced the equivalent emissivity. The optimal fill was achieved with a combination of a cell fill with a pattern of a MOSFET together with DAA rings, and a DGC placed on the STI at the center. The overfill of DAA or DGC would provide lower equivalent emissivity. However, this might violate the maximal coverage limits, as seen in Figure 29b, where the poly coverage is close or above GC.C.2. Therefore, the insertion utility needs to use the equivalent emissivity calculation described, as an additional boundary condition to the coverage limits. J. Low Power Electron. Appl. 2021, 11, x FOR PEER REVIEW 40 of 46

the insertion utility needs to use the equivalent emissivity calculation described, as an J. Low Power Electron. Appl. 2021 11 , , 2additional boundary condition to the coverage limits. 38 of 44

Table 4. Optimization of DAA and dummy poly (DGC) insertion with equivalent emissivity. See Figure 30. Table 4. Optimization of DAA and dummy poly (DGC) insertion with equivalent emissivity. See Figure 30. AA Poly Figure Dummy Insertion-Description Equivalent Emissivity Figure Dummy Insertion-DescriptionCoverage AA Coverage Coverage Poly Coverage Equivalent Emissivity FigureFigure 30a 30 a Without Without dummy dummy fill ﬁll 23% 23% 21% 21% 0.697 0.697

N/AN/A Small Small DAA DAA ring ring around around square square DGC DGC 36% 36% 22% 22% 0.642 0.642 N/A Large DAA ring around square DGC 38% 26% 0.623 N/A Large DAA ring around square DGC 38% 26% 0.623 N/A DAA ring around rectangular DGC 42% 26% 0.611 N/A DAA ring around rectangular DGC 42% 26% 0.611 Figure 30b MOSEFT Cell ﬁll 36% 40% 0.607 Figure 30b MOSEFT Cell fill 36% 40% 0.607 MOSEFT Cell ﬁll + large DAA ring Figure 30c 48% 28% 0.587 MOSEFT Cellaround fill + large square DAA DGC ring around Figure 30c 48% 28% 0.587 square DGC

Figure 30. Example of different dummy fillfill insertionsinsertions forfor DAADAA andand DGC,DGC, consideringconsidering bothboth AAAA and Polyand Poly coverage, coverage, regularity regularity and rapidand rapid thermal thermal annealing annealing (RTA) (RTA) variation. variation. (a) Original (a) Original design, design, with AA andwith polyAA and (GC) poly only; (GC) (b) afteronly; the(b) dummyafter the filldummy cells, withfill cells, a MOSFET with a MOSFET pattern; ( pattern;c) after the (c) dummyafter the fill dummy fill consisting of DAA rings around a DGC and MOSFET pattern. See Table 4 for these consisting of DAA rings around a DGC and MOSFET pattern. See Table4 for these results. results. 10.11. Dummy Fill Considerations for Design Fix (ECO Fill) 10.11.Due Dummy to the Fill complexity Consideration of thes for dummy Design insertion Fix (ECO for Fill) advanced technologies, any demand (or “order”)Due to forthe engineeringcomplexity changeof the dummy (ECO) that insertion arrives for after advanced the design technologies, has already any passed de- themand dummy (or “order”) fill insertion for engineering step will change lead to (ECO) a significant that arrives delay after to tape-out. the design To has overcome already this,passed the the team dummy from fill TSMC insertion [61] developed step will lead an automatedto a significant design delay flow to fortape-out. the 16 To nm over- and belowcome this, platforms. the team The from inputs TSMC are the[61] original developed design an andautomated modified design (ECO) flow design for databases,the 16 nm and thebelow original platforms. dummy The file inputs database. are the The original workflow design uses and the modified knowledge (ECO) of the design process da- layer/datatypetabases, and the mappingoriginal dummy and DRC file spacing database. as The an input workflow into theuses ECO the knowledge fill utility. Asof the an example,process layer/datatype we assume that mapping three bus and lines DRC located spacing at M4as an need input to changeinto the placeECO infill the utility. design. As Inan aexample, very general we assume way, the that two three main bus tasks lines of thelocated ECO at fill M4 utility need are to to change fill the place empty in area the withdesign. dummies In a very where general the way, bus the lines two were main located tasks andof the to ECO remove fill utility existing are dummies to fill the empty so the busarea linewith can dummies be replaced. where the bus lines were located and to remove existing dummies so the bus line can be replaced. 11. Metal Slits Rules One of the ways to reduce copper coverage is to include metal slots (Table5, Figure 31). For simplicity, a dedicated support layer is used to define the slot, e.g., layer M (slotting). During mask data preparation at the wafer manufacturer, and before OPC, the metal is J. Low Power Electron. Appl. 2021, 11, x FOR PEER REVIEW 41 of 46

11. Metal Slits Rules One of the ways to reduce copper coverage is to include metal slots (Table 5, Figure 31). For simplicity, a dedicated support layer is used to define the slot, e.g., layer M (slot- J. Low Power Electron. Appl. 2021, 11, 2ting). During mask data preparation at the wafer manufacturer, and before OPC, the 39metal of 44 is “punched” by a simple Boolean operator. The slits are needed only for wide and long lines. A typical definition for a “wide” copper line is >10 µm width.

“punched” byTable a simple 5. Metal Boolean slits (for operator. copper) Therules. slits are needed only for wide and long lines. A typical deﬁnition for a “wide” copper line is >10 µm width. # Rule Rule Description Rule Related to: Table 5. Metal slits (for copper) rules. 1 MSLOT.W.1 Minimum width of slot Photo and etch resolution. Typical guideline is: >5 × M.W.1 # Rule Rule Description Rule Related to: Minimum space between 2 MSLOT.S.1 Photo and etch to define a narrow Cu line. Typical guideline is: >5 × M.S.1 1 MSLOT.W.1slots Minimum width of slot Photo and etch resolution. Typical guideline is: >5 × M.W.1 Photo and etch to deﬁne a narrow Cu line. Typical guideline 3 2 MSLOT.A.1 MSLOT.S.1 Minimum Minimum area of slot space between slots To eliminate any dielectric erosion is: >5 × M.S.1 Distance to CS or Via To eliminate high resistance in case of misalignment, so the CS or the Via will 4 3MSLOT.D.1 MSLOT.A.1 Minimum area of slot To eliminate any dielectric erosion interact the metal line be partially covered by the slot (that is a dielectric). To eliminate high resistance in case of misalignment, so the Distance to CS or Via interact the 4 MSLOT.D.1Distance from a metal CS or the Via will be partially covered by the slot (that is metal line corner or intersection a dielectric). 5 MSLOT.D.2 To eliminate high resistance due to current crowding. areas.Distance See also from a metal corner or 5 MSLOT.D.2 MSLOT.N.2intersection areas. To eliminate high resistance due to current crowding. See also MSLOT.N.2 Eliminate slotting into Eliminate any resistance degradation of signal lines or inductors due to 6 MSLOT.N.1 Eliminate slotting into signal lines Eliminate any resistance degradation of signal lines or 6 MSLOT.N.1signal lines or inductors slotting. or inductors inductors due to slotting. Eliminate slotting at 7 7MSLOT.N.2 MSLOT.N.2 Eliminate slotting at intersectionTo areaseliminate To resistance eliminate degrad resistanceation degradation due to current due tocrowding current crowding intersection areas

Figure 31. IllustrationIllustration of of metal metal slits slits (for (for copper) copper) rules. rules.

TheThe impact of slotting onon resistanceresistance can can be be simulated simulated using using 2D 2D field field solver solver to to calculate calcu- latethe currentthe current distribution. distribution. Arora Arora [62] showed[62] show theed impact the impact of slots of on slots wire on resistance—a wire resistance—a simple simplecalculation calculation showed showed that the that increase the increase in resistance in resistance is proportional is proportional to the to area the ofarea the of slots. the slots.However, However, at high at operating high operating frequencies, frequencie the resistances, the resistance degradation degradation was enhanced was enhanced due to a dueskin to effect. a skin This effect. is the This reason is the for settingreason rulefor setting MSLOT.N.1 rule toMSLOT.N.1 eliminate slottingto eliminate signal slotting lines or signalinductors. lines Figureor inductors. 32 shows Figure our electromagnetic32 shows our electromagnetic simulation of differentsimulation slit of configurations different slit and the resistance change [63]. Using this example, and assuming all slits are placed parallel to the current flow, we can set additional guidelines for the insertion of slits:

J. Low Power Electron. Appl. 2021, 11, x FOR PEER REVIEW 42 of 46

configurations and the resistance change [63]. Using this example, and assuming all slits are placed parallel to the current flow, we can set additional guidelines for the insertion of slits: Guideline 1: For the same overall slit area, it is better to have as many (per rule MSLOT.W.1) narrow and long slits as possible. Figure 32(a.1–a.3) shows a resistance reduction from 17.6% to 16.1% to 15.2%, respectively. Narrow slits mean there will be lower current crowding, as shown in Figure 32b. Guideline 2: For the same overall slit area, it is better to have staggered placement of slits. Comparing Figure 32(a.3,a.4,b.1,b.2) shows that there was a relative resistance reduction in around 7% due to this configuration. Guideline 3: Eliminate having OPC to the slits, for having rounded slits corners. The increase in current density is the highest at the slits’ corners, so rounded corners would mean lower resistance. This guideline is easy to implement, as the slits are drawn using a dedicated support layer. Guideline 4: Eliminate having slits that restrict the path of the current flow. Slits should be placed parallel to the direction of the current. Figure 32(c.1,c.2) compare the current density for two configurations: having two slits in a row having current crowding at the slits corner (marked with arrow) and staggered slits configuration. The figure also J. Low Power Electron. Appl. 2021, 11, 2shows the resistance reduction for the second case. This is the reason for rule MSLOT.N.2,40 of 44 which eliminates slotting at intersection areas. In many cases when using the slits insertion utility, the slit should be set to be a simple square to eliminate current blocking.

Figure 32. The effect of metal slit length, width, and placement on resistance increase vs. a wire without any slits. ( a.1–a.4)) wires withwith W/LW/L = = 27/28 27/28 µm,µm, having having area area reduction reduction of of around around 11% 11% after after slits slits insertion insertion with with 2, 2, 3, 3, or or 4 4 rows rows of slits; ( b.1,,b.2) a similar coverage reduction can be seen withwith differentdifferent slitslit placements.placements. (c.1,,c.2c.2)) electromagneticelectromagnetic simulationsimulation showing the current density for two slits in a row (c.1) and staggered (c.2). Data from [63]. current density for two slits in a row (c.1) and staggered (c.2). Data from [63].

Guideline 1: For the same overall slit area, it is better to have as many (per rule MSLOT.W.1) narrow and long slits as possible. Figure 32(a.1–a.3) shows a resistance reduction from 17.6% to 16.1% to 15.2%, respectively. Narrow slits mean there will be lower current crowding, as shown in Figure 32b. Guideline 2: For the same overall slit area, it is better to have staggered placement of slits. Comparing Figure 32(a.3,a.4,b.1,b.2) shows that there was a relative resistance reduction in around 7% due to this configuration. Guideline 3: Eliminate having OPC to the slits, for having rounded slits corners. The increase in current density is the highest at the slits’ corners, so rounded corners would mean lower resistance. This guideline is easy to implement, as the slits are drawn using a dedicated support layer. Guideline 4: Eliminate having slits that restrict the path of the current flow. Slits should be placed parallel to the direction of the current. Figure 32(c.1,c.2) compare the current density for two configurations: having two slits in a row having current crowding at the slits corner (marked with arrow) and staggered slits configuration. The figure also shows the resistance reduction for the second case. This is the reason for rule MSLOT.N.2, which eliminates slotting at intersection areas. In many cases when using the slits insertion utility, the slit should be set to be a simple square to eliminate current blocking. The effect of the slotting configuration on inductors’ RF performance was also studied by Blaschke [50], who used detailed momentum simulations to analyze a range of configurations of metal slots for resistance and Q-factor dependency. As the Q-factor is directly proportional to the inductor resistance, a large slot area means high resistance and Q-factor degradation. It was found that the optimal configuration is to have one long J. Low Power Electron. Appl. 2021, 11, 2 41 of 44

slot located along the axes of the line. Breaking the single slot into several long or short lines, or staggered squares, degraded the Q-factor. For example, including a single slot of 1–3 µm width increased the line resistance by about 9% and degraded the Q-factor by about 9% (both compared to the case without a slot). However, using a staggered, square slot, increased the resistance by 9% but degraded the Q-factor by >14%. The length of the single slot is dependent on the wavelength, and a typical length should be <150 µm. The effect of metal slits on the EM performance was described in detail in [22]. For stress-induced voids reliability performances, the team from ONSEMI showed that the insertion of metal slots close to electrically active vias can act as a diffusive barrier and improved the via lifetime [64].

12. Summary and Future Directions The continuous scaling needed for higher density and better performance has introduced new coverage challenges reviewed in this paper. The global coverage rules have been replaced by local rules. In parallel, a new set of rules for dummy insertion were developed by IC manufacturers. Advanced ﬁll insertion utilities are now considered in addition to coverage needs, along with thermal effects, sensitive signal line, and critical analog and RF devices like inductors and double patterning processes, among others. To minimize proximity effects, the simple “tile” was replaced with a “cell” consisting of several layers. It is reasonable to assume that future technologies will require tighter coverage limits and be multilayer based, as measured by smaller windows (of less than 10 µm × 10 µm). The inserted cells will be highly regular and have a carefully optimized layout for uniform coverage. Finally, new thermal rules will require a uniform layout with a tight equivalent emissivity range.

Author Contributions: Conceptualization, E.N.S. and S.R.; methodology, E.N.S.; validation, E.N.S. and S.R.; formal analysis, E.N.S.; investigation, E.N.S.; writing—original draft preparation, E.N.S. and S.R.; writing—review and editing, E.N.S. and S.R. All authors have read and agreed to the published version of the manuscript. Funding: This research received no external funding. Acknowledgments: The author wishes to thank Eng. I. Rotstein, V. Blaschke, and Y. Takayuki for their endless fruitful stimulating discussions. The valuable technical support and the detailed explanations of Uri Krispil from Mentor Graphics, Israel, were very much appreciated. Special thanks to Daniel Shauly for the linguistic review of this paper. Conﬂicts of Interest: The authors declare no conﬂict of interest.

References 1. Appels, J.; Kooi, E.; Paffen, M.M.; Schatorje, J.J.H.; Verkuylen, W.H.C.G. Local oxidation of silicon and its application in semiconductor-device technology. Philips Res. Rep. 1970, 25, 118. 2. Mistry, K.; Allen, C.; Auth, C.; Beattie, B.; Bergstrom, D.; Bost, M.; Brazier, M.; Buehler, M.; Cappellani, R.A.; Chau, C.-H.; et al. 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging. In Proceedings of the 2007 IEEE International Electron Devices Meeting, Washington, DC, USA, 10–12 December 2007. 3. Hsieh, Y.H.; Hsu, H.K.; Huang, R.P.; Chen, C.H.; Tsai, T.C.; Lin, W.; Yang, C.L.; Wu, J.Y. Process Development of High-k Metal Gate Aluminium CMP at 28nm Technology Node. Microelectron. Eng. 2010, 92, 19–23. 4. Lee, H.-H.; Wilson, J. Calibre YieldEnhancer Analysis-based. In Proceedings of the 54th ACM/IEEE Design Automation Conference, San Francisco, CA, USA, 19–23 June 2017. 5. Oliver, M.R. Chemical-Mechanical Planarization of Semiconductor Materials; Springer: Berlin/Heidelberg, Germany, 2003. 6. Cook, L.M. Chemical processes in glass polishing. J. Noncryst. Solids 1990, 120, 152–171. [CrossRef] 7. Luo, J.; Dornfeld, D. Integrated Modeling of Chemical Mechanical Planarization for Sub-Micron IC Fabrication; Springer: Berlin/Heidelberg, Germany, 2004. 8. Zentye, P.B.; Kumar, A.; Sikder, A.K. Chemical mechanical planarization for microelectronics applications. Mater. Sci. Eng. R Rep. 2004, 45, 89–220. [CrossRef] 9. Joseph, M.; Shyam, P.S.; Ronald, J.M. Gutmann. Chemical Mechanical Planarization of Microelectronic Materials; WILEY-VCH Verlag GmbH & Co. KGaA: Weinheim, Germany, 1997. J. Low Power Electron. Appl. 2021, 11, 2 42 of 44

10. Runnels, S.R. Feature-scale fluid-based erosion modeling for chemical mechanical polishing. J. Electrochem. Soc. 1994, 141, 1900–1904. [CrossRef] 11. Stine, B.; Ouma, D.; Divecha, R.; Boning, D.; Chung, J. Rapid characterization and modeling of pattern dependent variation in chemical mechanical polishing. IEEE Trans. Semicond. Manuf. 1998, 11, 129–140. [CrossRef] 12. Stine, B.; Ouma, D.; Divecha, R.; Boning, D.; Chung, J. A closed-form analytic model for ILD thickness variation in CMP processes. In Proceedings of the 1997 CMP-MIC Conference, Santa Clara, CA, USA, 25 February 1997; pp. 266–273. 13. Kaufman, F.B.; Thompson, D.B.; Broadie, R.E.; Jaso, M.A.; Guthrie, W.L.; Pearson, D.J.; Small, M.B. Chemical-mechanical polishing for fabricating patterned W metal features as chip interconnects. J. Electrochem. Soc. 1991, 138, 3460–3465. [CrossRef] 14. Katakamsetty, U.; Koli, D.; Yeo, S.; Hui, C.; Ghulghazaryan, R.G.; Aytuna, B.; Wilson, J. 20nm CMP model calibration with optimized metrology data and CMP model applications. In Design-Process-Technology Co-Optimization for Manufacturability IX; Proc. SPIE 9427; International Society for Optics and Photonics: Bellingham, WA, USA, 2015; p. 94270U. 15. Tugbawa, T.E.; Park, T.H.; Boning, D.S. Integrated chip-scale simulation of pattern dependencies in copper electroplating and copper chemical mechanical polishing processes. In Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No.02EX519), Burlingame, CA, USA, 5 June 2002; pp. 167–169. 16. Lakshminarayanan, S.; Wright, P.J.; Pallinti, J. Electrical characterization of the copper CMP process and derivation of metal layout rules. IEEE Trans. Semicond. Manuf. 2003, 16, 668–676. [CrossRef] 17. Charles, C.; Jamil, K. Design for Manufacturability and Yield for Nano-Scale CMOS; Springer: Dordrecht, The Netherlands, 2007. 18. Doong, K.Y.; Lin, K.C.; Tseng, T.C.; Lu, Y.C.; Lin, S.C.; Hung, L.J.; Ho, P.S.; Hsieh, S.; Young, K.L.; Liang, M.S. Electrical characterization of model-based dummy feature insertion in Cu interconnects. In Proceedings of the 2004 International Conference on Microelectronic Test Structures (IEEE Cat. No.04CH37516), Awaji Yumebutai, Japan, 22–25 March 2004; pp. 87–92. 19. Ching, B.C.; Yew, H.C.; Tien, D.K.C. A case study of how pattern density affect metal etch. In Proceedings of the 2008 IEEE International Conference on Semiconductor Electronics, Johor Bahru, Malaysia, 25–27 November 2008; pp. 629–630. 20. Lakshminarayanan, S.; Wright, P.; Pallinti, J. Design rule methodology to improve the manufacturability of the copper CMP process. In Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No.02EX519), Burlingame, CA, USA, 5 June 2002; pp. 99–101. 21. Kahng, A.B.; Robins, G.; Singh, A.; Wang, H.; Zelikovsky, A. Filling and slotting: Analysis and algorithms. ISPD 1998, 95–102. [CrossRef] 22. Shauly, E.N. Physical, Electrical, and Reliability Considerations for Copper BEOL Layout Design Rules. J. Low Power Electron. Appl. 2018, 8, 20. [CrossRef] 23. Gupta, T. Copper Interconnect Technology; Springer: Berlin/Heidelberg, Germany, 2009. 24. Park, T.; Tugbawa, T.; Boning, D.; Hymes, S.; Smekalim, K. Multi-Level Test Mask Documentation for Low K Dielectric and Copper Damascene CMP Process (Mask K854); MIT: Cambridge, MA, USA, 1999. 25. Ban, Y.; Han, S.M.; Choi, E.; Gbondo-Tugbawa, T.; Chen, K.H. Model-based CMP aware RC extraction of interconnects in 16nm designs. In Design-Process-Technology Co-Optimization for Manufacturability X; International Society for Optics and Photonic: Bellingham, WA, USA, 2016; Volume 9781, p. 97810G. 26. Kahng, A.B.; Topaloglu, R.O. DOE-Based Extraction of CMP, Active and Via Fill Impact on Capacitances. IEEE Trans. Semicond. Manuf. 2008, 21, 22–32. [CrossRef] 27. Topaloglu, R.O. Standard Cell and Custom Circuit Optimization using Dummy Diffusion through STI Width Stress Effect Utilization. In Proceedings of the IEEE Custom Integrated Circuit Conferance (CICC), San Jose, CA, USA, 16–19 September 2007; pp. 619–622. 28. Inoue, T.; Tower Panasonic Corporation, Toyama, Japan. Personal communication, 2014. 29. Zilberman, A.; TowerJazz, Migdal, Ha’Emek, Israel. Personal communication, 2010. 30. Hamouda, A.; Salama, M. Efficient model-based dummy-fill OPC correction flow for deep sub-micron technology nodes. In Photomask Technology 2014; International Society for Optics and Photonics: Bellingham, WA, USA, 2014; Volume 9235, p. 92351W. 31. Calibre YiledEnhancer SmartFill. Available online: https://www.mentor.com/products/ic_nanometer_design/design-for- manufacturing/calibre-yieldenhancer/ (accessed on 30 October 2020). 32. Ferguson, J. Inclusion and Verification of Planarization Fills on Low-Density IC Regions, AppNote 0328. Available online: https://support.sw.siemens.com/kbassets/external/MG575410/files/0328.pdf (accessed on 30 October 2020). 33. Ferguson, J.; Suaya, R.; Moore, A. On the Inclusion and Verification of Planarization Fills on Low-Density IC Regions; Mentor Graphics Corp.: Wilsonville, OR, USA, 2001. 34. Tian, R.; Wong, D.F.; Boone, R. Model-based dummy feature placement for oxide chemical-mechanical polishing manufacturability. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 2001, 20, 902–910. [CrossRef] 35. Kahng, A.B.; Robins, G.; Singh, A.; Zelikovsky, A. New and Exact Filling Algorithms for Layout Density Control. In Proceedings of the Twelfth International Conference on VLSI Design, Goa, India, 7–10 January 1999. 36. Song, Y.; Lee, J.; Lee, S.; Shin, Y. Integrated routing and fill for self-aligned double patterning (SADP) using grid-based design. In Design-Process-Technology Co-Optimization for Manufacturability X; International Society for Optics and Photonics: Bellingham, WA, USA, 2016; Volume 9781, p. 978105. J. Low Power Electron. Appl. 2021, 11, 2 43 of 44

37. Chang, L.-F.; Fan, Z.; Lu, D.; Bao, A. Improving Copper CMP Topography by Dummy Fill Co-Optimization Electroplating and CMP Planarization. In Design for Manufacturability through Design-Process Integration IV; International Society for Optics and Photonics: Bellingham, WA, USA, 2010; Volume 7641, p. 76410W. 38. Beckage, T.P.; Brown, R.; Tian, E.; Travis, A.P.; Thomas, C. Implementation of Model-Based Tiling at STI CMP for 90nm Technology. In Proceedings of the CMP-MIC Conference, Tampa, FL, USA, 24–26 February 2004; pp. 157–162. 39. Katakamsetty, U.; Hui, C.; Huang, L.D.; Weng, L.; Wu, P. Timing-aware metal fill for optimized timing impact and uniformity. In Design for Manufacturability through Design-Process Integration III; International Society for Optics and Photonics: Bellingham, WA, USA, 2009; Volume 7275, p. 72751P. 40. Talapatra, S. Calibre Net Aware Metal Fill Flow, Mentor Graphics User2User Meeting, Bangalore. 2015. Available online: https://www.mentor.com/events/user2user (accessed on 30 October 2020). 41. Kahng, A.B.; Samadi, K.; Sharma, P. Study of floating fill impact on interconnect capacitance. In Proceedings of the 7th International Symposium on Quality Electronic Design (ISQED’06), San Jose, CA, USA, 27–29 March 2006; pp. 6–696. 42. Kose, S.; Salman, E.; Friedman, E.G. Shielding Methodologies in the Presence of Power/Ground Noise. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2011, 19, 1458–1468. [CrossRef] 43. Charre, L.; Gravano, B.; Possas, R.; Zheng, C. Timing Aware Dummy Metal Fill Methodology. arXiv 2017, arXiv:1711.01407v2. 44. Thomas, C.; Malek, A.; Smith, I. A Novel Approach to Dummy Fill for Analog Designs Using CALIBRE®SMATRFILLTM. Mentor Graphics White Paper. 2014. Available online: www.mentor.com (accessed on 30 October 2020). 45. Lee, T.H. The Design of CMOS Radio-Frequency Integrated Circuits; Cambridge University Press: Cambridge, UK, 2004. 46. Kurokawa, A.; Kanamoto, T.; Kasebe, A.; Inoue, Y.; Masuda, H. Efficient capacitance extraction method for interconnects with dummy fills. In Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571), Orlando, FL, USA, 6 October 2004; pp. 485–488. 47. Karmarkar, A.P.; Xu, X.; Moroz, V.; Rollins, G.; Lin, X. Analysis of performance and reliability trade-off in dummy pattern design for 32-nm technology. In Proceedings of the 2009 10th International Symposium on Quality Electronic Design, San Jose, CA, USA, 16–18 March 2009; pp. 185–189. 48. Tsuchiya, A.; Onodera, H. Measurement of interconnect loss due to dummy fills. In Proceedings of the 2007 IEEE Workshop on Signal Propagation on Interconnects, Genova, Italy, 13–16 May 2007; pp. 241–244. 49. Tsuchiya, A.; Onodera, H. Effect of Dummy Fills on High-Frequency Characteristics of On-Chip Interconnects. In Proceedings of the 2006 IEEE Workshop on Signal Propagation on Interconnects, Berlin, Germany, 9–12 May 2006; pp. 275–278. 50. Blaschke, T.V.; Newport Beach, CA, USA. Personal communication, 2009. 51. Tsuchiya, A.; Onodera, H. Patterned Floating Dummy Fill for On-Chip Spiral Inductor Considering the Effect of Dummy Fill. IEEE Trans. Microw. Theory Tech. 2008, 56, 3217–3222. [CrossRef] 52. Pastore, C.; Gianesello, F.; Gloria, D.; Serret, E.; Benech, P. Test structure definition for dummy metal filling strategy dedicated to advanced integrated RF inductors. In Proceedings of the 2008 IEEE International Conference on Microelectronic Test Structures, Edinburgh, UK, 24–27 March 2008; pp. 214–219. 53. Pastore, C.; Gianesello, F.; Gloria, D.; Serret, E.; Benech, P. Innovative and Complete Dummy Filling Strategy for RF Inductors Integrated in an Advanced Copper BEOL. In Proceedings of the 2008 European Microwave Integrated Circuit Conference, Amsterdam, The Netherlands, 27–28 October 2008; pp. 40–43. 54. Detcheverry, C.; van Noort, W.; Hoofman, R.; Tiemeijer, L.; Nguyen, V.H.; Verheyden, G.; Bancken, P.; Daamen, R.; Havens, R. The effect of copper design rules on inductor performance. In Proceedings of the ESSDERC’03, 33rd Conference on European Solid-State Device Research, Estoril, Portugal, 16–18 September 2003; pp. 107–110. 55. Tsuchiya, A.; Onodera, H. Effect of Dummy fills on characteristics of passive devices in CMOS millimeter-wave circuits. In Proceedings of the 2009 IEEE 8th International Conference on ASIC, Changsha, China, 20–23 October 2009; pp. 296–299. 56. Kim, D.; de la Garza, E.; Ibrahim, M.E.; Mousa, S.H.; Hogan, M. Improving Analog and RF Fill Generation Using Calibre PERC, YieldEnhancer and Pattern matching. In Proceedings of the 54th ACM/IEEE Design Automation Conference, San Francisco, CA, USA, 18–22 June 2017. 57. Walsh, B.; Utomo, H.; Leobandung, E.; Mahorowala, A.; Mocuta, D.; Miyamoto, K.; Kumar, M.; Huang, S.; Gribelyuk, M.; Gabor, A.; et al. RTA-Driven Intra-Die Variations in Stage Delay, and Parametric Sensitivities for 65nm Technology. In Proceedings of the 2006 Symposium on VLSI Technology, Honolulu, HI, USA, 13–15 June 2006; pp. 170–171, Digest of Technical Papers. 58. Wei, Y.; Hu, J.; Liu, F.; Sapatnekar, S.S. Physical design techniques for optimizing RTA-induced variations. In Proceedings of the 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), Taipei, Taiwan, 18–21 January 2010; pp. 745–750. 59. Liu, F.; Chen, M.; Cao, Y. Variability analysis under layout pattern-dependent Rapid-Thermal Annealing process. In Proceedings of the 2009 46th ACM/IEEE Design Automation Conference, San Francisco, CA, USA, 26–31 July 2009; pp. 551–556. 60. Lin, S.C.; Liu, S.F.; Chen, F.L. Using genetic algorithm to optimize the dummy filling problem of the flash lamp anneal process in semiconductor manufacturing. J. Intell. Manuf. 2012, 23, 775–785. [CrossRef] 61. Davis, G.; Wilson, J.; Yu, J.J.; Chiu, A.; Chuang, Y.J.; Yang, R. ECO fill: Automated fill modification to support late-stage design changes. In Design-Process-Technology Co-Optimization for Manufacturability VIII; International Society for Optics and Photonics: Bellingham, WA, USA, 2014; Volume 9053, p. 90530S. 62. Arora, N.D. Modeling and characterization of copper interconnects for SoC design. In Proceedings of the 2003 International Conference on Simulation of Semiconductor Processes and Devices, Boston, MA, USA, 3–5 September 2003; pp. 1–6. [CrossRef] J. Low Power Electron. Appl. 2021, 11, 2 44 of 44

63. Kozhekin, A.; TowerJazz, Natanya Design Center, Israel. Personal communication, 2020. 64. Hall, G.D.R.; Allman, D.D.J.; Bhatt, H.D. Impact of via interactions and metal slotting on stress induced voiding. In Proceedings of the 2008 IEEE International Reliability Physics Symposium, Phoenix, AZ, USA, 27 April–1 May 2008; pp. 392–398.