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V13. MBE Growth and Optical Properties of III/V-II/VI Hybrid Core-Shell Nanowires
V13. MBE growth and optical properties of III/V-II/VI hybrid core-shell nanowires Alexander Pawlis and Mihail Ion Lepsa Peter Grünberg Instutite (PGI-9, PGI-10) JARA-Fundamentals for Information Technology Research Center Jülich, 52425 Contents 1. Introduction ........................................................................................................................ 2 2. Molecular beam epitaxy of semiconductor heterostructures .............................................. 3 2.1 Molecular beam epitaxy ................................................................................................... 3 2.2 MBE growth..................................................................................................................... 7 3. Growth, morphology and structural properties of GaAs/ZnSe core-shell nanowires ...... 12 3.1 Growth of self-catalyzed GaAs nanowires .................................................................... 12 3.2 Growth of ZnSe shell ..................................................................................................... 14 3.3 Structural properties of GaAs/ZnSe core/shell nanowires ............................................. 15 4. Theoretical basis for describing optical properties of semiconductor nanostructures ...... 17 4.1 Energy gap, band structure and effective mass approximation ..................................... 17 4.2 Electron-photon interaction, transition matrix and oscillator strength .......................... 19 4.3 Einstein coefficients, transition rates and radiative -
Advanced MOSFET Structures and Processes for Sub-7 Nm CMOS Technologies
Advanced MOSFET Structures and Processes for Sub-7 nm CMOS Technologies By Peng Zheng A dissertation submitted in partial satisfaction of the requirements for the degree of Doctor of Philosophy in Engineering - Electrical Engineering and Computer Sciences in the Graduate Division of the University of California, Berkeley Committee in charge: Professor Tsu-Jae King Liu, Chair Professor Laura Waller Professor Costas J. Spanos Professor Junqiao Wu Spring 2016 © Copyright 2016 Peng Zheng All rights reserved Abstract Advanced MOSFET Structures and Processes for Sub-7 nm CMOS Technologies by Peng Zheng Doctor of Philosophy in Engineering - Electrical Engineering and Computer Sciences University of California, Berkeley Professor Tsu-Jae King Liu, Chair The remarkable proliferation of information and communication technology (ICT) – which has had dramatic economic and social impact in our society – has been enabled by the steady advancement of integrated circuit (IC) technology following Moore’s Law, which states that the number of components (transistors) on an IC “chip” doubles every two years. Increasing the number of transistors on a chip provides for lower manufacturing cost per component and improved system performance. The virtuous cycle of IC technology advancement (higher transistor density lower cost / better performance semiconductor market growth technology advancement higher transistor density etc.) has been sustained for 50 years. Semiconductor industry experts predict that the pace of increasing transistor density will slow down dramatically in the sub-20 nm (minimum half-pitch) regime. Innovations in transistor design and fabrication processes are needed to address this issue. The FinFET structure has been widely adopted at the 14/16 nm generation of CMOS technology. -
Coverage Layout Design Rules and Insertion Utilities for CMP-Related Processes
Journal of Low Power Electronics and Applications Review Coverage Layout Design Rules and Insertion Utilities for CMP-Related Processes Eitan N. Shauly 1,2,* and Sagee Rosenthal 1 1 Tower Semiconductor, Migdal Ha’Emek 10556, Israel; [email protected] 2 The Faculty of Materials Science and Engineering, Technion-Israel Institute of Technology, Haifa 32000, Israel * Correspondence: [email protected] Abstract: The continuous scaling needed for higher density and better performance has introduced some new challenges to the planarity processes. This has resulted in new definitions of the layout coverage rules developed by the foundry and provided to the designers. In advanced technologies, the set of rules considers both the global and the local coverage of the front-end-of line (FEOL) dielectric layers, to the back-end-of-line (BEOL) Cu layers and Al layers, to support high-k/Metal Gate process integration. For advance technologies, a new set of rules for dummy feature insertion was developed by the integrated circuit (IC) manufacturers in order to fulfill coverage limits. New models and utilities for fill insertion were developed, taking into consideration the design coverage, thermal effects, sensitive signal line, critical analog and RF devices like inductors, and double patterning requirements, among others. To minimize proximity effects, cell insertion was also introduced. This review is based on published data from leading IC manufacturers with a careful integration of new experimental data accumulated by the authors. We aim to present a typical foundry perspective. The review provides a detailed description of the chemical mechanical polishing (CMP) process and the coverage dependency, followed by a comprehensive description of coverage rules needed for dielectric, poly, and Cu layers used in advanced technologies. -
A Back-End, CMOS Compatible Ferroelectric Field Effect Transistor
A back-end, CMOS compatible ferroelectric Field Effect Transistor for synaptic weights , , Mattia Halter,∗ † ‡ Laura Bégon-Lours,† Valeria Bragaglia,† Marilyne Sousa,† Bert Jan Offrein,† Stefan Abel,† Mathieu Luisier,‡ and Jean Fompeyrine† IBM Research GmbH - Zurich Research Laboratory, CH-8803 RÃijschlikon, Switzerland † Integrated Systems Laboratory, ETH Zurich, CH-8092 Zurich, Switzerland ‡ E-mail: [email protected] Abstract Neuromorphic computing architectures enable the dense co-location of memory and processing elements within a single circuit. This co-location removes the communi- cation bottleneck of transferring data between separate memory and computing units as in standard von Neuman architectures for data-critical applications including ma- chine learning. The essential building blocks of neuromorphic systems are non-volatile synaptic elements such as memristors. Key memristor properties include a suitable non-volatile resistance range, continuous linear resistance modulation and symmetric arXiv:2001.06475v1 [cs.ET] 17 Jan 2020 switching. In this work, we demonstrate voltage-controlled, symmetric and analog po- tentiation and depression of a ferroelectric Hf0.57Zr0.43O2 (HZO) field effect transistor (FeFET) with good linearity. Our FeFET operates with a low writing energy (fJ) and fast programming time (40 ns). Retention measurements have been done over 4-bits depth with low noise (1 %) in the tungsten oxide (WOx) read out channel. By ad- justing the channel thickness from 15nm to 8nm, the on/off ratio of the FeFET can be engineered from 1 % to 200 % with an on-resistance ideally >100 kΩ, depending on the channel geometry. The device concept is using earth-abundant materials, and is 1 compatible with a back end of line (BEOL) integration into complementary metal-oxide- semiconductor (CMOS) processes. -
Investigation of Structural Characteristics of III-V Semiconductor Nanowires Grown by Molecular Beam Epitaxy Zhi Zhang Master of Chemical Engineering
Investigation of Structural Characteristics of III-V Semiconductor Nanowires Grown by Molecular Beam Epitaxy Zhi Zhang Master of Chemical Engineering A thesis submitted for the degree of Doctor of Philosophy at The University of Queensland in 2015 School of Mechanical and Mining Engineering Abstract One-dimensional nanowires made of III-V semiconductors have attracted significant research interest in the recent decades due to their distinct physical and chemical properties that can potentially lead to a wide range of applications in nanoelectronics and optoelectronics. As a key class of III-V semiconductor nanowires, InAs nanowires have attracted special attention due to their narrow bandgap, relatively high electron mobility, and small electron effective mass, which made them a promising candidate for the applications in future optical and high- frequency electronic devices. One of the challenges in realizing these unique III-V nanowire properties in nanowire-based devices is to integrate nanowires on the nano-devices or chips with well-organized arrangement. To solve this issue, the epitaxial nanowire growth provides the uniqueness that well aligned nanowires can be grown on the chosen substrates, and by selecting substrates with particular orientations, specifically orientated nanowires can be grown. Au-assisted nanowire growth is one of the most common methods to grow epitaxial III-V nanowires via the vapor-liquid-solid (VLS) mechanism or vapor-solid-solid (VSS) mechanism. For III-V nanowires, one of the coherent problems is that the stacking faults and/or twin defects can easily be introduced in both wurtzite or zinc-blende structured nanowires due to the small energy differences between wurtzite and zinc-blende stacking sequences of their dense planes. -
Design, Fabrication, and Characterization of Three‑Dimensional Embedded Capacitor in Through‑Silicon Via
This document is downloaded from DR‑NTU (https://dr.ntu.edu.sg) Nanyang Technological University, Singapore. Design, fabrication, and characterization of three‑dimensional embedded capacitor in through‑silicon via Lin, Ye 2019 Lin, Y. (2019). Design, fabrication, and characterization of three‑dimensional embedded capacitor in through‑silicon via. Doctoral thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/102666 https://doi.org/10.32657/10220/48586 Downloaded on 28 Sep 2021 02:52:36 SGT ( O n th e S p ine) DESIGN, FA BRICATION, AND CHARACTERIZATION OF 3 DESIGN, FABRICATION, AND CHARACTERIZATION OF THREE-DIMENSIONAL EMBEDDED CAPACITOR IN THROUGH-SILICON VIA - D EMBEDDED CAPACITOR IN TSV LIN YE LIN YE SCHOOL OF ELECTRICAL AND ELECTRONIC ENGINEERING 2019 2019 DESIGN, FABRICATION, AND CHARACTERIZATION OF THREE-DIMENSIONAL EMBEDDED CAPACITOR IN THROUGH-SILICON VIA LIN YE (B. Eng., Nanyang Technological University) SCHOOL OF ELECTRICAL AND ELECTRONIC ENGINEERING A thesis submitted to the Nanyang Technological University in partial fulfillment of the requirement for the degree of Doctor of Philosophy 2019 Statement of Originality I hereby certify that the work embodied in this thesis is the result of original research, is free of plagiarised materials, and has not been submitted for a higher degree to any other University or Institution. 28 May 2019 Date Lin Ye Supervisor Declaration Statement I have reviewed the content and presentation style of this thesis and declare it is free of plagiarism and of sufficient grammatical clarity to be examined. To the best of my knowledge, the research and writing are those of the candidate except as acknowledged in the Author Attribution Statement. -
Comparison of DC High-Frequency Performance of Zinc-Doped And
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 5, MAY 2002 725 Comparison of DC High-Frequency Performance of Zinc-Doped and Carbon-Doped InP/InGaAs HBTs Grown by Metalorganic Chemical Vapor Deposition Delong Cui, Dimitris Pavlidis, Fellow, IEEE, Shawn S. H. Hsu, and Andreas Eisenbach Abstract—Zinc and carbon-doped InP/InGaAs heterojunction by the low temperature growth of the carbon-doped base in an bipolar transistors (HBTs) with the same design were grown HBT structure could lead to the degradation of base-emitter by metalorganic chemical vapor deposition (MOCVD). Dc and base-collector junction and hence degrade even further the current gain values of 36 and 16 were measured for zinc and electrical performance of carbon-doped HBTs. carbon-doped HBTs, respectively, and carrier lifetimes were measured by time-resolved photoluminescnce to explain the dif- Recently, carbon-doped InP/InGaAs HBTs have been grown ference. Transmission line model (TLM) analysis of carbon-doped by MOCVD. 62-GHz and 42 GHz have been achieved base layers showed excellent sheet-resistance (828 for 600 by using TEGa and CCl as precursors [21], [22]. A two-step e# base), indicating successful growth of highly carbon-doped MOCVD growth procedure has been also proposed to increase IW Q base (2 10 cm ). The reasons for larger contact resistance the of carbon-doped HBTs to 160 GHz [23]. However, of carbon than zinc-doped base despite its low sheet resistance it requires regrowth and the regrowth temperature must also were analyzed. and mx of 72 and 109 GHz were measured be low to prevent rehydrogenation during deposition. -
Chemical Vapor Deposition Epitaxy on Patternless and Patterned Substrates
ELECTRONIC MATERIALS PROCESSING CHEMICAL VAPOR DEPOSITION EPITAXY ON PATTERNLESS AND PATTERNED SUBSTRATES CHRISTOS G. TAKOUDIS Purdue University West Lafayette, IN 47907 (a) HE ELECTRONIC MATERIALS processing curric Tulum at Purdue consists primarily of a one-semes ter course. The objective of this course is to provide chemical engineering students with the basic princi ples and practical aspects of the most advanced state of electronics processing. The main emphasis of the (b) ~ course is on fundamental processes especially useful - ~a~,/J - for Very Large Scale Integration (VLSI) schemes [1]. 0 0 0 0 0 About five weeks are devoted to epitaxy, which is a process by which material is deposited onto a crys talline substrate or seed, and the crystalline config (c) uration is maintained. Two and one-half weeks are devoted to Vapor Phase Epitaxy (VPE) on patternless substrates, one week to VPE on patterned substrates typically known as Selective Epitaxial Growth (SEG), one week to doping profiles in epitaxially grown thin films, and one-half week to other kinds of epitaxy (e .g., Molecular Beam Epitaxy (MBE), Plasma As (d) sisted Chemical Vapor Deposition (PACVD)). The purpose of this paper is to focus on Chemical Vapor Deposition (CVD) epitaxy on patternless and pat terned substrates in the manner in which it has been developed in our course over the past five years. Journal articles play a very important role in many educational aspects of the CVD epitaxy on patternless (e) ==- and patterned substrates. A list of such journal arti ~ - 1/1 111/ll/ ll/ l ( - p E:=ic=5 1=5 cles typically used in class is presented at the end of FIGURE 1. -
2013 Edition
INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS 2013 EDITION INTERCONNECT THE ITRS IS DEVISED AND INTENDED FOR TECHNOLOGY ASSESSMENT ONLY AND IS WITHOUT REGARD TO ANY COMMERCIAL CONSIDERATIONS PERTAINING TO INDIVIDUAL PRODUCTS OR EQUIPMENT. THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2013 Table of Content Interconnect .......................................................................................................................... 1 1. Scope ................................................................................................................ 1 1.1. Introduction ..................................................................................................................................... 1 1.2. What’s new for 2013? .................................................................................................................... 1 2. Summary ........................................................................................................... 2 2.1. Difficult Challenges......................................................................................................................... 2 2.2. Interconnect Architectures ............................................................................................................. 4 2.3. 3D Interconnect Architectures ........................................................................................................ 6 2.4. Passive Devices .......................................................................................................................... -
EMC-99 Advance Mailer
Minerals • Metals Materials Address Service Requested T University of California T S Santa Barbara, California MineralsT • Metals • MaterialsS June 30 – July 2, 1999 Minerals • Metals • Materials S 184 Thorn Hill Road, Warrendale, Pennsylvania 15086-7528 USA Thorn Hill Road, Warrendale, 184 41st ELECTRONIC MATERIALS CONFERENCE FIRST CLASS MAIL WARRENDALE, PA PERMIT NO. 16 U.S. POSTAGE June 30 - July 2, 1999 PAID ADVANCE PROGRAM Includes Housing & Registration Forms http://www.tms.org/Meetings/Specialty/EMC99/EMC99.html Schedule of Events Picnic: Evening at the Zoo .............................. 6:00PM-9:00PM 41st Electronic Materials Conference Location ............................ Santa Barbara Zoological Gardens Session J. Epitaxy for Devices-A.................................. 8:20AM Tuesday, June 29, 1999 Session K. Nanoscale Characterization ...................... 8:20AM Registration ....................................................... 3:00PM-8:00PM Session L. Wide Bandgap AlGaN/GaN Location .................University Center/Multicultural Lounge Heterostructures ............................................................. 8:20AM Session M. SiC Growth & Characterization ............... 8:20AM Wednesday, June 30, 1999 Session N. Infrared Materials & Devices .................... 8:20AM Session O. Issues for Ferroelectric Registration ...................................................... 7:30AM-5:00PM & High Permittivity Thin Film Materials .................... 8:20AM Location .................University Center/Multicultural Lounge -
Physical, Electrical, and Reliability Considerations for Copper BEOL Layout Design Rules
Journal of Low Power Electronics and Applications Review Physical, Electrical, and Reliability Considerations for Copper BEOL Layout Design Rules Eitan N. Shauly 1,2 1 TowerJazz Corporation, Migdal Ha’Emek 10556, Israel; [email protected]; Tel.: +972-4-6506570 2 The Faculty of Materials Science and Engineering, Technion-Israel Institute of Technology, Haifa 32000, Israel Received: 16 March 2018; Accepted: 18 May 2018; Published: 14 June 2018 Abstract: The continuous scaling needed for better performance and higher density has introduced some new challenges to the back end of line (BEOL) in terms of layout and design. Reductions in metal line width, spacing, and thickness require major changes in both process and design environments. Advanced deep-submicron layout design rules (DRs) should now consider many new proximity effects and reliability concerns due to high electrical fields and currents, planarization-related coverage effects, etc. It is, therefore, necessary to redefine many of the common DRs. For example, space rules now have a complex definition, including both line width and parallel length. In addition, new rules have been introduced to represent the challenges of reliability such as stress-induced voids, time-dependent dielectric breakdowns of intermetal dielectrics, dependency on misalignment, sensitivity to double patterning, etc. This review describes a set of copper (Cu) BEOL layout design rules, as used in technologies featuring lengths ranging from 0.15 µm to 20 nm. The verification of layout rules and sensitivity issues related to them are presented. Reliability-related aspects of some rules, like space, width, and via density, are also discussed with additional design-for-manufacturing layout recommendations. -
Dissertation Pretext
AN ABSTRACT OF THE DISSERTATION OF Dustin Zachary Austin for the degree of Doctor of Philosophy in Electrical and Computer Engineering presented on May 19, 2017. Title: Atomic Layer Deposition of Multi-Insulator Metal-Insulator-Metal Capacitors. Abstract approved: ______________________________________________________ John F. Conley Jr. Back end of line (BEOL) metal-insulator-metal capacitors (MIMCAPs) have become a core passive component in modern integrated circuits. International Technology Roadmap for Semiconductors (ITRS) projections for scaling of analog/mixed-signal MIMCAP applications require simultaneously increasing capacitance density while maintaining low leakage current density and low voltage nonlinearity (characterized by the quadratic voltage coefficient of capacitance, αVCC). In addition to these conflicting performance requirements, BEOL processing allows for temperatures of no more than 400°C. In this work, atomic layer deposition (ALD) of both dielectrics and metals have been investigated to develop complementary multi-insulator MIMCAPs to meet future ITRS requirements. Initially Al2O3/SiO2 bilayers are assessed for targeting the ITRS 2020 node. These oxides are attractive due to their large metal-insulator barrier heights, high dielectric breakdown strength, and common usage in IC fabrication. SiO2 is one of only a few materials to exhibit a negative αVCC, which in combination with the positive αVCC of Al2O3 enables ultra-low device αVCC through the "canceling" effect. ALD for these ultra- thin insulators has become the preferred deposition method due to the inherent low deposition temperatures, precise film thickness control, and excellent film quality. Next, to support scaling beyond the 2020 node, novel ALD processes are developed for bismuth oxide (Bi2O3), ruthenium oxide (RuO2), and ruthenium metal (Ru).