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2013 Edition INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS 2013 EDITION INTERCONNECT THE ITRS IS DEVISED AND INTENDED FOR TECHNOLOGY ASSESSMENT ONLY AND IS WITHOUT REGARD TO ANY COMMERCIAL CONSIDERATIONS PERTAINING TO INDIVIDUAL PRODUCTS OR EQUIPMENT. THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2013 Table of Content Interconnect .......................................................................................................................... 1 1. Scope ................................................................................................................ 1 1.1. Introduction ..................................................................................................................................... 1 1.2. What’s new for 2013? .................................................................................................................... 1 2. Summary ........................................................................................................... 2 2.1. Difficult Challenges......................................................................................................................... 2 2.2. Interconnect Architectures ............................................................................................................. 4 2.3. 3D Interconnect Architectures ........................................................................................................ 6 2.4. Passive Devices ........................................................................................................................... 13 2.5. More Moore versus More Than Moore......................................................................................... 16 3. Reliability and Performance ..............................................................................16 3.1. Reliability Introduction .................................................................................................................. 16 3.2. Metallization Reliability ................................................................................................................. 17 3.3. Dielectric Reliability ...................................................................................................................... 23 3.4. Interconnect Performance ............................................................................................................ 29 4. Process Modules ..............................................................................................33 4.1. Dielectric Potential Solutions ........................................................................................................ 33 4.2. Barrier Potential Solutions ............................................................................................................ 39 4.3. Nucleation Potential Solutions ..................................................................................................... 41 4.4. Conductor Potential Solutions ...................................................................................................... 43 4.5. Etch / Strip / Clean Potential Solutions ........................................................................................ 45 4.6. Planarization Potential Solutions .................................................................................................. 50 4.7. Through-Si-VIA (TSV), 3D Stacking Technology ......................................................................... 56 5. Emerging Interconnect Solutions ......................................................................62 5.1. Overview ...................................................................................................................................... 62 5.2. Cu Replacements ......................................................................................................................... 63 5.3. CMOS-compatible Optical Interconnects and I/O ........................................................................ 68 5.4. Superconductors .......................................................................................................................... 70 5.5. Wireless Interconnect ................................................................................................................... 70 5.6. Si CMOS Replacements and Interconnect Implications .............................................................. 71 6. CrossCut Challenges ........................................................................................76 6.1. ESH .............................................................................................................................................. 76 6.2. Chip-Package-Interaction (CPI) ................................................................................................... 77 7. Appendices .......................................................................................................78 7.1. Passive Devices ........................................................................................................................... 78 7.2. Dielectric Appendix....................................................................................................................... 83 7.3. Interconnect Model Adopted for RC Delay Evaluation Appendix ................................................ 84 7.4. Glossary of 3D and TSV Definitions............................................................................................. 85 8. References .......................................................................................................87 THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2013 List of Figures Figure INTC1 Typical Cross-sections of Hierarchical Scaling (MPU Device (left), ASIC (middle) and Flash Memory (right)) ............................................................ 4 Figure INTC2 Typical ILD Architectures ..................................................................................... 5 Figure INTC3 Schematic Cross-sections of TSV First and Middle/Last Process Flows ................................................................................................................... 9 Figure INTC4 Schematic Representation of the Various Key Process Modules and 3D-stacking Options when using Through-Si-Via 3D-SIC Technologies ..................................................................................................... 10 Figure INTC5 Schematic Representation of the Various Key Process Modules and 3D-stacking Options when using Through-Si-Via 3D-WLP Technologies ..................................................................................................... 11 Figure INTC6 Experiment and model of lifetime scaling versus interconnect geometry ( from Ref 8) ...................................................................................... 18 Figure INTC7 Evolution of lifetime vs. technology node. Black line shows trend for reduced critical void volume: Green line shows the EM enhancement urgently needed (Courtesies of A. Aubel/GLOBALFOUNDRIES) ...................... 18 Figure INTC8 Calculation Model for Jmax (The maximum equivalent dc current expected to appear in a high-performance digital circuit divided by the cross-sectional area of an intermediate wire.) .................................................... 19 Figure INTC9 Evolution of Jmax (from device requirement) and JEM (from targeted lifetime) .............................................................................................................. 19 Figure INTC10 Comparison of the Lifetime Improvement versus the Resistivity Increase for Different EM Resistance Booster Technologies11 ........................... 20 Figure INTC11 Comparison of EM lifetime for Cu and CuMn interconnects at 0.1% (NSD = -3) as a function of line height h x via size d for various technologies. CuMn significantly enhances the EM lifetime for 40nm and 28nm nodes to levels exceeding the Cu 65nm node (From Ref.29). ............................................................................................................. 22 Figure INTC12 Degradation paths in low-κ damascene structure .............................................. 23 Figure INTC13 Impact of CMP and post CMP delay time on dielectric breakdown: Dielectric breakdown voltage decreases as post Cu CMP delay time increases[2] ....................................................................................................... 24 Figure INTC14 Impact of plasma process on low-κ TDDB [7] .................................................... 24 Figure INTC15 Effect of pore sealing on low-κ reliability: breakdown electric field at T=100°C for a 50nm dielectric spacing of PEBO- and PCBO- integrated porous SiLKTM [8]. ........................................................................... 25 Figure INTC16 Impact of bulk low-κ property on low-κ reliability: Leakage current density versus applied electric field for two CVD low-κ after curing and after curing and porogen removal by He/H2 plasma [10] ............................. 25 Figure INTC17 Cross-section and top-down schematics of low-κ planar capacitor structure designed for intrinsic TDDB study of barrier/low-κ for damascene integration [11] ............................................................................... 26 Figure INTC18 Likelihood ratio of the simultaneous fits of all lifetime models for the 4 data sets of TABLE I with κ≥2.5. E-model was used as a reference and its likelihood ratio is 1 by definition
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