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Front-End Electronics for Multichannel Semiconductor Detector Systems; Eucard Editorial Series on Accelerator Science and Technology, Vol.08

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Front-End Electronics for Multichannel Semiconductor Detector Systems; Eucard Editorial Series on Accelerator Science and Technology, Vol.08 EuCARD-BOO-2010-004 European Coordination for Accelerator Research and Development PUBLICATION Front-end Electronics for Multichannel Semiconductor Detector Systems; EuCARD Editorial Series on Accelerator Science and Technology, Vol.08 Grybos, P (AGH-UST, Krakow, Poland) 17 August 2012 The research leading to these results has received funding from the European Commission under the FP7 Research Infrastructures project EuCARD, grant agreement no. 227579. This work is part of EuCARD Work Package 4: AccNet: Accelerator Science Networks. The electronic version of this EuCARD Publication is available via the EuCARD web site <http://cern.ch/eucard> or on the CERN Document Server at the following URL : <http://cdsweb.cern.ch/record/1473436 EuCARD-BOO-2010-004 Pawe³ Gryboœ Front-end Electronics for Multichannel Semiconductor Detector Systems Editorial Series on ACCELERATOR SCIENCE Institute of Electronic Systems Warsaw University of Technology — Warsaw 2010 Kazimierz Korbel Andrzej Napieralski the part of 64-channel DEDIX integrated circuit (photo courtesy of Luciano Ramello) Front-end electronics for multichannel semiconductor detector systems i CONTENTS Acknowledgements ...................................................................................................................... iii List of symbols ..............................................................................................................................iv Abbreviations and acnonyms used in the text..............................................................................viii 1. Introduction ................................................................................................................................1 2. Semiconductor detectors.............................................................................................................5 2.1. Materials for semiconductor detectors ............................................................................6 2.2. Reverse bias p-n junction ................................................................................................8 2.3. Charge generation in detector........................................................................................13 2.4. Charge transport ............................................................................................................15 2.5. Ramo theory and signal formation ................................................................................19 2.6. Detector geometry.........................................................................................................21 2.7. Important detector parameters.......................................................................................23 3. Architecture of front-end electronics........................................................................................27 3.1. Types of amplifiers........................................................................................................29 3.2. Charge sensitive amplifier.............................................................................................31 3.2.1. Ideal charge sensitive amplifier .........................................................................31 3.2.2. Realistic charge sensitive amplifier ...................................................................33 3.2.3. Examples of core amplifier architectures...........................................................37 3.2.4. Feedback configuration......................................................................................40 3.2.5. Test injection circuit ..........................................................................................42 3.3. Shaper............................................................................................................................43 3.3.1. Signal shaping....................................................................................................44 3.3.2. Noise analysis ....................................................................................................56 3.4. Noise optimization of CSA input transistor ..................................................................62 3.4.1. Strong inversion region......................................................................................63 3.4.2. Moderate and weak inversion regions ...............................................................66 3.5. Aspect of fast signal processing ....................................................................................70 3.5.1. Pulse pile-ups at CSA output .............................................................................71 3.5.2. Pole-zero cancellation circuit.............................................................................72 3.5.3. Base line restorer ...............................................................................................75 3.6. Further signal processing...............................................................................................80 3.6.1. Discriminators....................................................................................................83 3.6.2. Peak Detector Derandomizer .............................................................................86 4. Important aspect of multichannel low noise mixed-mode integrated circuits..........................89 4.1. Noise modeling in MOS transistors ..............................................................................91 4.1.1. Channel thermal noise........................................................................................91 4.1.2. Flicker noise.......................................................................................................94 4.1.3. Short channel effects..........................................................................................96 Front-end electronics for multichannel semiconductor detector systems ii 4.2. Cross-talk in mixed mode circuits.................................................................................98 4.2.1. Generation, transmission and reception of switching noise...............................98 4.2.2. Reducing the noise generation .........................................................................102 4.2.3. Increasing the immunity of analog part ...........................................................103 4.2.4. Isolation techniques .........................................................................................103 4.2.5. Summary of crosstalk reduction techniques ....................................................106 4.3. Random matching and offsets .....................................................................................107 4.3.1. Mismatch parameters of MOS transistors........................................................109 4.3.2. Transistor matching in various processes ........................................................112 4.3.3. Current matching in MOS transistors ..............................................................114 4.3.4. Random matching in circuits ...........................................................................115 4.3.5. Layout rules for good matching.......................................................................116 4.3.6. Matching on multichip modules ......................................................................118 4.3.7. Mismatch simulation using Monte Carlo analysis ...........................................119 5. Radiation damage in silicon detectors and readout electronics...............................................121 5.1. Total dose effects ........................................................................................................122 5.1.1. Displacement damage ......................................................................................122 5.1.2. Ionization effects..............................................................................................123 5.2. Single event effects .....................................................................................................127 5.3. Radiation tolerant design of readout electronics .........................................................128 6. Examples of multichannel counting IC for X-ray applications...............................................131 6.1. Requirements for multichannel counting systems.......................................................132 6.2. ASIC for strip detectors...............................................................................................135 6.3. Solutions for pad detectors and small array of pixel detectors....................................141 6.4. Solutions for pixel detectors........................................................................................148 7. References ..............................................................................................................................173 Front-end electronics for multichannel semiconductor detector systems iii Acknowledgements This monograph is the result of countless interactions with many people who de- voted their precious time and effort trying to teach me electronics. At various occasions I have met them at universities, research institutes, conferences, meetings, or just on the web. I would like to thank them all for their open mind, patience and cordial assistance. I have also benefited from suggestions made by my reviewers: Prof. Kazimierz Korbel and Prof. Andrzej Napieralski. I wish to extend my appreciation to Robert Szczygieł for proof-reading and
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