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Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models

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Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models Outline • Low-frequency small-signal equivalent circuit model • High-frequency small-signal equivalent circuit model Reading Assignment: Howe and Sodini; Chapter 4, Sections 4.5-4.6 Announcements: 1.Quiz#1: March 14, 7:30-9:30PM, Walker Memorial; covers Lectures #1-9; open book; must have calculator • No Recitation on Wednesday, March 14: instructors or TA’s available in their offices during recitation times 6.012 Spring 2007 Lecture 10 1 Large Signal Model for NMOS Transistor Regimes of operation: VDSsat=VGS-VT ID linear saturation ID V DS VGS V GS VBS VGS=VT 0 0 cutoff VDS • Cut-off I D = 0 • Linear / Triode: W V I = µ C ⎡ V − DS − V ⎤ • V D L n ox⎣ GS 2 T ⎦ DS • Saturation W 2 I = I = µ C []V − V •[1 + λV ] D Dsat 2L n ox GS T DS Effect of back bias VT(VBS ) = VTo + γ [ −2φp − VBS −−2φp ] 6.012 Spring 2007 Lecture 10 2 Small-signal device modeling In many applications, we are only interested in the response of the device to a small-signal applied on top of a bias. ID+id + v - ds + VDS v + v gs - - bs VGS VBS Key Points: • Small-signal is small – ⇒ response of non-linear components becomes linear • Since response is linear, lots of linear circuit techniques such as superposition can be used to determine the circuit response. • Notation: iD = ID + id ---Total = DC + Small Signal 6.012 Spring 2007 Lecture 10 3 Mathematically: iD(VGS, VDS , VBS; vgs, vds , vbs ) ≈ ID()VGS , VDS ,VBS + id (vgs, vds, vbs ) With id linear on small-signal drives: id = gmvgs + govds + gmbvbs Define: gm ≡ transconductance [S] go ≡ output or drain conductance [S] gmb ≡ backgate transconductance [S] Approach to computing gm, go, and gmb. ∂i g ≈ D m ∂v GS Q ∂i g ≈ D o ∂v DS Q ∂i g ≈ D mb ∂v BS Q Q ≡ [vGS = VGS, vDS = VDS, vBS = VBS] 6.012 Spring 2007 Lecture 10 4 Transconductance In saturation regime: W 2 i = µ C []v − V • []1 + λV D 2L n ox GS T DS Then (neglecting channel length modulation) the transconductance is: ∂i W g = D ≈ µ C ()V − V m ∂v L n ox GS T GS Q Rewrite in terms of ID: W g = 2 µ C I m L n ox D g m saturation 0 0 ID 6.012 Spring 2007 Lecture 10 5 Transconductance (contd.) Equivalent circuit model representation of gm: id G D + vgs gmvgs - S B 6.012 Spring 2007 Lecture 10 6 Output conductance In saturation regime: W 2 i = µ C []v − V • []1 + λV D 2L n ox GS T DS Then: ∂i W 2 g = D = µ C ()V − V • λ ≈ λI o ∂v 2L n ox GS T D DS Q Output resistance is the inverse of output conductance: 1 1 ro = = go λID Remember also: 1 λ ∝ L Hence: ro ∝ L 6.012 Spring 2007 Lecture 10 7 Output conductance (contd.) Equivalent circuit model representation of go: id G D + vgs ro - S B 6.012 Spring 2007 Lecture 10 8 Backgate transconductance In saturation regime (neglect channel length modulation): W 2 iD ≈ µnCox[]vGS − VT 2L Then: ∂i W ⎛ ∂V ⎞ g = D =− µ C ()V − V • ⎜ T ⎟ mb ∂v L n ox GS T ∂v BS Q ⎝ BS Q⎠ Since: VT(vBS ) = VTo + γ [ −2φp − vBS −−2φp ] Then : ∂V −γ T = ∂v 2 −2φ − V BS Q p BS Hence: γ gm gmb = 2 −2φp − VBS 6.012 Spring 2007 Lecture 10 9 Backgate transconductance (contd.) Equivalent circuit representation of gmb: id G D + vgs gmbvbs - S - vbs + B 6.012 Spring 2007 Lecture 10 10 Complete MOSFET small-signal equivalent circuit model for low frequency: id G D + vgs gmvgs gmbvbs ro - S - vbs + B + V metal − DS + V interconnect to gate − GS + n polysilicon gate + n source 0 y n+ drain + QN(y) Xd(y) V BS − x p-type metal interconnect to bulk 6.012 Spring 2007 Lecture 10 11 2. High-frequency small-signal equivalent circuit model Need to add capacitances. In saturation: fringe electric field lines gate source drain n+ n+ C q (v ) sb N GS C depletion L db overlap LD overlap D region Cgs ≡ channel charge + overlap capacitance, Cov Cgd ≡ overlap capacitance, Cov Csb ≡ source junction depletion capacitance (+sidewall) Cdb ≡ drain junction depletion capacitance (+sidewall) ONLY Channel Charge Capacitance is intrinsic to device operation. All others are parasitic. 6.012 Spring 2007 Lecture 10 12 Inversion layer charge in saturation L vGS −VT dy q (v ) = WQ(y)dy = WQ(v )• • dv N GS ∫ N ∫ N C C 0 0 dvC Note that qN is total inversion charge in the channel & vC(y) is the channel voltage. But: dv i C =− D dy W µnQN (vC ) Then: 2 VGS −VT W µ 2 q (v ) =− n • Q (v ) • dv N GS ∫ []N C C iD 0 Remember: QN (vC ) =−Cox [vGS − vC (y) − VT ] Then: 2 v −V W µ GS T 2 q (v ) =− n • []v − v (y) − V • dv N GS i ∫ GS C T C D 0 6.012 Spring 2007 Lecture 10 13 Inversion layer charge in saturation (contd.) Do integral, substitute iD in saturation and get: 2 q (v ) =− WLC ()v − V N GS 3 ox GS T Gate charge: qG (vGS ) = −qN (vGS ) − QB,max Intrinsic gate-to-source capacitance: dqG 2 Cgs,i = = WLCox dv GS 3 Must add overlap capacitance: 2 C = WLC + WC gs 3 ox ov Gate-to-drain capacitance — only overlap capacitance: Cgd = WCov 6.012 Spring 2007 Lecture 10 14 Other capacitances NRS = N (source) NRD = N (drain) = × = = × = PS 2 L (source) W PD 2 L (drain) W diff diff L Ldiff (source) Ldiff (drain) W = × = × AS W Ldiff (source) AD W Ldiff (drain) Source-to-Bulk capacitance: Csb = WLdiff C j + (2Ldiff + W)C jsw 2 where C j : Bottom Wall at VSB(F / cm ) C jsw : Side Wall at VSB(F / cm) Drain-to-Bulk capacitance: Cdb = WLdiff C j + (2Ldiff + W)C jsw 2 where C j : Bottom Wall at VDB(F/ cm ) C jsw : Side Wall at VDB(F / cm) Gate-to-Bulk capacitance: Cgb ≡ small parasitic capacitance in most cases (ignore) 6.012 Spring 2007 Lecture 10 15 What did we learn today? Summary of Key Concepts High-frequency small-signal equivalent circuit model of MOSFET Cgd id G D + vgs Cgs Cgb gmvgs gmbvbs ro - S - vbs Csb + B Cdb In saturation: W g ∝ I m L D L ro ∝ I D Cgs ∝ WLCox 6.012 Spring 2007 Lecture 10 16.
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