DOCSLIB.ORG

Analyzing the Effect of Parasitic Capacitance in a Full-Bridge Class-D Current Source Rectifier on a High Step-Up Push–Pull Multiresonant Converter

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Analyzing the Effect of Parasitic Capacitance in a Full-Bridge Class-D Current Source Rectifier on a High Step-Up Push–Pull Multiresonant Converter sustainability Article Analyzing the Effect of Parasitic Capacitance in a Full-Bridge Class-D Current Source Rectifier on a High Step-Up Push–Pull Multiresonant Converter Anusak Bilsalam 1,* , Chainarin Ekkaravarodome 2, Viboon Chunkag 3 and Phatiphat Thounthong 4 1 Department of Electrical Engineering Technology, College of Industrial Technology (CIT), King Mongkut’s University of Technology North Bangkok (KMUTNB), 1518 Pracharat 1 Rd., Wongsawang, Bang Sue, Bangkok 10800, Thailand 2 Advanced Power Electronics and Experiment Laboratory, Department of Instrumentation and Electronics Engineering, Faculty of Engineering, King Mongkut’s University of Technology North Bangkok (KMUTNB), 1518 Pracharat 1 Rd., Wongsawang, Bang Sue, Bangkok 10800, Thailand; [email protected] 3 Department Electrical and Computer Engineering, Faculty of Engineering, King Mongkut’s University of Technology North Bangkok (KMUTNB), 1518 Pracharat 1 Rd., Wongsawang, Bang Sue, Bangkok 10800, Thailand; [email protected] 4 Renewable Energy Research Centre, Department of Teacher Training in Electrical Engineering, Faculty of Technical Education, King Mongkut’s University of Technology North Bangkok (KMUTNB), 1518 Pracharat 1 Rd., Wongsawang, Bang Sue, Bangkok 10800, Thailand; [email protected] * Correspondence: [email protected] Abstract: This paper presents an analysis on the effect of a parasitic capacitance full-bridge class-D current source rectifier (FB-CDCSR) on a high step-up push–pull multiresonant converter (HSPPMRC). The proposed converter can provide high voltage for a 12 V battery using an isolated transformer Citation: Bilsalam, A.; DC Ekkaravarodome, C.; Chunkag, V.; and an FB-CDCSR. The main switches of the push–pull and diode full-bridge rectifier can be operated Thounthong, P. Analyzing the Effect under a zero-current switching condition (ZCS). The advantages of this technique are that it uses a of Parasitic Capacitance in a leakage inductance to achieve the ZCS for the power switch, and the leakage inductance and parasitic Full-Bridge Class-D Current Source junction capacitance are used to design the secondary side of the resonant circuit. A prototype Rectifier on a High Step-Up HSPPMRC was built and operated at 200 kHz fixed switching frequency, 340 VDC output voltage, Push–Pull Multiresonant Converter. and 250 W output power. In addition, the efficiency is equal to 96% at maximum load. Analysis of the Sustainability 2021, 13, 5477. https:// effect of the parasitic junction capacitance on the full-bridge rectifier indicates that it has a significant doi.org/10.3390/su13105477 impact on the operating point of the resonant tank and voltage. The proposed circuit design was verified via experimental results, which were found to be in agreement with the theoretical analysis. Academic Editor: Detlef Schulz Keywords: parasitic capacitance; high step-up; zero-current switching; multiresonant; converter; Received: 15 April 2021 current source rectifier Accepted: 6 May 2021 Published: 13 May 2021 Publisher’s Note: MDPI stays neutral 1. Introduction with regard to jurisdictional claims in published maps and institutional affil- Currently, fossil fuel sources are being depleted owing to the considerable increase iations. in the need for energy sources. To overcome this problem, efforts have been invested to develop renewable energy systems in the energy production field. In recent years, high step-up converters have been widely used in distributed power generators based on battery energy storage (BES) and module-integrated converters (MIC) with a DC link, and in stand- alone/grid-connected renewable energy systems such as photovoltaic cells, wind turbines, Copyright: © 2021 by the authors. Licensee MDPI, Basel, Switzerland. and fuel cells. These systems, which can be single or hybrid, use energy sources to generate This article is an open access article electricity [1–4]. As these are low-voltage systems, the output voltage can be varied. For distributed under the terms and maintaining system voltage, a battery system is generally used to back-up the system conditions of the Creative Commons with a constant DC-link in the inverter state. Therefore, to increase the low voltage of the Attribution (CC BY) license (https:// battery to a suitable value, a high step-up converter is employed to step-up the low input creativecommons.org/licenses/by/ voltage to a high output voltage. High step-up topologies are classified into nonisolated 4.0/). and isolated DC/DC converters. The nonisolated topology typically uses a boost converter Sustainability 2021, 13, 5477. https://doi.org/10.3390/su13105477 https://www.mdpi.com/journal/sustainability Sustainability 2021, 13, x FOR PEER REVIEW 2 of 20 system with a constant DC-link in the inverter state. Therefore, to increase the low voltage of the battery to a suitable value, a high step-up converter is employed to step-up the low input voltage to a high output voltage. High step-up topologies are classified into noniso- lated and isolated DC/DC converters. The nonisolated topology typically uses a boost con- Sustainability 2021, 13, 5477 verter structure to provide a higher output voltage from low input sources by2 of varying 19 the duty cycle of the pulse width modulation (PWM) [5]. At high voltage/frequency, the con- verter generates a high voltage spike at the power switch and high electromagnetic inter- structure to provide a higher output voltage from low input sources by varying the duty ference increases the switching loss and the loss due to the passive element. A significant cycle of the pulse width modulation (PWM) [5]. At high voltage/frequency, the converter issue generateswith the a boost high voltage converter spike atis thethat power when switch considering and high electromagnetic a low input voltage interference source, it is difficultincreases to obtain the switching a high lossvoltage and the conversion loss due to theratio. passive To overcome element. A significantthis problem, issue the gain conversionwith the ratio boost is converter modified is that to whenmaximize considering the gain a low voltage input voltage using source, several it is difficulttechniques such as interleavedto obtain a positive/negative high voltage conversion coupling; ratio. To cascading, overcome this n-stage problem, cascading, the gain conversion or integrated cas- ratio is modified to maximize the gain voltage using several techniques such as interleaved cading;positive/negative and using multilevel coupling; cells cascading, and switch n-stage capacitors cascading, or [6–17]. integrated The cascading; overall family and of high step-upusing converters multilevel is cells depicted and switch in Figure capacitors 1. [Isolated6–17]. The DC/DC overall familyconverter of high topologies step-up that in- cludeconverters the flyback is depicted and forward in Figure converters1. Isolated are DC/DC considered converter more topologies suitable that for include low-voltage/- powerthe applications flyback and forward because converters these areconverters considered on morely have suitable a forsingle low-voltage/-power switch that results in applications because these converters only have a single switch that results in lower cost lowerand cost significantly and significantly lower circuit lower losses circuit during losses operation. during High-voltage operation. step-up High-voltage techniques step-up techniquesrequire require high-frequency high-frequency transformers. transformers. Family High Step-up Converter [5-17] [19-38] Non-Isolated Isolated Interleaved Technique [6-7] [19-30] [22-23,31-38] Push_Pull Source Coupled Inductor Technique [8-9] Topology Cascade and n-state Technique [10-11] Flyback Topology [19-20] [22-23,31-33,38] [34-37] Switched Capacitor Technique [12-13] Flyback-forword Topology [21] Voltage Fed Current Fed Inductor and Switched Capacitor Technique [14-15] Push-Pull Topology [22-23] Topology and Techniques Topology Three-level Technique [16-17] Class-E Topology [24] Modes Half-Bridge Topology [27-28] ZVS ZCS ZVCS PWM and Resonant Techniques andPWM Resonant Full-Bridge Topology [29-30] [31-32] [35-38] [33-34] Figure 1. FigureFamily 1. ofFamily high of step-up high step-up converters converters and and the the propos proposeded high high step-up step-up push–pull push–pull resonant resonant converter. converter. Asymmetric pattern waveforms have disadvantages such as flux saturation and Asymmetricvoltage/power pattern issues on waveforms the primary have side of disadvan the high-frequencytages such transformer. as flux saturation However, and volt- age/powerthe leakage issues inductance on the atprimary the primary side side of of th thee transformerhigh-frequency can place transformer. high-voltage stressHowever, the leakageon theinductance power switch at the during primary the turn-on side andof the turn-off transformer states [18– can23]. Aplace Class-E high-voltage inverter is a stress on the powertopology switch with the during advantages the turn-on of using a and single turn-o switch,ff a states simple gate[18–23]. driving A circuit, Class-E and inverter all is a its parameters can be calculated. However, the high voltage across the power switch has a topologylimitation with as the it is advantages approximately of three using ranges a single higher switch, than that a of simple the input gate voltage driving [24–26 circuit,]. and all itsTherefore, parameters two switchcan be converters calculated. among However, half-bridge, the push–pull, high voltage and Class-D
Load more

Recommended publications
  • Three-Dimensional Integrated Circuit Design: EDA, Design And
    Integrated Circuits and Systems Series Editor Anantha Chandrakasan, Massachusetts Institute of Technology Cambridge, Massachusetts For other titles published in this series, go to http://www.springer.com/series/7236 Yuan Xie · Jason Cong · Sachin Sapatnekar Editors Three-Dimensional Integrated Circuit Design EDA, Design and Microarchitectures 123 Editors Yuan Xie Jason Cong Department of Computer Science and Department of Computer Science Engineering University of California, Los Angeles Pennsylvania State University [email protected] [email protected] Sachin Sapatnekar Department of Electrical and Computer Engineering University of Minnesota [email protected] ISBN 978-1-4419-0783-7 e-ISBN 978-1-4419-0784-4 DOI 10.1007/978-1-4419-0784-4 Springer New York Dordrecht Heidelberg London Library of Congress Control Number: 2009939282 © Springer Science+Business Media, LLC 2010 All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights. Printed on acid-free paper Springer is part of Springer Science+Business Media (www.springer.com) Foreword We live in a time of great change.
    [Show full text]
  • Negative Capacitance in a Ferroelectric Capacitor
    Negative Capacitance in a Ferroelectric Capacitor Asif Islam Khan1, Korok Chatterjee1, Brian Wang1, Steven Drapcho2, Long You1, Claudy Serrao1, Saidur Rahman Bakaul1, Ramamoorthy Ramesh2,3,4, Sayeef Salahuddin1,4* 1 Dept. of Electrical Engineering and Computer Sciences, University of California, Berkeley 2 Dept. of Physics, University of California, Berkeley 3 Dept. of Material Science and Engineering, University of California, Berkeley 4 Material Science Division, Lawrence Berkeley National Laboratory, Berkeley, *To whom correspondence should be addressed; E-mail: [email protected] The Boltzmann distribution of electrons poses a fundamental barrier to lowering energy dissipation in conventional electronics, often termed as Boltzmann Tyranny1-5. Negative capacitance in ferroelectric materials, which stems from the stored energy of phase transition, could provide a solution, but a direct measurement of negative capacitance has so far been elusive1-3. Here we report the observation of negative capacitance in a thin, epitaxial ferroelectric film. When a voltage pulse is applied, the voltage across the ferroelectric capacitor is found to be decreasing with time–in exactly the opposite direction to which voltage for a regular capacitor should change. Analysis of this ‘inductance’-like behavior from a capacitor presents an unprecedented insight into the intrinsic energy profile of the ferroelectric material and could pave the way for completely new applications. 1 Owing to the energy barrier that forms during phase transition and separates the two degenerate polarization states, a ferroelectric material could show negative differential capacitance while in non-equilibrium1-5. The state of negative capacitance is unstable, but just as a series resistance can stabilize the negative differential resistance of an Esaki diode, it is also possible to stabilize a ferroelectric in the negative differential capacitance state by placing a series dielectric capacitor 1-3.
    [Show full text]
  • Very High Frequency Integrated POL for Cpus
    Very High Frequency Integrated POL for CPUs Dongbin Hou Dissertation submitted to the Faculty of the Virginia Polytechnic Institute and State University in partial fulfillment of the requirements for the degree of DOCTOR OF PHILOSOPHY in Electrical Engineering Fred C. Lee, Chair Qiang Li Rolando Burgos Daniel J. Stilwell Dwight D. Viehland March 23rd, 2017 Blacksburg, Virginia Keywords: Point-of-load converter, integrated voltage regulator, very high frequency, 3D integration, ultra-low profile inductor, magnetic characterizations, core loss measurement © 2017, Dongbin Hou Dongbin Hou Very High Frequency Integrated POL for CPUs Dongbin Hou Abstract Point-of-load (POL) converters are used extensively in IT products. Every piece of the integrated circuit (IC) is powered by a point-of-load (POL) converter, where the proximity of the power supply to the load is very critical in terms of transient performance and efficiency. A compact POL converter with high power density is desired because of current trends toward reducing the size and increasing functionalities of all forms of IT products and portable electronics. To improve the power density, a 3D integrated POL module has been successfully demonstrated at the Center for Power Electronic Systems (CPES) at Virginia Tech. While some challenges still need to be addressed, this research begins by improving the 3D integrated POL module with a reduced DCR for higher efficiency, the vertical module design for a smaller footprint occupation, and the hybrid core structure for non-linear inductance control. Moreover, as an important category of the POL converter, the voltage regulator (VR) serves an important role in powering processors in today’s electronics.
    [Show full text]
  • RX200, RX100 Series Application Note Overview of CTSU Operation
    APPLICATION NOTE RX200, RX100 Series R01AN3824EU0100 Rev 1.00 Overview of CTSU operation May 10, 2017 Introduction This document gives an operational overview of the capacitive touch sensing unit (CTSU) associated with a variety of RX and Synergy MCUs, including functioning principals and waveforms describing its operation in mutual and self- capacitive modes. Target Device RX230, RX231, RX130, and RX113. Contents 1. The components of capacitive touch ............................................................................. 2 2. Generation of the Electrostatic Field ............................................................................. 2 2.1 Overview of Parasitic capacitance ............................................................................................ 3 3. CTSU Capacitance Estimation ........................................................................................ 4 3.1 Measuring current via the Self-Capacitance Method .............................................................. 4 3.2 Measuring current via the Mutual-Capacitance Method ......................................................... 6 3.2.1 Simulation of the currents in Mutual Mode ........................................................................ 8 3.3 Turning the current to a digital measurement ......................................................................... 9 R01AN3824EU0100 Rev 1.00 Page 1 of 11 May 10, 2017 RX200, RX100 Series Overview of CTSU operation 1. The components of capacitive touch Renesas’ capacitive touch solution
    [Show full text]
  • Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models
    Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models Outline • Low-frequency small-signal equivalent circuit model • High-frequency small-signal equivalent circuit model Reading Assignment: Howe and Sodini; Chapter 4, Sections 4.5-4.6 Announcements: 1.Quiz#1: March 14, 7:30-9:30PM, Walker Memorial; covers Lectures #1-9; open book; must have calculator • No Recitation on Wednesday, March 14: instructors or TA’s available in their offices during recitation times 6.012 Spring 2007 Lecture 10 1 Large Signal Model for NMOS Transistor Regimes of operation: VDSsat=VGS-VT ID linear saturation ID V DS VGS V GS VBS VGS=VT 0 0 cutoff VDS • Cut-off I D = 0 • Linear / Triode: W V I = µ C ⎡ V − DS − V ⎤ • V D L n ox⎣ GS 2 T ⎦ DS • Saturation W 2 I = I = µ C []V − V •[1 + λV ] D Dsat 2L n ox GS T DS Effect of back bias VT(VBS ) = VTo + γ [ −2φp − VBS −−2φp ] 6.012 Spring 2007 Lecture 10 2 Small-signal device modeling In many applications, we are only interested in the response of the device to a small-signal applied on top of a bias. ID+id + v - ds + VDS v + v gs - - bs VGS VBS Key Points: • Small-signal is small – ⇒ response of non-linear components becomes linear • Since response is linear, lots of linear circuit techniques such as superposition can be used to determine the circuit response. • Notation: iD = ID + id ---Total = DC + Small Signal 6.012 Spring 2007 Lecture 10 3 Mathematically: iD(VGS, VDS , VBS; vgs, vds , vbs ) ≈ ID()VGS , VDS ,VBS + id (vgs, vds, vbs ) With id linear on small-signal drives: id = gmvgs + govds + gmbvbs Define: gm ≡ transconductance [S] go ≡ output or drain conductance [S] gmb ≡ backgate transconductance [S] Approach to computing gm, go, and gmb.
    [Show full text]
  • Lnt Room 36-412
    ~n;A r lrr^-> , ;-rl _ L N T ROOM 36-412 ,~' t nl S i WITH r S E FEUN CA TESI i r 4 > i o ) Urlt..... .. i 6 I tv J:sos? ', f5a 11,!ls.tr''j'6 8^,t~~~ 0t-,,' -~~~nr w AAPLIFIERS WITI-`PRSAIBED FREQUENCY CHARACTERISTICS AND ARBITRARY BANDWIDTH JOHN G. LINVILL (Qh) copor TECHNICAL REPORT NO. 163 JULY 7, 1950 RESEARCH LABORATORY OF ELECTRONICS MASSACHUSETTS INSTITUTE OF TECHNOLOGY CAMBRIDGE, MASSACHUSETTS t The research reported in this document was made possible through support extended the Massachusetts Institute of Tech- nology, Research Laboratory of Electronics, jointly by the Army Signal Corps, the Navy Department (Office of Naval Research) and the Air Force (Air Materiel Command), under Signal Corps Contract No. W36-039-sc-32037, Project No. 102B; Department of the Army Project No. 3-99-10-022. This report is based on a thesis in the Department of Electrical Engineering, M.I.T. I _ _ I _ __ _ MASSACHUSETTS INSTITUTE OF TECHNOLOGY RESEARCH LABORATORY OF ELECTRONICS Technical Report No. 163 July 7, 1950 AMPLIFIERS WITH PRESCRIBED FREQUENCY CHARACTERISTICS AND ARBITRARY BANDWIDTH John G. Linvill Abstract The amplifier chain, a cascade connection of amplifier tubes connected by two- terminal or two-terminal-pair interstages, is the basic component of the amplifiers designed. Shunt capacitance in the interstages imposes a limit on the amplification per stage over a prescribed band of frequencies. The limit of amplification per stage is inversely proportional to the bandwidth. The method of design of amplifier chains pre- sented leads to simple interstages which are economically close to the maximum in performance for the shunt capacitance present.
    [Show full text]
  • Analysis of Low Voltage Regulator Efficiency Based
    ANALYSIS OF LOW VOLTAGE REGULATOR EFFICIENCY BASED ON FERRITE INDUCTOR by MRIDULA KOTHAKONDA A THESIS Submitted in partial fulfillment of the requirements for the degree of Master of Science in the Department of Electrical and Computer Engineering in the Graduate School of The University of Alabama TUSCALOOSA, ALABAMA 2010 Copyright Mridula Kothakonda 2010 ALL RIGHTS RESERVED ABSTRACT Low voltage regulator based on ferrite inductor, using single- and two-phase topologies, were designed and simulated in MATLAB. Simulated values of output voltage and current were used to evaluate the buck converter (i.e., low voltage regulator) for power efficiency and percentage ripple reduction at frequencies between 1 and 10 MHz with variable loads from 0.024 to 4 Ω. The parameters, such as inductance of 20 nH, quality factor of 15 of fabricated ferrite inductor and DC resistance (DCR) of 8.3 mΩ, were used for efficiency analysis of the converter. High current around 40 A was achieved by the converter at low load values. Low output voltage in the range of 0.8-1.2 V was achieved. The simulated results for the single- and two- phase converter were compared for maximum efficiency and lowest ripple in output voltage and current. The maximum efficiency of 97 % with load of 0.33 Ω and the lowest ripple current of about 2.3 mA were estimated for the two-phase converter at 10 MHz. In summary, the two- phase converter showed higher efficiency and lower ripple voltage and current than those of the single-phase converter. In addition, the efficiency of single- and two-phase converters based on ferrite inductor was compared to single- and two-phase converters based on air-core inductor.
    [Show full text]
  • Parasitic Oscillation and Ringing of Power Mosfets Application Note
    Parasitic Oscillation and Ringing of Power MOSFETs Application Note Parasitic Oscillation and Ringing of Power MOSFETs Description This document describes the causes of and solutions for parasitic oscillation and ringing of power MOSFETs. © 2017 - 2018 1 2018-07-26 Toshiba Electronic Devices & Storage Corporation Parasitic Oscillation and Ringing of Power MOSFETs Application Note Table of Contents Description ............................................................................................................................................ 1 Table of Contents ................................................................................................................................. 2 1. Parasitic oscillation and ringing of a standalone MOSFET .......................................................... 3 2. Forming of an oscillation network ....................................................................................................... 3 2.1. Oscillation phenomenon ..................................................................................................................... 3 2.1.1. Feedback circuit (positive and negative feedback) ......................................................................... 4 2.1.2. Conditions for oscillation ...................................................................................................................... 5 2.2. MOSFET oscillation .............................................................................................................................. 5 2.2.1.
    [Show full text]
  • The MOS Tetrode Transistor Is Studied in This Project
    AN ABSTRACT OF THE THESIS OF Thawee Limvorapun for the Master of Science (Name) (Degree) in Electrical and Electronics Engineering (Major) 4; -- 7 -- presented on . (Date) Title: THE MOS TETROD.° mr""TcTcm"" Redacted for Privacy Abstract approved: James C. Lodriey The MOS tetrode transistor is studied in this project. This device is ideally suited for high frequency and switching application. In effect it is the solid state analogy of a multigrid vacuum tube performing a very useful multigrid function. A new structure is developed for p-channel 10 ohm-cm. silicon substrate of (111) crystal orientation. This structure consists of an aluminum con- trol gate G1 buried in the pyrolytic SiO2, or E-gun evapo- ration SiO with thermal oxide for the control gate in- 2' sulator. An offset gate G2 produces another channel L2 and causes a longer pinchoff region in the device. The drain breakdown can be maximized so as to approach bulk breakdown as the result of the redistribution of the surfacefield. is very low, ap- The Miller feedback capacitance CGl-D proaching values similar to those of the vacuum pentodes. This paper describes the design, artwork, pyrolytic SiO and E-gun evaporation SiO process. The V-I 2 2 characteristics, dynamic drain resistance, capacitance, small signal equivalent circuit and large signal limitation, and drain breakdown voltage are also discussed. THE MOS TETRODE TRANSISTOR by Thawee Limvorapun A THESIS submitted to Oregon State University in partial fulfillment of the requirements for the degree of Master of Science June 1973 APPROVED: Redacted for Privacy Associa e rofessor of Electrical andEleC-E-Anics Engineering in charge of major Redacted for Privacy Head of Department of Electrical and Electronics Engineering Redacted for Privacy Dean of Graduate School Date thesis is presented 6- 7- 7 2 Typed by Erma McClanathan for Thawee Limvorapun ACKNOWLEDGMENTS I wish to express my sincere appreciation to my advisor, Professor James C.
    [Show full text]
  • Design, Fabrication, and Characterization of Three‑Dimensional Embedded Capacitor in Through‑Silicon Via
    This document is downloaded from DR‑NTU (https://dr.ntu.edu.sg) Nanyang Technological University, Singapore. Design, fabrication, and characterization of three‑dimensional embedded capacitor in through‑silicon via Lin, Ye 2019 Lin, Y. (2019). Design, fabrication, and characterization of three‑dimensional embedded capacitor in through‑silicon via. Doctoral thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/102666 https://doi.org/10.32657/10220/48586 Downloaded on 28 Sep 2021 02:52:36 SGT ( O n th e S p ine) DESIGN, FA BRICATION, AND CHARACTERIZATION OF 3 DESIGN, FABRICATION, AND CHARACTERIZATION OF THREE-DIMENSIONAL EMBEDDED CAPACITOR IN THROUGH-SILICON VIA - D EMBEDDED CAPACITOR IN TSV LIN YE LIN YE SCHOOL OF ELECTRICAL AND ELECTRONIC ENGINEERING 2019 2019 DESIGN, FABRICATION, AND CHARACTERIZATION OF THREE-DIMENSIONAL EMBEDDED CAPACITOR IN THROUGH-SILICON VIA LIN YE (B. Eng., Nanyang Technological University) SCHOOL OF ELECTRICAL AND ELECTRONIC ENGINEERING A thesis submitted to the Nanyang Technological University in partial fulfillment of the requirement for the degree of Doctor of Philosophy 2019 Statement of Originality I hereby certify that the work embodied in this thesis is the result of original research, is free of plagiarised materials, and has not been submitted for a higher degree to any other University or Institution. 28 May 2019 Date Lin Ye Supervisor Declaration Statement I have reviewed the content and presentation style of this thesis and declare it is free of plagiarism and of sufficient grammatical clarity to be examined. To the best of my knowledge, the research and writing are those of the candidate except as acknowledged in the Author Attribution Statement.
    [Show full text]
  • High Frequency Passive Components
    EECS 142 Laboratory #1 High Frequency Passive Components Prof. A. M. Niknejad and Dr. Joel Dunsmore University of California Berkeley, CA 94720 February 11, 2013 1 1 Introduction Passive components play an important role in RF and microwave circuits. For instance, inductors are commonly employed to tune out the capacitance of transistors by forming resonant circuits. Inductors and capacitors together are used to build filters and impedance matching circuits. In communication circuits, filtering and matching are important functions for attenuating unwanted signals while maximizing the gain of desired frequencies. Unfortu- nately, there are no ideal inductors, capacitors, or resistors, and the unwanted characteristics of these components are called parasitics. In this laboratory, you will learn about the high frequency parasitics associated with passive components. These parasitics add loss and limit the upper frequency range over which the components function properly. 2 PCB Manufacturing All circuits will be fabricated using a simple two-layer printed circuit board (PCB). The PCB consists of a low-cost dielectric material, usually FR4 (r = 4:4), with a thickness of 62 mils1, and two layers of Cu metal layer. The copper layers are plated with solder, which doesn't oxidize and which melts at low temperature. The metal layers have a thickness of 34 µm. Normally you would pattern the metal layers to produce your circuit but in the interest of time, the boards have been prefabricated to take on a standard form. The backside of the board is a solid ground plane. Connections to ground must travel through a plated-through \via" to reach the backside.
    [Show full text]
  • Effect of Parasitic Capacitance in Op Amp Circuits (Rev. A)
    Application Report SLOA013A - September 2000 Effect of Parasitic Capacitance in Op Amp Circuits James Karki Mixed Signal Products ABSTRACT Parasitic capacitors are formed during normal operational amplifier circuit construction. Operational amplifier design guidelines usually specify connecting a small 20-pF to 100-pF capacitor between the output and the negative input, and isolating capacitive loads with a small, 20-Ω to 100-Ω resistor. This application report analyzes the effects of capacitance present at the input and output pins of an operational amplifier, and suggests means for computing appropriate values for specific applications. The inverting and noninverting amplifier configurations are used for demonstration purposes. Other circuit topologies can be analyzed in a similar manner. Contents 1 Introduction . 3 2 Basic One-Pole Operational Amplifier Model. 3 3 Basic Circuits and Analysis. 4 3.1 Gain Analysis . 5 3.1.1 Stability Analysis. 6 4 Capacitance at the Inverting Input. 7 4.1 Gain Analysis With Cn. 7 4.1.1 Stability Analysis With Cn. 10 4.1.2 Compensating for the Effects of Cn. 11 5 Capacitance at the Noninverting Input. 14 5.1 Gain Analysis With Cp. 14 5.2 Stability Analysis With Cp. 15 5.3 Compensating for the Effects of Cp. 15 6 Output Resistance and Capacitance. 16 6.1 Gain Analysis With Ro and Co. 16 6.2 Stability Analysis With Ro and Co. 18 6.3 Compensation for Ro and Co. 19 7 Summary . 24 8 References . 25 List of Figures 1 Basic Dominant-Pole Operational Amplifier Model. 4 2 Amplifier Circuits Constructed With Negative Feedback.
    [Show full text]