The Vacuum Tube Distributed Amplifier
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Design of a Low Noise Distributed Amplifier with Adjustable Gain Control in 0.15 M Gaas PHEMT
Vol. 33, No. 3 Journal of Semiconductors March 2012 Design of a low noise distributed amplifier with adjustable gain control in 0.15 m GaAs PHEMT Zhang Ying(张瑛), Wang Zhigong(王志功), Xu Jian(徐建), and Luo Yin(罗寅) Institute of RF- & OE-ICs, Southeast University, Nanjing 210096, China Abstract: A low noise distributed amplifier consisting of 9 gain cells is presented. The chip is fabricated with 0.15-m GaAs pseudomorphic high electron mobility transistor (PHEMT) technology from Win Semiconductor of Taiwan. A special optional gate bias technique is introduced to allow an adjustable gain control range of 10 dB. A novel cascode structure is adopted to extend the output voltage and bandwidth. The measurement results show that the amplifier gives an average gain of 15 dB with a gain flatness of 1 dB in the 2–20 GHz band. The noise figure is between 2 and 4.1 dB during the band from 2 to 20 GHz. The amplifier˙ also provides 13.8 dBm of output power at a 1 dB gain compression point and 10.5 dBm of input third order intercept point (IIP3), which demonstrates the excellent performance of linearity. The power consumption is 300 mW with a supply of 5 V, and the chip area is 2.36 1.01 mm2. Key words: distributed amplifiers; low noise; adjustable gain control; GaAs PHEMT DOI: 10.1088/1674-4926/33/3/035003 EEACC: 2570 1. Introduction structure is introduced to extend the output voltage and band- width. A special optional gate bias technique is used to allow With the rapid development of wireless and optical com- an adjustable gain control range of 10 dB. -
Three-Dimensional Integrated Circuit Design: EDA, Design And
Integrated Circuits and Systems Series Editor Anantha Chandrakasan, Massachusetts Institute of Technology Cambridge, Massachusetts For other titles published in this series, go to http://www.springer.com/series/7236 Yuan Xie · Jason Cong · Sachin Sapatnekar Editors Three-Dimensional Integrated Circuit Design EDA, Design and Microarchitectures 123 Editors Yuan Xie Jason Cong Department of Computer Science and Department of Computer Science Engineering University of California, Los Angeles Pennsylvania State University [email protected] [email protected] Sachin Sapatnekar Department of Electrical and Computer Engineering University of Minnesota [email protected] ISBN 978-1-4419-0783-7 e-ISBN 978-1-4419-0784-4 DOI 10.1007/978-1-4419-0784-4 Springer New York Dordrecht Heidelberg London Library of Congress Control Number: 2009939282 © Springer Science+Business Media, LLC 2010 All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights. Printed on acid-free paper Springer is part of Springer Science+Business Media (www.springer.com) Foreword We live in a time of great change. -
Negative Capacitance in a Ferroelectric Capacitor
Negative Capacitance in a Ferroelectric Capacitor Asif Islam Khan1, Korok Chatterjee1, Brian Wang1, Steven Drapcho2, Long You1, Claudy Serrao1, Saidur Rahman Bakaul1, Ramamoorthy Ramesh2,3,4, Sayeef Salahuddin1,4* 1 Dept. of Electrical Engineering and Computer Sciences, University of California, Berkeley 2 Dept. of Physics, University of California, Berkeley 3 Dept. of Material Science and Engineering, University of California, Berkeley 4 Material Science Division, Lawrence Berkeley National Laboratory, Berkeley, *To whom correspondence should be addressed; E-mail: [email protected] The Boltzmann distribution of electrons poses a fundamental barrier to lowering energy dissipation in conventional electronics, often termed as Boltzmann Tyranny1-5. Negative capacitance in ferroelectric materials, which stems from the stored energy of phase transition, could provide a solution, but a direct measurement of negative capacitance has so far been elusive1-3. Here we report the observation of negative capacitance in a thin, epitaxial ferroelectric film. When a voltage pulse is applied, the voltage across the ferroelectric capacitor is found to be decreasing with time–in exactly the opposite direction to which voltage for a regular capacitor should change. Analysis of this ‘inductance’-like behavior from a capacitor presents an unprecedented insight into the intrinsic energy profile of the ferroelectric material and could pave the way for completely new applications. 1 Owing to the energy barrier that forms during phase transition and separates the two degenerate polarization states, a ferroelectric material could show negative differential capacitance while in non-equilibrium1-5. The state of negative capacitance is unstable, but just as a series resistance can stabilize the negative differential resistance of an Esaki diode, it is also possible to stabilize a ferroelectric in the negative differential capacitance state by placing a series dielectric capacitor 1-3. -
Distributed Integrated Circuits: Wideband Communications for the 21St Century by Ali Hajimiri
Distributed Integrated Circuits: Wideband Communications for the 21st Century by Ali Hajimiri lobal communications mitted per second (i.e., bit rate) G have rendered our world a determines the speed of a digital smaller, yet more interest- communications system. C.E. ing place, making it possi- Shannon, the founder of modern ble to exchange visions, ideas, information theory, proved that the goals, dreams—and PoKéMoN maximum achievable bit rate of a cards—across our small planet. digital communications system Modern communications systems, increases linearly with the available such as the internet and portable range of frequencies (i.e., channel wireless systems, have added new bandwidth) and logarithmically dimensions to an already complex with the signal-to-noise ratio. world. They make us aware of our Thus, three critical parameters, similarities and differences and give namely, bandwidth, signal power, us an opportunity to communicate and noise, are the most important with people we have never met parameters in determining the per- from places we have never been. formance of any given communica- The fusion of education with com- Ali Hajimiri tions system. munication is already bringing One of the more common about new levels of awareness, methods of increasing the band- accompanied by creative upheavals million) of reliable active (e.g., tran- width, and hence the bit rate, of in all aspects of modern life. sistors) and passive (e.g., intercon- any given system is to migrate to However, the ever-increasing nect) devices. Further, they are rela- higher operating frequencies. The demand for more connectivity tively inexpensive to incorporate maximum speed of operation in inevitably increases the complexity into mass-market products. -
Very High Frequency Integrated POL for Cpus
Very High Frequency Integrated POL for CPUs Dongbin Hou Dissertation submitted to the Faculty of the Virginia Polytechnic Institute and State University in partial fulfillment of the requirements for the degree of DOCTOR OF PHILOSOPHY in Electrical Engineering Fred C. Lee, Chair Qiang Li Rolando Burgos Daniel J. Stilwell Dwight D. Viehland March 23rd, 2017 Blacksburg, Virginia Keywords: Point-of-load converter, integrated voltage regulator, very high frequency, 3D integration, ultra-low profile inductor, magnetic characterizations, core loss measurement © 2017, Dongbin Hou Dongbin Hou Very High Frequency Integrated POL for CPUs Dongbin Hou Abstract Point-of-load (POL) converters are used extensively in IT products. Every piece of the integrated circuit (IC) is powered by a point-of-load (POL) converter, where the proximity of the power supply to the load is very critical in terms of transient performance and efficiency. A compact POL converter with high power density is desired because of current trends toward reducing the size and increasing functionalities of all forms of IT products and portable electronics. To improve the power density, a 3D integrated POL module has been successfully demonstrated at the Center for Power Electronic Systems (CPES) at Virginia Tech. While some challenges still need to be addressed, this research begins by improving the 3D integrated POL module with a reduced DCR for higher efficiency, the vertical module design for a smaller footprint occupation, and the hybrid core structure for non-linear inductance control. Moreover, as an important category of the POL converter, the voltage regulator (VR) serves an important role in powering processors in today’s electronics. -
Breaking Bandwidth Limit: a Review of Broadband Doherty Power Amplifier Design for 5G
1 Breaking Bandwidth Limit: A Review of Broadband Doherty Power Amplifier Design for 5G Gholamreza Nikandish, Member, IEEE, Robert Bogdan Staszewski, Fellow, IEEE, and Anding Zhu, Senior Member, IEEE I. INTRODUCTION [6]–[11]. However, there is no complete review on broadband HE next generation wireless network, 5G, is expected to design techniques for the DPA, an essential subject for 5G T provide ubiquitous connections to billions of devices as wireless transmitters. well as to unlock many new services with multi-Gigabit-per- In this paper, we present a comprehensive review and second data transmission. To meet ever increasing demands for critical discussion on bandwidth enhancement techniques for higher data rates and larger capacity, new modulation schemes the DPA proposed in the literature, in order to provide a have been developed and wider frequency bands, e.g., at mm- thorough understating of broadband design of DPA for high- wave, have been designated to 5G [1], [2]. Massive multi-input efficiency 5G wireless transmitters. The paper is organized multi-output (MIMO), that uses a large number of antennas at as follows. In Section II, we discuss the main bandwidth the transmitter and receiver, has been considered as one of the limitation factors. In Section III, we review various bandwidth key enabling technologies in 5G to improve data throughput enhancement techniques for the DPA, including modified load and spectrum efficiency [3]. These new application scenarios modulation networks, frequency response optimization, para- pose stringent requirements on the wireless transceiver front- sitic compensation, post-matching, distributed DPA, and dual- ends and call for special considerations at both circuit and input digital DPA. -
RX200, RX100 Series Application Note Overview of CTSU Operation
APPLICATION NOTE RX200, RX100 Series R01AN3824EU0100 Rev 1.00 Overview of CTSU operation May 10, 2017 Introduction This document gives an operational overview of the capacitive touch sensing unit (CTSU) associated with a variety of RX and Synergy MCUs, including functioning principals and waveforms describing its operation in mutual and self- capacitive modes. Target Device RX230, RX231, RX130, and RX113. Contents 1. The components of capacitive touch ............................................................................. 2 2. Generation of the Electrostatic Field ............................................................................. 2 2.1 Overview of Parasitic capacitance ............................................................................................ 3 3. CTSU Capacitance Estimation ........................................................................................ 4 3.1 Measuring current via the Self-Capacitance Method .............................................................. 4 3.2 Measuring current via the Mutual-Capacitance Method ......................................................... 6 3.2.1 Simulation of the currents in Mutual Mode ........................................................................ 8 3.3 Turning the current to a digital measurement ......................................................................... 9 R01AN3824EU0100 Rev 1.00 Page 1 of 11 May 10, 2017 RX200, RX100 Series Overview of CTSU operation 1. The components of capacitive touch Renesas’ capacitive touch solution -
Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models
Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models Outline • Low-frequency small-signal equivalent circuit model • High-frequency small-signal equivalent circuit model Reading Assignment: Howe and Sodini; Chapter 4, Sections 4.5-4.6 Announcements: 1.Quiz#1: March 14, 7:30-9:30PM, Walker Memorial; covers Lectures #1-9; open book; must have calculator • No Recitation on Wednesday, March 14: instructors or TA’s available in their offices during recitation times 6.012 Spring 2007 Lecture 10 1 Large Signal Model for NMOS Transistor Regimes of operation: VDSsat=VGS-VT ID linear saturation ID V DS VGS V GS VBS VGS=VT 0 0 cutoff VDS • Cut-off I D = 0 • Linear / Triode: W V I = µ C ⎡ V − DS − V ⎤ • V D L n ox⎣ GS 2 T ⎦ DS • Saturation W 2 I = I = µ C []V − V •[1 + λV ] D Dsat 2L n ox GS T DS Effect of back bias VT(VBS ) = VTo + γ [ −2φp − VBS −−2φp ] 6.012 Spring 2007 Lecture 10 2 Small-signal device modeling In many applications, we are only interested in the response of the device to a small-signal applied on top of a bias. ID+id + v - ds + VDS v + v gs - - bs VGS VBS Key Points: • Small-signal is small – ⇒ response of non-linear components becomes linear • Since response is linear, lots of linear circuit techniques such as superposition can be used to determine the circuit response. • Notation: iD = ID + id ---Total = DC + Small Signal 6.012 Spring 2007 Lecture 10 3 Mathematically: iD(VGS, VDS , VBS; vgs, vds , vbs ) ≈ ID()VGS , VDS ,VBS + id (vgs, vds, vbs ) With id linear on small-signal drives: id = gmvgs + govds + gmbvbs Define: gm ≡ transconductance [S] go ≡ output or drain conductance [S] gmb ≡ backgate transconductance [S] Approach to computing gm, go, and gmb. -
Analyzing the Effect of Parasitic Capacitance in a Full-Bridge Class-D Current Source Rectifier on a High Step-Up Push–Pull Multiresonant Converter
sustainability Article Analyzing the Effect of Parasitic Capacitance in a Full-Bridge Class-D Current Source Rectifier on a High Step-Up Push–Pull Multiresonant Converter Anusak Bilsalam 1,* , Chainarin Ekkaravarodome 2, Viboon Chunkag 3 and Phatiphat Thounthong 4 1 Department of Electrical Engineering Technology, College of Industrial Technology (CIT), King Mongkut’s University of Technology North Bangkok (KMUTNB), 1518 Pracharat 1 Rd., Wongsawang, Bang Sue, Bangkok 10800, Thailand 2 Advanced Power Electronics and Experiment Laboratory, Department of Instrumentation and Electronics Engineering, Faculty of Engineering, King Mongkut’s University of Technology North Bangkok (KMUTNB), 1518 Pracharat 1 Rd., Wongsawang, Bang Sue, Bangkok 10800, Thailand; [email protected] 3 Department Electrical and Computer Engineering, Faculty of Engineering, King Mongkut’s University of Technology North Bangkok (KMUTNB), 1518 Pracharat 1 Rd., Wongsawang, Bang Sue, Bangkok 10800, Thailand; [email protected] 4 Renewable Energy Research Centre, Department of Teacher Training in Electrical Engineering, Faculty of Technical Education, King Mongkut’s University of Technology North Bangkok (KMUTNB), 1518 Pracharat 1 Rd., Wongsawang, Bang Sue, Bangkok 10800, Thailand; [email protected] * Correspondence: [email protected] Abstract: This paper presents an analysis on the effect of a parasitic capacitance full-bridge class-D current source rectifier (FB-CDCSR) on a high step-up push–pull multiresonant converter (HSPPMRC). The proposed converter can provide high voltage for a 12 V battery using an isolated transformer Citation: Bilsalam, A.; DC Ekkaravarodome, C.; Chunkag, V.; and an FB-CDCSR. The main switches of the push–pull and diode full-bridge rectifier can be operated Thounthong, P. -
Lnt Room 36-412
~n;A r lrr^-> , ;-rl _ L N T ROOM 36-412 ,~' t nl S i WITH r S E FEUN CA TESI i r 4 > i o ) Urlt..... .. i 6 I tv J:sos? ', f5a 11,!ls.tr''j'6 8^,t~~~ 0t-,,' -~~~nr w AAPLIFIERS WITI-`PRSAIBED FREQUENCY CHARACTERISTICS AND ARBITRARY BANDWIDTH JOHN G. LINVILL (Qh) copor TECHNICAL REPORT NO. 163 JULY 7, 1950 RESEARCH LABORATORY OF ELECTRONICS MASSACHUSETTS INSTITUTE OF TECHNOLOGY CAMBRIDGE, MASSACHUSETTS t The research reported in this document was made possible through support extended the Massachusetts Institute of Tech- nology, Research Laboratory of Electronics, jointly by the Army Signal Corps, the Navy Department (Office of Naval Research) and the Air Force (Air Materiel Command), under Signal Corps Contract No. W36-039-sc-32037, Project No. 102B; Department of the Army Project No. 3-99-10-022. This report is based on a thesis in the Department of Electrical Engineering, M.I.T. I _ _ I _ __ _ MASSACHUSETTS INSTITUTE OF TECHNOLOGY RESEARCH LABORATORY OF ELECTRONICS Technical Report No. 163 July 7, 1950 AMPLIFIERS WITH PRESCRIBED FREQUENCY CHARACTERISTICS AND ARBITRARY BANDWIDTH John G. Linvill Abstract The amplifier chain, a cascade connection of amplifier tubes connected by two- terminal or two-terminal-pair interstages, is the basic component of the amplifiers designed. Shunt capacitance in the interstages imposes a limit on the amplification per stage over a prescribed band of frequencies. The limit of amplification per stage is inversely proportional to the bandwidth. The method of design of amplifier chains pre- sented leads to simple interstages which are economically close to the maximum in performance for the shunt capacitance present. -
Analysis of Low Voltage Regulator Efficiency Based
ANALYSIS OF LOW VOLTAGE REGULATOR EFFICIENCY BASED ON FERRITE INDUCTOR by MRIDULA KOTHAKONDA A THESIS Submitted in partial fulfillment of the requirements for the degree of Master of Science in the Department of Electrical and Computer Engineering in the Graduate School of The University of Alabama TUSCALOOSA, ALABAMA 2010 Copyright Mridula Kothakonda 2010 ALL RIGHTS RESERVED ABSTRACT Low voltage regulator based on ferrite inductor, using single- and two-phase topologies, were designed and simulated in MATLAB. Simulated values of output voltage and current were used to evaluate the buck converter (i.e., low voltage regulator) for power efficiency and percentage ripple reduction at frequencies between 1 and 10 MHz with variable loads from 0.024 to 4 Ω. The parameters, such as inductance of 20 nH, quality factor of 15 of fabricated ferrite inductor and DC resistance (DCR) of 8.3 mΩ, were used for efficiency analysis of the converter. High current around 40 A was achieved by the converter at low load values. Low output voltage in the range of 0.8-1.2 V was achieved. The simulated results for the single- and two- phase converter were compared for maximum efficiency and lowest ripple in output voltage and current. The maximum efficiency of 97 % with load of 0.33 Ω and the lowest ripple current of about 2.3 mA were estimated for the two-phase converter at 10 MHz. In summary, the two- phase converter showed higher efficiency and lower ripple voltage and current than those of the single-phase converter. In addition, the efficiency of single- and two-phase converters based on ferrite inductor was compared to single- and two-phase converters based on air-core inductor. -
Parasitic Oscillation and Ringing of Power Mosfets Application Note
Parasitic Oscillation and Ringing of Power MOSFETs Application Note Parasitic Oscillation and Ringing of Power MOSFETs Description This document describes the causes of and solutions for parasitic oscillation and ringing of power MOSFETs. © 2017 - 2018 1 2018-07-26 Toshiba Electronic Devices & Storage Corporation Parasitic Oscillation and Ringing of Power MOSFETs Application Note Table of Contents Description ............................................................................................................................................ 1 Table of Contents ................................................................................................................................. 2 1. Parasitic oscillation and ringing of a standalone MOSFET .......................................................... 3 2. Forming of an oscillation network ....................................................................................................... 3 2.1. Oscillation phenomenon ..................................................................................................................... 3 2.1.1. Feedback circuit (positive and negative feedback) ......................................................................... 4 2.1.2. Conditions for oscillation ...................................................................................................................... 5 2.2. MOSFET oscillation .............................................................................................................................. 5 2.2.1.