Circuits, Devices, Networks, and Microelectronics
CHAPTER 12. TRANSISTOR PARASITICS: Time constants and frequency domain analysis
12.1 SINGLE TIME-CONSTANT ANALYSIS
The speed of a circuit is governed by its time constants. For most electronic circuits these are due to capacitances since (1) capacitances are used for coupling signals into and/or out of the transistor and (2) transistor devices have parasitic capacitances. Coupling capacitances are on the order of F and parasitic capacitances are on the order of pF and fF, (depending on the type of transistors). Assuming resistance defaults of k the expectations should be
(coupling) = RC = 1k × 1F = 1msec → f in kHz (parasitic) = RC = 1k × 1pF = 1nsec → f in GHz
The default context is illustrated by figure 12.1-1. And the expectations are then a shortcut.
Figure 12.1-1. CS topology with coupling capacitances (default = F) and source resistance RZ.
Another shortcut is the approximation conversion between time constants and frequency
1 f 0.16 where = 1/ 2
And even though the radian frequency () is the analytical domain for poles and zeros the operational domain is always Herzian frequency.
Impulses will always relate to rise times and fall times and to overshoots and undershoots. The frequency domain will relate to the Bode magnitude plot as represented by figure 12.1-2.
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Figure 12.1-2. Bode plot response of a single stage subcircuit.
The Bode magnitude plot is characterized by (1) midband gain (|vL/vS|) and (2) upper and lower 3dB roll- off corners. The corners relate to poles, and poles are defined by RC time constants.
The lower frequency poles are usually due to the coupling capacitances (F) and the lower pole frequency corner may roughly be approximated by
p L p L1 p L2 p L3 ... (12.1-1)
where pL1, pL2, pL3, .. are (single time constant) low frequency poles. The higher pole frequency corner may be roughly approximated by
1 1 1 1 .. = H1 H 2 H 3 ... (12.1-2) pH pH1 pH 2 pH 3
Where pH1, pH2, pH3, .. are (single time constant) high frequency poles. Take note that it may be more convenient to use time constants rather than poles for the high-frequency assessments.
Be aware that these approximations are crude. In reality the circuit should be assessed by network analysis using complex admittances and impedances. But this sort of analysis is not one for back-of-the envelope assessments. Fortunately we have pspice or some other circuit simulation utility that will accomplish multi-node nodal analysis with considerable alacrity. And its post-processor will generate
Bode magnitude plots, Bode phase plots and even extract the fL and fH corner information.
Equations (12.1-1) and (12.1-2) are a means to make a rough assessment as well as determine which poles are dominant. The dominant poles are the ones that become targets when extending the reach of the circuit. Equation (12.1-1) shows that the highest of the low frequency poles is dominant and equation (12.1-2) shows us that the lowest of the high frequency poles is dominant.
The rest of the story relies on the assumption that the poles are separable. They are not. But for the sake of assessment they are treated as if they can be isolated as if each were dominant. And that assumption is
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sufficient to make practical use of the simplifying context of equations (12.1-1) and (12.1-2), whether for the benefit of a rough definition of the circuit performance characteristics or for identifying the constraints and redesigning for a greater reach.
12.2 LOW-FREQUENCY APPROXIMATIONS
Using the assumption that the poles are separable and that capacitances can be treated as separable the rest of the story is in the resistances. Each capacitance will have a resistance link through which it will charge and discharge.
And that is one of the reasons why the resistance of the input source must be included. It forms part of the resistance path for the input coupling capacitance.
If the source is from a previous stage then it is the output resistance of that stage. However if it is from a transducer (more common) then it must be ascertained from the specification of the transducer. A transducer is defined in terms of its short-circuit current (iSS) and its open-circuit (signal) voltage vS so that
RZ = vS/iSS (source transducer resistance) (12.2-1)
It then becomes part of the resistance that is ‘seen’ by the input capacitance. This context is represented by figure 12.2-1.
Figure 12.2-1. (Low frequency) pole for the input capacitance (C1).
And then the time constant is
L1 RZ Rin C1 (12.2-2)
for which pL1 = 1/L1. Since Rin can be determined by inspection the pole can also be determined by inspection, - or at least by no more than a couple of hiccups.
The time constant associated with the output is similar to that of the input. And it also includes the resistance RL which is external to the two-port subcircuit. It has been included before as a part of the
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signal load of the transistor. It may be a transducer for vibrating another medium. More likely RL is the input resistance to the next stage. Its context is shown by figure 12.2-2.
Figure 12.2-2. (Low frequency) pole for the output capacitance (C2).
The time constant associated with the output capacitance is
L2 Rout RL C 2 (12.2-2)
for which pL2 = 1/L2. Since Rout can be done by inspection, particularly in its rough form, this pole can also be done by inspection.
Keep in mind that approximations are rampant in the science and art of electronics, in particular in the evaluation of the frequency domain for which the analysis represented by the above equations will be superceded by simulation. But the step is necessary for the preliminary assessment and for making judgment calls on device sizing.
If a circuit includes a bypass capacitance as identified by topologies such as that shown by figure 12.1-1 (CS topology) it also fits into the same category as figure 12.2-1 and 12.2-2 in that the rest of its story is
L3 R5 || R4 RiE C3 (12.2-3)
and for which pL3 = 1/L3. The context of this capacitance is represented by figure 12.2-3, where it should be evident that the smaller resistances (R4 + RiE) will be dominant. If it is applied to the FET then the dominant resistance will be (R4 + RiS).
Figure 12.2-3. Low frequency pole for the bypass capacitance (C3).
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The small resistance (R4 + RiE) will not only dominate the approximations (the results will always be smaller than the smallest) they will also cause C3 to dominate the set of low frequency poles unless C3 is made considerably larger than the other capacitances.
Keep in mind that the pole is the reciprocal of the time constant and so the highest of the low also is associated with the smallest time constant. So if C3 is small and (R4 + RiE) is small courtesy of its circumstance, then the pole associated with C3 (bypass capacitance) will most likely be the dominant pole.
Consider the following example
EXAMPLE 12.2-1: For the CE topology shown and an input transducer with open circuit signal voltage vS = 5mV and short-circuit signal current iSS = 0.1 mA determine (a) source resistance RZ (b) transfer characteristics Rin, Rout and vL/vI, and (c) dominant low frequency pole and the approximate corner frequency fL. And (d) compare the midband gain and lower corner frequency to the result using pspice.
ANALYTICAL SOLUTIONS:
(a) RZ = vS/iSS = 5.0mV/0.1mA = 50 k
(b) For the source current shown
gm = 40 × I = 4.0mA/V.
By inspection RiB = 75k [= 100 × (1/4.0 + 0.5)]
Then (by inspection) Rin k ( = 150||75||75 )
vL 30 45 And by inspection Rout = 30 k (R3 ) and -24V/V vI 1 4 0.5 (and where | -24V/V| is approximately 28dB)
(c) The time constant for capacitance C1 is 1 = 0.2 × (50 + 30) = 16 ms → pL1 = .0625 kr/s
The time constant for capacitance C2 is 2 = 0.2 × (30 + 45) = 15 ms → pL2 = .0667 kr/s
1 RBS 1 150|| 75|| 50 RiE = = 0.5 k g m F 4 100
And so the time constant for capacitance C3 is 3 = 4.0 × (0.5+ 0.5) = 4 ms → pL3 = 0.25 kr/s *
Note that pL3 gets recognition and a star because it is the dominant pole.
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The low frequency corner pole is approximated by pL = (.0625 + .0667 + 0.25) = 0.38 kr/s
For which fL 0.16 × 0.38 = .061 kHZ = 61 Hz
PSPICE SOLUTIONS:
The circuit execution in pspice gives results as shown. The cursor coordinates indicate the midband gain |vL/vS| in dB and the low-frequency corner in Hz
The pspice assessment shows a |vL/vS| midband gain of 19.2 dB and a low frequency corner defined by
(19dB – 3dB = 16dB) of value fL = 47.0 Hz . The pspice value is the more accurate result. The analytical value is not inconsistent with that of the pspice corner and supplies more information about the dominant components within the circuit.
12.3 PARASITIC CAPACITANCES in TRANSISTORS
The simulation result for the previous example also shows that there is an upper-frequency roll-off at approximately 200kHz. Although this performance metric will not win any awards it does point to the rest of the story. Circuit speed has its limits, and they are vested in capacitances (and inductances) that are unseen, otherwise known as ‘parasitics’. Parasitic inductances are vested in interconnects and become part of the circuit picture in the UHF domain, in which case they will be part of a transmission line. Parasitic capacitances are mostly a matter of structures with junctions and layers (a.k.a transistor parasitics) and they are formulated in terms of RC time constants.
Although wiring and interconnects may contribute, the principal parasitic capacitances are those within the transistors. They all have structural layers and junctions. The MOSFET even looks like a capacitance and includes parasitic capacitances associated with the thin oxide layer as well as those of the source and drain junctions. Since the MOSFET is a four-terminal capacitance it is much more complex than can safely be resolved by STC analysis, so only the major contributions are broken out.
The BJT is an area structure with layers. The layers include pn junctions and pn junctions have capacitance of the form approximately defined by equation (9.2-4). For discrete transistors such the 2n3904, the layer area is sufficient to form capacitances on the order of pF. Figure 12.3-1 identifies the relevant information and the context in which the parasitic capacitances must be considered.
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Figure 12.3-1. BJT capacitance structure.
The fact that junction capacitances have voltage dependence means that they will require more overhead than a back-of-the-envelope calculation would consider. But even though the circuit simulation has the final word, it is still necessary to be able to do some back-of-the-envelope assessments in order to make decisions. The equation for BJT junction capacitance as employed by the circuit simulator is equation (9.2-4) with nomenclature that reflects the junction identified by figure 12.3-2, i.e.
MJE C BE C JE 1 VEB JE (12.3-1a)
MJC C BC C JC 1 VCB JC (12.3-1b) for which the subscripts relate to the respective junctions. Relative to the figure the BE junction is forward-biased to VBE 0.7Vand so (as an estimate) for analysis
CBE(rough) 2CJE (12.3-2a)
And the BC junction is reverse-biased to VBC -4V (typical) so that
CBC(rough) 0.5CJC (12.3-2b)
A visit to spice parameters for the 2n3906 (figure 12.3-2) confirms the context of (zero-bias) junction capacitances on the order of pF
Figure 12.3-2. BJT pspice device parameters (2n3904).
A context assessment using the 2n3904 parameters confirms the approximations (12.3-2a) and (12.3-2b).
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EXAMPLE 12.3-1: Evaluate equations (12.3-1a) and (12.3-1a) for the 2n3904 transistor with the assumption that VBE = 0.7V and VBC = 5.0V.
SOLUTION: For the pspice parameters given by figure 12.3-2
MJE 0.2593 C BE C JE 1 VEB JE C JE 1 (0.7) 0.75 = 2.085 CJE
MJC 0.3085 C BC C JC 1 VCB JC C Jc 1 (5.0) 0.75 = 0.53 CJC
The same context is true for the FET. The control node should be expected to have parasitic capacitances between itself and the adjacent nodes. For discrete devices such as the BJT and the JFET these parasitic capacitances will be due to junctions and will be on the order of pF as represented by figure 12.3-4.
Figure 12.3-4. Parasitic capacitances in the common types of transistors
Parasitic capacitances between adjacent nodes become seriously worse if the transistor circuit is being prototyped on a protoboard since the protoboard will contribute parasitic wiring capacitances between adjacent nodes that are also on the order of pF.
The BJT has a extra capacitance unlike that of its cousins, and this is illustrated by figure 12.3-5.
Figure 12.3-5. Charge carriers injected across the BE junction = diffusion charge effects.
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It is a fact of life that a forward-biased junction will inject a great deal of charge (diffusion charge) across a junction and into enemy territory. While the injected charge is subject to recombination with the opposite type of charge carriers it still represents a sizeable charge, and the dynamic removal of the charge injected across the BE junction is of the form
QF CD (12.3-3) VBE
CD is a diffusion capacitance. The forward charge QF is represented by figure 12.3-5 and is directly related to the forward current IF by the transit time = effective time it takes for the charge to transit the base layer. It is a parameter rather than an actual time interval and is represented by parameter TF in the listing for the 2n3904 BJT given by figure 12.3-2. The relationship is
I F QF F (12.3-4)
This identification between QF and IF makes analysis fairly simple since
QF I F CD I F F F g m F (12.3-5) VBE VBE VBE
This capacitance belongs to the BE junction since it is the one that is forward biased. So the capacitance due to the base-emitter junction takes on the name C, with
C CBE CD CBE g m F (12.3-6a)
No such situation exists for the BC junction and so
C CBC (12.3-6b)
Consider the following example
EXAMPLE 12.3-1: For the CE topology shown and a 2n3904 transistor determine the parasitic capacitances
C and C of the BJT.
SOLUTION:
For the parameter set for the 2n3904 (figure 12.3-2)
CJE = 4.49 pF
CJC = 3.64 pF
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F = 300ps = 0.3ns
For the source current shown gm = 40 × I = 4.0mA/V.
Using the approximations suggested by equations (12.3-2a) and (12.3-2b), then
CBE = 2 × 4.49 pF 9.0pF CBC = 3.64 pF /2 1.8 pF
So C CBE g m F 9.0 4.0 0.3 ** = 10.2pF
** (Note shortcut: Put F in ns and gm is in mA/V and the result is in pF)
C CBC = 1.8 pF
Similar parasitics for the JFET are represented by figure 12.3-6a and reflect a ‘partitioning’ of the JFET.
The partitioning is not elected but shows up in the parameter list as different value for CGS and CGD as represented by the pspice parameter list for the 2n3918 shown by figure 12.3-6b.
Figure 12.6-6. Parasitics for the JFET. (a) channel partitioning (b) 2n3918 parameter set.
For a discrete device such as that represented, parasitic capacitance values for the JFET will be on the order of pF. CGD and CGS are also defined in terms of junction bias character of the same form as represented by (junction) equation (9.2-4) and consequently parasitic capacitances CGS and CGD for the JFET are voltage dependent and are of the form
M CGK CGK 0 1 VR B (12.3-7)
Equation (12.3-7) is the form that will be used by the circuit simulation utility. Otherwise, and in accordance with previous approximation for junction capacitances, the parameter list values for CGS and
CGD can be reduced by approximately a factor of two for back-of-the-envelope calculations.
As might be expected the MOSFET is the transistor that reflects the most parasitic capacitances. The parasitics of the MOSFET are represented by figure 12.3-4(c) and by figure 12.3-6. As indicated by these figures it not only has gate capacitances CGS and CGD, it also has junction capacitances CJS and CJD. Whenever a design is invoked in pspice these parasitics are invoked by means of device and junction
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sizing. They are not automatic except for VLSI layout design. They are not insignificant, so if the user neglects to include them, the simulation results will be seriously compromised.
Figure 12.3-6. Parasitic capacitances contained in the MOSFET structure
Figure 12.3-7. MOSFET parameters (BSIM3V4), TSMC 0.35 micron T83U with capacitance parameters marked.
The gate capacitance parameters are defined by the thin oxide and by the overlap of gate over the junction. While this overlap is relatively small it can be a significant factor in a structure such as the MOSFET for which fF are typical. It is represented by the parameters CGDO and CGSO in the BSIM3V4 parameter listing shown by figure 12.3-7. The gate capacitances are
2 C C W L CGSO W (12.3-8a) GS 3 OX
and CGD = CGDO × W (12.3-8b)
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The first term in the equation for CGS is the gate capacitance due to inversion layer charge under the gate which is modeled as if it has triangular distribution density (and is the reason for the factor of 2/3.)
The rest of the parasitic capacitances relate to the junction capacitances formed by the source and darin implants. They are defined both by area and by sidewalls of the implant as represented by the inset to figure 12.3-6. The BSIM3V4 parameters that serve as coefficients to these contributions are CJ and CJSW. And they contribute to the junction capacitance as a sum of terms. For the drain junction
CJD = CJ × AD + CJSW × PD (12.3-9)
where AD = area of the drain junction and PD = perimeter of the drain junction. Specifically
AD = W × LD (12.3-10a)
PD = 2 × (W + L) (12.3-10b)
where LD = drain extension length (also shown by figure 12.3-6). As a part of the technology assessment these capacitances may be roughly calculated by a hand analysis. But otherwise they are also subject to the same junction equation (9.2-4) and more explicitly defined by their junction context as
MJ C D C JD 1 VR B (12.3-11) with specific parameters for each junction type (sidewall and area). The user needs to acknowledge the nature of these contributions but should obligingly give the simulation software the lead in detailing.
A like set of equations exist for the source, with the subscripts changed accordingly.
Analysis is typically performed as a technology assessment, as represented by example 12.3-2.
EXAMPLE 12.3-2: For an nMOS device and the T83U technology parameters (figure 12.3-7) evaluate the parasitic capacitances for the transistor assuming W/L = 2.5m/0.7m and drain-source extensions LD
= LS = 1.2m.
2 SOLUTION: TOX = 7.7nm, then COX = .0345/.0077 = 4.5fF/m
2 2 And then CGS = C W L 4.5 2.5 0.7 = 5.25fF 3 OX 3
To which must be added CG(overlap) using CGSO = CGDO = 3.18 × 10-10 F/m
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Which gives CGD = CGDO × W = 3.18 × 10-10 F/m × (1015fF/F)/(106m/m) × 2.5m
= 3.18 × 0.1 × 2.5 * = 0.8 fF
*Take note of the shortcut. After all of the dust clears with the units conversion and the 10-10, all that is left is the factor 0.1. So this analysis can be done by inspection. The gate capacitances are then
CGS = 5.25 fF + 0.8fF = 6.05 fF
CGD = = 0.8 fF
Similar units conversion shortcuts are available with the junction capacitances for the source and drain junctions. The term for the area capacitance is
-4 2 15 6 2 CJD(area) = CJ AD = 9.32 × 10 F/m × (10 fF/F)/(10 m/m) × (2.5m × 1.2m) = 9.32 × 0.1 × (2.5 × 1.2) * = 2.8 fF
*Take note. Another shortcut. After all of the dust clears with the units conversion and the 10-4, all that is left is the factor 0.1. So this analysis can be done by inspection.
-10 15 6 CJD(perimeter) = CJSW PD = 2.81 × 10 F/m × (10 fF/F)/(10 m/m) × [2 × (2.5m + 1.2m)] = 2.81 × 0.1 × 2( 2.5 + 1.2) * = 2.08 fF
* (Once again) after the dust clears with the units conversion and the 10-10, all that is left is the factor 0.1. So this analysis can also be done by inspection.
And so the drain junction capacitance is CJD = CD(area) + CD(perimeter) = 2.9 + 2.08 = 5.0fF
(And is the same for CJS since the source and drain are the same dimensions.)
Example 12.3-2 shows that the technology assessment is straightforward and can be accomplished virtually by inspection if the units shortcuts are acknowledged and applied.
The rest of the story is then a matter of toggling the appropriate aspects of the circuit simulator to ensure that it includes the analysis. Activation of the capacitance terms requires an estimate of the drain (and source) extension lengths LS and LD, in figure 12.3-6 and as was done by example 12.3-2.
Each MOS transistor must have a set of citations to assure that the junction parasitics are invoked. For the pspice simulation utility the typical citation box looks like that of figure 12.3-8.
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Figure 12.3-8. Citation box for including and invoking the MOS junction capacitances in pspice. Take note of the parametric usage (pspice form) in designation of lengths and widths.
A revisit and labeling of the parasitic capacitances of the transistor is shown by figure 12.3-9
Figure 12.3-9. Parasitic capacitances in transistors, with identification.
12.4 HIGH FREQUENCY ANALYSIS
The parasitic capacitances are the ones that define the high frequency response. They represent a mix of sources, with the most emphatic ones associated with junctions and transistors.
The small-signal models for the BJT and FET, with capacitances, are represented by Figure 12.4-1.
Figure 12.4-1. Small signal models for the BJT and the FET.
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Since the transistor is a signal transfer device, anything between input and output points will be affected by voltage feedback, which will strongly change the apparent capacitance between nodes. The most emphatic voltage feedback effect is the one for which the transfer gain across the bridging component is a large negative, and is defined as Miller multiplication. It is represented by figure 12.4-2.
Figure 12.4-2. Miller multiplication effect and equivalence.
The Miller effect evaluates the transistor as a two-port network and acknowledges that a bridging admittance Y12 between any two ports can be resolved in terms of equivalent input and output admittances
Y11 and Y22, i.e.
i Y v v v 1 12 1 2 2 (12.4-1) Y11 Y12 1 v1 v1 v1
If the transfer ratio v2/v1 happens to be a large negative value (such as for the CE and CS topologies) then the input admittance is subject to regenerative feedback. Regenerative feedback has the effect of a multiplying factor. So if the bridging admittance is a capacitance this phenomenon multiplies the capacitance at node 1 by a gain factor as reflected by equation (12.4-2), i.e.
v 2 (12.4-2) C11 C12 1 v1
On the convenience side, the use of figure 12.4-2 reduces the small-signal equivalent topology to a more tractable form, as represented by that of the CE topology and the figure sequence from 12.4-3a to 12.4-3c.
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Figure 12.4-3a. CE configuration reflecting the presence of parasitic capacitances.
Figure 12.4-3b. CE configuration, small-signal equivalent, with capacitances.
Figure 12.4-3c. CE configuration, small-signal equivalent simplified by Miller effect usage.
The components represented by topology 12.4-3c are
v ' E (12.4-3) C C 1 vB v and ' C (12.4-4) C C 1 vB
' vE and = RiB (12.4-5) r r 1 vB
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v v and '' B C (12.4-6) C C 1 C 11 vC vB
The transfer gain between base (B) and emitter (E) is the same as that of the emitter-follower topology except that there is no load at the emitter node, and so
v g g E m m (12.4-7) vB g m g G4 g m G4
If (12.4-7) is applied to (12.4-5) a little fun algebra will confirm that r’ = RiB . The input/output transfer gain for the CE topology, designated in terms of that between base (B) and collector (C) is
v R || R R || R C 3 L 3 L (12.4-8) vB RiB 1 g m R4 which is the recognized transfer gain for the CE topology given by equation (10.6-7).
Example 12.4-1 will give a sense of the effect of the Miller multiplication.
EXAMPLE 12.4-1: Evaluate the CE circuit topology of Example 12.2-1 for the upper frequency corner. The transistor used in the circuit is the 2n3904.
SOLUTION: This is the same topology and BJT used by Example 12.3-1 for which it was determined that
C = 10.2pF and
C = 1.8 pF
And so the rest of the story is to evaluate the equivalent circuit of figure 12.4-2c. It clearly shows two poles. Both make use of
gm = 40 × I = 4mA/V
RiB = 100 × (1/4 + 0.5) 75 k
Figure E12.4-1a. Base node equivalence v R || R 30|| 45 For which C 3 L -24V /V vB 1 g m R4 1 4 0.5
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v g 4.0 2 and E m V/V vB g m G4 4.0 2.0 3
v 2 gives ' E = 3.4 pF C C 1 10.2 1 vB 3 v ' C = 45pF C C 1 1.8 1 24 vB
These are the equivalent capacitances at the base node and are in parallel as indicated by figure E11-4.1. The figure also indicate that the resistance that charges and discharges these capacitances will be
RN1 = RZ ||R1||R2||RiB = 50||150||75||75 = 18.75k and so the time constant is H1 = (C’ + C’) × RN1 = (45pF + 3.4 pF) × 18.75k = 908 ns
The other pole is defined by the collector node
v For which '' C 1.8 1 1/ 24 C C 11 vB 1.8pF
And it is charged and discharged by RN2 R3 ||RL
= 30||45 = 18 k Figure E12.4-1b. Collector node equivalence.
So its time constant is H2 = C” × RN2 = 1.8pF × 18k = 32.4 ns
Consequently the high-frequency time constant for the circuit, H = tH1 + H2 = 908 + 32.4 940ns
which corresponds to high frequency pole frequency corner pH = 1/940ns 1.06 Mr/s
or fH = 0.16 × pH = 0.16 × 1.06 170 kHz
Execution of the circuit in pspice gives the result shown by figure E12.4-3
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Figure E12.4-1c. Pspice simulation of the CE circuit.
The pspice assessment shows a |vL/vS| midband gain of 19dB and a low frequency corner defined by
(19dB – 3dB = 16dB) of value fH = 222.5 kHz . The pspice value is the more accurate result. And the two are consistent, but only the analytical one gives insight into what is taking place within the CE circuit topology. **The dominant pole is H1 since it is the largest time constant.
As a figure of merit, a transfer circuit is usually defined by its gain-bandwidth (GB) product. This value has particular merit in the use of feedback in electronics circuits and is approximately constant with respect to feedback.
GB = AV f H f L AV f H (12.4-9)
For Example 12.4-1 the GB product is |-24 V/V| × 170 kHz = 4.08 MHz
12.5 HIGH-FREQUENCY CIRCUIT TOPOLOGIES
Example 12.4-1 confirms that the single-transistor circuit topology has serious bandwidth (= fH) limitations. In order to extend the reach into RF applications it is necessary to go from 1-transistor to 2- transistor forms that accomplish the same signal transfer purpose but (1) reduce the Miller multiplication effect and (2) reduce the resistances in the charge-discharge path of the capacitance. If this is accomplished, the RC time constant will then be small since both R and C are small.
The topology of figure 12.5-1 is one such candidate. It is called the cascode configuration and consists of two stages. The first stage is a CE stage and the second stage is a common-base stage. As a consequence
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of adding more nodes the topology adds an extra high-frequency pole. But the resulting three time
constants are small, so the overall time constant is small, - and so the resulting fH is large.
Figure 12.5-1. Cascode configuration using BJTs. Note use of bipolar supply rails.
A realization of the circuit as two stages also indicates that the parasitic capacitances (shown) will still have the Miller multiplication effect, but at much reduced multiplication factors. The equivalent small-
signal circuit tells much of the story. Transistors Q1 and Q2 both carry the same current and consequently
have the same small signal parameters gm and r , assuming that they are both the same type transistor.
Figure 12.5-2. Cascode topology small-signal equivalent circuit including Miller effect equivalents.
Of particular interest is input resistance to the second stage. Since the second stage is a common-base topology then
Rin2 1 g m (12.5-1)
And that means that the transfer gain vC1/vB1 of the first stage is
v R || R R 1 g C1 3 L in2 m = -1 (12.5-2) vB1 1 g m R4 1 g m 1 g m
And that means that
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v ' C 2C C1 C 1 C 1 1 vB and v '' C 2C C 2 C 11 C 11 1 vB
And so much of the Miller multiplication effect is eliminated. And therefore the node capacitance at the
base node of Q1 (labeled as N1 in figure 12.5-1) is the sum
CN1 = 2C + C (12.5-3)
Furthermore, the capacitance at the collector of Q1 (which is also the emitter of Q2) labeled as node N2 in figure 12.5-1 will be
CN2 = 2C + C (12.5-4)
The capacitance at the collector of Q2, labeled as node N3 in figure 12.5-2 has no multiplication effects since the base is at GND. So it will be
CN3 = C (12.5-5)
The resistances at these nodes is evident from figure 12.5-2 and will be
RN1 = R1||R2||RZ||RiB = R1||R2||RZ ||r (12.5-6)
RN2 = Rin2 = 1/gm (12.5-7)
RN3 = R3||RL (12.5-8)
The gain of the transistor pair will be
vL vC1 vL = (-1) × (gmR3||RL) = -gmR3||RL (12.5-9) vI vb1 vE2
And it is worthwhile to undertake an example and assess the bandwidth fH and the GB figure of merit.
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EXAMPLE E12.5-1: Evaluate the cascode configuration shown assuming that both transistors are 2n3904 and that the input transducer is a 6mV, 0.1A photodetector. Compare results to pspice.
SOLUTION:
(a) First: find the resistance of the source transducer:
vS 6mV RZ = 60k iSS 0.1A (b) Find the small-signal characteristics of the BJT
gm = 40I = 20mA/V
F 100 r = 5k g m 20 Figure E12.5-1a. Cascode topology.
(c) Assuming the usual approximations for junctions and using the parameter listed by figure 12.3-2,
CJE = 4.49pF, CJC = 3.64pF and F = 300ps = 0.3ns. Then the hybrid-pi capacitances are
C = 2 × 4.49 + 20 × 0.3 = 15 pF
C = 3.64/2 = 1.8pF
And so the node capacitances are
CN1 = C + 2C = 15 + 3.6 = 18.6pF = CN2
CN3 = C = 1.8pF
And the node resistances are
RN1 = R1||R2||RZ ||r = 120||40||60||5 = 4k
RN2 = 1/gm = 0.05k
RN3 = R3||RL = 20||5 = 4k
And then the time constants are
N1 = 18.6 × 4 = 74 ns
N2 = 18.6 × 0.05 = 0.9ns
N3 = 1.8 × 4 = 7.2 ns
And so the high-frequency time constant N = N1 + N2 + N3 = 74 + 0.9 + 7.2 = 82ns
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So the equivalent high frequency pole pH = 1/N = 1/ 83ns = 12.0 Mr/s
Corresponding to fH = 0.16 × pH = 0.16 × 12.0 = 1.92 MHz
**The dominant node is the one with the largest time constant, which is N1.
Combining bandwidth with transfer gain |vL/vI|
= | g m R3 || RL | = |-20 × 20 || 5| = 80 V/V
gives GB = 80 × 1.92 = 153MHz
Figure E12.5-1b. Pspice simulation of the CE circuit.
The pspice assessment shows a midband gain of 17dB and a low frequency corner defined by (17dB –
3dB = 14dB) of value fH = 1.73MHz which is not inconsistent with the analytical result. (pspice value is
always the more accurate result.) The transfer gain represented by pspice is vL/vS, which if it had been evaluated would have been = (4.5/65) × 80 = 5.5V/V (= 14.8dB).
Higher frequencies on the order of UHF are within reach of the cascode configuration if the bias
resistances are reduced. For example if R1 and R2 are reduced by a factor of 50 then the largest time
constant N1 will be reduced by approximately the same factor. But it would then be necessary that the high transducer resistance RZ be buffered in order to accommodate the input voltage division.
The cascode configuration can be fielded using JFETs provided that sufficient care is taken with the bias network to ensure that the junctions are kept in reverse bias.
There is another high frequency topology that is fairly common, and can either be defined as the emitter- follower + common-base configuration or the wideband emitter-coupled pair. The BJT version of this topology is shown by figure 12.5-3. The parasitic capacitances are penciled in much like the context of
figure 12.5-1 and show the effect on the principal nodes of interest, N1 and N2.
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Figure 12.5-3. Wideband EF-CB configuration using BJTs. Note use of bipolar supply rails. The emitters are coupled to the current source node so it is also called the wideband emitter-coupled pair.
By inspection of the figure, the capacitances at node N1 will be terminated on either GND or the voltage supply rail. Consequently they are not afflicted by the Miller effect, and so
CN1 C C seriesC C C 2 (12.5-10)
The resistance at node N1 has (1) resistance into the base of transistor Q1 in series with the same
resistance for transistor Q2 so that
Rin1 r r 2r
Including (2) the resistance of the source RZ the operational resistance at node N1 is
RN1 RZ || 2r (12.5-11)
Node N1 will have a time constant N1 RN1CN1 (12.5-12)
(which uses equations (12.5-10) and (12.5-11))
Similarly node N2 will have a capacitance to GND that is not afflicted by the Miller effect, and therefore will be
CN 2 C (12.5-13)
and it will have resistance at node N2 of value
RN 2 R3 || RL (12.5-14)
Therefore node N2 will have a time constant N 2 RN 2CN 2 (12.5-15)
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The transfer gain of the circuit is that of an emitter follower followed by a common-base configuration
with the input signal vI divided by a factor of two since the two transistors are equal and will divide the signal between them. So the gain is then
vL 1 1 1 g m R3 || RL g m R3 || RL (12.5-16) vI 2 2
And we will check out this circuit with an example
EXAMPLE E12.5-2: Evaluate the wideband configuration shown assuming that both transistors are 2n3904 and that the source resistance is from a
previous stage with Rout = RZ = 2.5k. Compare results to pspice.
SOLUTION: The current is split equally between Q1 and Q2 so the transconductance is
gm = 40 × Ix/2 = 40 × 0.5mA = 20mA/V
And r F gm 100/20 = 5k
The capacitances are C = CJC/2 = (3.64pF)/2 = 1.8pF
And C = 2CJE + gm × F = 2 × 4.49pF + 20mA/V × 0.3ns = 15 pF
And so CN1 = 1.8pF + (15pF)/2 = 9.3pF with associated resistance
RN1 = 2.5||(2 × 5) = 2.0k
For which N1 = 9.3 × 2.0 = 18.6ns
And at node N2 we have CN2 = CJC/2 = 1.8pF and RN2 = 10||40 = 8 k so that
N2 = 1.8 × 8 = 14.4ns
And this give an overall time constant of H = N1 +N2 = 18.6 + 14.4 = 33ns
For which the high frequency pole is pH = 1/H =1/33ns 30Mr/s
Or fH = 0.16 × pH = 0.16 × 30 = 4.80 MHz
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vL 1 With transfer gain g m R3 || RL = 0.5 × 20 × 10||40 = 80 V/V vI 2
And so the gain-bandwidth product GB = 4.80 × 80 = 384MHz
The pspice simulation shows An upper frequency corner of
fH = 6.12MHz which is consistent with that ascertained analytically (and is more accurate).
The GB product is in the UHF range of the RF spectrum and the upper frequency corner is in the VHF range of the RF spectrum.
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PORTFOLIO and SUMMARY
(1) STC (single time constant) analysis:
(a) Low frequency time constants LK= RKCK for each circuit capacitances CK where RK = resistance network that charges/discharges CK.
(b) High frequency time constants: Parasitic capacitances
BJT: CBE 2CJE CBC 0.5CJC
C CBE g m F Cp= CBE + gmtF
C CBC
JFET: CGS and CGD = spice params 2 MOSFET: C C W L CGSO W C CGDOW GS 3 OX GD
CJD = CJ × AD + CJSW × PD where AD = W × LD PD = 2 × (W + LD)
v (c) Miller multiplication 2 C11 C12 1 v1
(2) CE/CS topology
v v ' E ' C C C 1 C C 1 vB vB
' vE = RiB r r 1 vB
'' vB vC C C 1 C 11 vC vB v g v R || R E m C 3 L vB g m G4 vB 1 g m R4
HK RNK || CNK H H1 H 2 GB AV f H
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(3) High-bandwidth topologies
(a) Cascode topology
CN1 2C C
CN 2 2C C
CN 3 C
RN1 R1 || R2 || RZ || r
RN 2 Rin2 1 g m
RN3 R3 || RL
vL g m R3 || RL vI
HK RNK || CNK H H1 H 2 H 3 GB AV f H
(b) Wide –Band topology
CN1 C C 2
CN 2 C
RN1 RZ || 2r
RN 2 R3 || RL
vL 1 g m R3 || RL vI 2
CN1 CGD CGS 2
CN 2 CGD
RN1 RZ
RN 2 R3 || RL
vL 1 g m R3 || RL vI 2
HK RNK || CNK H H1 H 2 GB AV f H
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