Circuits, Devices, Networks, and Microelectronics CHAPTER 12. TRANSISTOR PARASITICS: Time constants and frequency domain analysis 12.1 SINGLE TIME-CONSTANT ANALYSIS The speed of a circuit is governed by its time constants. For most electronic circuits these are due to capacitances since (1) capacitances are used for coupling signals into and/or out of the transistor and (2) transistor devices have parasitic capacitances. Coupling capacitances are on the order of F and parasitic capacitances are on the order of pF and fF, (depending on the type of transistors). Assuming resistance defaults of k the expectations should be (coupling) = RC = 1k × 1F = 1msec → f in kHz (parasitic) = RC = 1k × 1pF = 1nsec → f in GHz The default context is illustrated by figure 12.1-1. And the expectations are then a shortcut. Figure 12.1-1. CS topology with coupling capacitances (default = F) and source resistance RZ. Another shortcut is the approximation conversion between time constants and frequency 1 f 0.16 where = 1/ 2 And even though the radian frequency () is the analytical domain for poles and zeros the operational domain is always Herzian frequency. Impulses will always relate to rise times and fall times and to overshoots and undershoots. The frequency domain will relate to the Bode magnitude plot as represented by figure 12.1-2. 317 Circuits, Devices, Networks, and Microelectronics Figure 12.1-2. Bode plot response of a single stage subcircuit. The Bode magnitude plot is characterized by (1) midband gain (|vL/vS|) and (2) upper and lower 3dB roll- off corners. The corners relate to poles, and poles are defined by RC time constants. The lower frequency poles are usually due to the coupling capacitances (F) and the lower pole frequency corner may roughly be approximated by p L p L1 p L2 p L3 ... (12.1-1) where pL1, pL2, pL3, .. are (single time constant) low frequency poles. The higher pole frequency corner may be roughly approximated by 1 1 1 1 .. = H1 H 2 H 3 ... (12.1-2) pH pH1 pH 2 pH 3 Where pH1, pH2, pH3, .. are (single time constant) high frequency poles. Take note that it may be more convenient to use time constants rather than poles for the high-frequency assessments. Be aware that these approximations are crude. In reality the circuit should be assessed by network analysis using complex admittances and impedances. But this sort of analysis is not one for back-of-the envelope assessments. Fortunately we have pspice or some other circuit simulation utility that will accomplish multi-node nodal analysis with considerable alacrity. And its post-processor will generate Bode magnitude plots, Bode phase plots and even extract the fL and fH corner information. Equations (12.1-1) and (12.1-2) are a means to make a rough assessment as well as determine which poles are dominant. The dominant poles are the ones that become targets when extending the reach of the circuit. Equation (12.1-1) shows that the highest of the low frequency poles is dominant and equation (12.1-2) shows us that the lowest of the high frequency poles is dominant. The rest of the story relies on the assumption that the poles are separable. They are not. But for the sake of assessment they are treated as if they can be isolated as if each were dominant. And that assumption is 318 Circuits, Devices, Networks, and Microelectronics sufficient to make practical use of the simplifying context of equations (12.1-1) and (12.1-2), whether for the benefit of a rough definition of the circuit performance characteristics or for identifying the constraints and redesigning for a greater reach. 12.2 LOW-FREQUENCY APPROXIMATIONS Using the assumption that the poles are separable and that capacitances can be treated as separable the rest of the story is in the resistances. Each capacitance will have a resistance link through which it will charge and discharge. And that is one of the reasons why the resistance of the input source must be included. It forms part of the resistance path for the input coupling capacitance. If the source is from a previous stage then it is the output resistance of that stage. However if it is from a transducer (more common) then it must be ascertained from the specification of the transducer. A transducer is defined in terms of its short-circuit current (iSS) and its open-circuit (signal) voltage vS so that RZ = vS/iSS (source transducer resistance) (12.2-1) It then becomes part of the resistance that is ‘seen’ by the input capacitance. This context is represented by figure 12.2-1. Figure 12.2-1. (Low frequency) pole for the input capacitance (C1). And then the time constant is L1 RZ Rin C1 (12.2-2) for which pL1 = 1/L1. Since Rin can be determined by inspection the pole can also be determined by inspection, - or at least by no more than a couple of hiccups. The time constant associated with the output is similar to that of the input. And it also includes the resistance RL which is external to the two-port subcircuit. It has been included before as a part of the 319 Circuits, Devices, Networks, and Microelectronics signal load of the transistor. It may be a transducer for vibrating another medium. More likely RL is the input resistance to the next stage. Its context is shown by figure 12.2-2. Figure 12.2-2. (Low frequency) pole for the output capacitance (C2). The time constant associated with the output capacitance is L2 Rout RL C 2 (12.2-2) for which pL2 = 1/L2. Since Rout can be done by inspection, particularly in its rough form, this pole can also be done by inspection. Keep in mind that approximations are rampant in the science and art of electronics, in particular in the evaluation of the frequency domain for which the analysis represented by the above equations will be superceded by simulation. But the step is necessary for the preliminary assessment and for making judgment calls on device sizing. If a circuit includes a bypass capacitance as identified by topologies such as that shown by figure 12.1-1 (CS topology) it also fits into the same category as figure 12.2-1 and 12.2-2 in that the rest of its story is L3 R5 || R4 RiE C3 (12.2-3) and for which pL3 = 1/L3. The context of this capacitance is represented by figure 12.2-3, where it should be evident that the smaller resistances (R4 + RiE) will be dominant. If it is applied to the FET then the dominant resistance will be (R4 + RiS). Figure 12.2-3. Low frequency pole for the bypass capacitance (C3). 320 Circuits, Devices, Networks, and Microelectronics The small resistance (R4 + RiE) will not only dominate the approximations (the results will always be smaller than the smallest) they will also cause C3 to dominate the set of low frequency poles unless C3 is made considerably larger than the other capacitances. Keep in mind that the pole is the reciprocal of the time constant and so the highest of the low also is associated with the smallest time constant. So if C3 is small and (R4 + RiE) is small courtesy of its circumstance, then the pole associated with C3 (bypass capacitance) will most likely be the dominant pole. Consider the following example EXAMPLE 12.2-1: For the CE topology shown and an input transducer with open circuit signal voltage vS = 5mV and short-circuit signal current iSS = 0.1 mA determine (a) source resistance RZ (b) transfer characteristics Rin, Rout and vL/vI, and (c) dominant low frequency pole and the approximate corner frequency fL. And (d) compare the midband gain and lower corner frequency to the result using pspice. ANALYTICAL SOLUTIONS: (a) RZ = vS/iSS = 5.0mV/0.1mA = 50 k (b) For the source current shown gm = 40 × I = 4.0mA/V. By inspection RiB = 75k [= 100 × (1/4.0 + 0.5)] Then (by inspection) Rin k ( = 150||75||75 ) vL 30 45 And by inspection Rout = 30 k (R3 ) and -24V/V vI 1 4 0.5 (and where | -24V/V| is approximately 28dB) (c) The time constant for capacitance C1 is 1 = 0.2 × (50 + 30) = 16 ms → pL1 = .0625 kr/s The time constant for capacitance C2 is 2 = 0.2 × (30 + 45) = 15 ms → pL2 = .0667 kr/s 1 RBS 1 150|| 75|| 50 RiE = = 0.5 k g m F 4 100 And so the time constant for capacitance C3 is 3 = 4.0 × (0.5+ 0.5) = 4 ms → pL3 = 0.25 kr/s * Note that pL3 gets recognition and a star because it is the dominant pole. 321 Circuits, Devices, Networks, and Microelectronics The low frequency corner pole is approximated by pL = (.0625 + .0667 + 0.25) = 0.38 kr/s For which fL 0.16 × 0.38 = .061 kHZ = 61 Hz PSPICE SOLUTIONS: The circuit execution in pspice gives results as shown. The cursor coordinates indicate the midband gain |vL/vS| in dB and the low-frequency corner in Hz The pspice assessment shows a |vL/vS| midband gain of 19.2 dB and a low frequency corner defined by (19dB – 3dB = 16dB) of value fL = 47.0 Hz . The pspice value is the more accurate result. The analytical value is not inconsistent with that of the pspice corner and supplies more information about the dominant components within the circuit. 12.3 PARASITIC CAPACITANCES in TRANSISTORS The simulation result for the previous example also shows that there is an upper-frequency roll-off at approximately 200kHz.