Parasitics Impact on the Performance of Rectifier Circuits in Sensing RF

sensors

Article Parasitics Impact on the Performance of Rectiﬁer Circuits in Sensing RF Energy Harvesting

Antonio Alex-Amor 1,2,*, Javier Moreno-Núñez 3 , José M. Fernández-González 2 , Pablo Padilla 3 and Jaime Esteban 2

1 Departamento de Lenguajes y Ciencias de la Información, Universidad de Málaga, 29071 Málaga, Spain 2 Information Processing and Telecommunications Center, Universidad Politécnica de Madrid, 28040 Madrid, Spain; [email protected] (J.M.F.-G.); [email protected] (J.E.) 3 Departamento de Teoría de la Señal, Telemática y Comunicaciones, Universidad de Granada, 18071 Granada, Spain; [email protected] (J.M.-N.); [email protected] (P.P.) * Correspondence: [email protected]

Received: 19 September 2019; Accepted: 6 November 2019; Published: 13 November 2019

Abstract: This work presents some accurate guidelines for the design of rectifier circuits in radiofrequency (RF) energy harvesting. New light is shed on the design process, paying special attention to the nonlinearity of the circuits and the modeling of the parasitic elements. Two different configurations are tested: a Cockcroft–Walton multiplier and a half-wave rectifier. Several combinations of diodes, capacitors, inductors and loads were studied. Furthermore, the parasitics that are part of the circuits were modeled. Thus, the most harmful parasitics were identified and studied in depth in order to improve the conversion efficiency and enhance the performance of self-sustaining sensing systems. The experimental results show that the parasitics associated with the diode package and the via holes in the PCB (Printed Circuit Board) can leave the circuits inoperative. As an example, the rectifier efficiency is below 5% without considering the influence of the parasitics. On the other hand, it increases to over 30% in both circuits after considering them, twice the value of typical passive rectifiers.

Keywords: RF energy harvesting; guidelines; sensor applications; low-power; Cockcroft–Walton multiplier; half-wave rectiﬁer; parasitics modeling

1. Introduction With the rapid development of wireless communications in the latest years, there has been an exponential increase in the number of radiofrequency (RF) transmitters operating in VHF and UHF bands. As a consequence, ambient RF power density has increased and RF energy harvesting has become an environment-friendly energy source for low-consumption electronic devices, such as sensors, regulators, oscillators and LCD screens [1,2]. Additionally, RF energy is present both indoors and outdoors, which is an advantage with respect to other harvestable sources. The most significant power contribution normally comes from mobile network (0.8, 0.9, 1.8, and 2.1 GHz) and WiFi frequency bands (2.4 and 5.2 GHz). Specifically, previous works have demonstrated that most part of the incoming RF power has its origin in mobile bands [3–5]. Concretely, Ref. [5] points out that more than an 80% of the power harvested is located in 0.8 and 0.9 GHz frequency bands. Rural and remote areas are especially interested for looking at self-sustaining sensing systems due to the difficulty of access to them. Low-power sensors can benefit from the use of RF harvesting systems and be deployed in these challenging environments, forming wireless sensor networks (WSNs) [6] applied in, e.g., tracking and farming tasks [7,8] or monitoring fire risk areas [9]. As an example, Figure1 shows a possible implementation of a low-power WSN formed by independent.

Sensors 2019, 19, 4939; doi:10.3390/s19224939 www.mdpi.com/journal/sensors Sensors 2019, 19, 4939 2 of 16 Sensors 2019, 19 FOR PEER REVIEW 2

Figure 1.1. Example of a wireless sensor network (WSN)(WSN) where the sensing devices are powered by radiofrequencyradiofrequency (RF)(RF) energyenergy harvestingharvesting systems.systems.

Autonomous nodes.nodes. EachEach node node is is powered powered by by a RFa RF harvesting harvesting system, system, formed formed in four in four stages stages [10]: a[10]: RF harvester,a RF harvester, a receiving a receiving antenna antenna that collects that energycollects from energy the bandsfrom the of interest;bands of a rectifierinterest; circuit a rectifier that convertscircuit that the converts signal acquired the signal by acquired the antenna by the into an atenna DC supply into a source;DC supply a matching source; circuit,a matching in charge circuit, of maximizingin charge of themaximizing power transfer the power from transfer the antenna from to the the antenna rectifier to circuit; the rectifier and a storagecircuit; circuit,and a storage which storescircuit, the which acquired stores power the acquired in order power to feed in a order certain to electronicfeed a certain device. electronic device. Nowadays, the bottleneck in energyenergy harvestingharvesting isis thethe designdesign ofof thethe rectifierrectifier circuit.circuit. This is partiallypartially attributedattributed toto thethe losseslosses presentpresent inin thethe diodes.diodes. The low input power level provokes the diodes intointo dissipatingdissipating anan importantimportant partpart ofof thethe incomingincoming power.power. Specifically,Specifically, RFRF harvestingharvesting systemssystems mustmust operate with lower power densities [[3–5]3–5] compared to other harvestable sources, such as the sun, windwind oror vibrationsvibrations [[11].11]. Moreover, thethe nonlinearitynonlinearity associatedassociated withwith thethe diodesdiodes representsrepresents anan addedadded didifficultyfficulty [12[12]:]: thethe performance performance of of the the entire entire system system is dependent, is dependent, among among other other parameters, parameters, on the on input the power,input power, which unfortunatelywhich unfortunately hampers hampers the design the of desi thegn matching of the matching circuit. Because circuit. of Because these combined of these facts,combined the e ffifacts,ciency the of efficiency different topologiesof different of topologies passive circuitries of passive (not circuitries externally fed)(not isexternally normally fed) under is 15%normally [10,12 under–14]. On15% the [10,12–14]. other hand, On the there other are hand, some recentthere are studies some thatrecent have studies applied that active have applied circuits (externallyactive circuits fed) (externally [14,15] in orderfed) [14,15] to lower in theorder threshold to lower voltage the threshold of diodes voltage/transistors. of diodes/transistors. In these cases, the In componentthese cases, lossesthe component are reduced losses and are the reduced efficiency and enhanced, the efficiency at the enhanced, expense of at using the expense an external of using feed, whichan external is prohibitive feed, which for self-sustainingis prohibitive for devices self-sustaining [16,17]. devices [16,17]. The mostmost commonlycommonly used topologytopology for aa passivepassive rectifierrectifier circuitcircuit isis thethe half-wavehalf-wave rectifier.rectifier. It benefitsbenefits from aa simplersimpler designdesign andand lowerlower losseslosses comparedcompared to full-wavefull-wave schemes [[18],18], since onlyonly one diode is required.required. On the other hand, the low-voltagelow-voltage input levels make multipliermultiplier circuits, such as thethe Cockcroft–Walton (CW) (CW) multiplier multiplier [14], [14], an an intere interestingsting option option to toconsider. consider. At Atleast least two two diodes diodes are areneeded needed in this in this configuration, configuration, so sothe the losses losses are are similar similar to to those those of of a a full-wave full-wave rectifier rectifier but higherhigher compared toto aa half-wavehalf-wave rectifier. rectifier. As As opposed opposed to to the the full-wave full-wave rectifier, rectifier, the the CW CW multiplier multiplier is capableis capable of elevatingof elevating the the input input voltage voltage while while rectifying. rectifying. Ideally, Ideally, the more the more stages stages are placed, are placed, the higher the thehigher output the voltageoutput voltage is. However, is. However, the losses the in losses the diodes in the typicallydiodes typically prevent prevent one from one using from more using than more one than stage one in thestage CW in multiplier,the CW multiplier, since the sinc efficiencye the efficiency rapidly decays. rapidly decays. InIn addition,addition, there isis aa needneed forfor aa circuitcircuit modelmodel thatthat isis capablecapable ofof predictingpredicting howhow thethe parasiticsparasitics aaffectffect thethe operationoperation ofof thethe system.system. Regretfully, the vast majority of papers in the literature do notnot provideprovide aa clearclear insightinsight onon thethe matter.matter. In this paper,paper, wewe presentpresent aa designdesign methodologymethodology toto maximizemaximize thethe powerpower suppliedsupplied toto the sensor by taking into account the nonlinearity of the circuits and the eeffectffect of the parasiticparasitic elements. We studystudy two didifferentfferent configurations:configurations: thethe half-wave rectifierrectifier and the CW multiplier. However,However, the the steps steps followed followed in the in document the document can be can extrapolated, be extrapolated, without losswithout of generality, loss of generality, to any other configuration. According to the estimations of the incoming power provided in [3–5], the circuits are designed to operate within 800–900 frequency bands, the center frequency

Sensors 2019, 19 FOR PEER REVIEW 3 being 870 MHz. Several combinations of components were tested in both circuits. Thus, the most harmful parasitics in the circuits were identified and modeled. The experimental results show that a proper modeling of the parasitic elements is fundamental in order to avoid a low conversion efficiency in the rectifiers. The document is organized as follows. Section 2 presents the design methodology and the different steps involved in it. Section 3 gives useful insights on the choice of components. Section 4 describes the design of the matching circuit and the search for the optimal source impedance that Sensors 2019, 19, 4939 3 of 16 maximizes the rectifier efficiency. Section 5 presents the model of the parasitics and their influence on the overall performance of the circuits. Finally, Section 6 presents the main conclusions. to any other configuration. According to the estimations of the incoming power provided in [3–5], the 2.circuits Design are Process designed to operate within 800–900 frequency bands, the center frequency being 870 MHz. SeveralDue combinations to the nonlinearity of components of rectifier were testedcircuits, in boththeir circuits.input impedance Thus, the most (and harmful their response) parasitics inis dependentthe circuits on were many identified parameters: and modeled. the input The power, experimental the antenna results impedance, show that the a proper load impedance modeling of (the the typeparasitic of sensor elements we isuse), fundamental the operation in order frequency, to avoid etc. a low Furthermore, conversion the effi ciencyrectifier in thecannot rectifiers. be directly attachedThe documentto the antenna, is organized since there as follows. exists Sectionan impedance2 presents mismatch the design between methodology both, which and the translates di fferent intosteps a involvedlow rectifier in it. efficiency. Section3 gives Consequently, useful insights a matching on the choice circuit of is components. commonly placed Section between4 describes the antennathe design and of the the rectifier matching to circuitmaximize and the the power search tran for thesfer. optimal However, source the impedancedesign of the that matching maximizes circuit the suffersrectifier from efficiency. the same Section problems5 presents associated the model with the of thenonlinearity parasitics of and the their rectifier. influence on the overall performanceThe design of themethod circuits. that Finally, overcomes Section these6 presents difficul theties main and conclusions.maximizes the rectifier efficiency is presented in Figure 2, as an iterative process. First, we must select the components that are part of 2. Design Process the rectifier circuit, trying to reduce the losses in the diode and the output voltage ripple of the rectifiedDue DC to the signal. nonlinearity Then, we of must rectifier design circuits, the theirmatchi inputng circuit. impedance The design (and their of the response) matching is dependent circuit is basedon many on parameters:the search, for the a input given power, load the𝑍, antennaof the optimal impedance, source the impedance load impedance 𝑍 that (the maximizes type of sensor the powerwe use), transfer the operation between frequency, the antenna etc. and Furthermore, the rectifier. theThus, rectifier the components cannot be directlyof the matching attached circuit to the areantenna, estimated since in there order exists to maximize an impedance the rectifier mismatch efficiency. between However, both, which the parasitics translates of into the a components low rectifier andefficiency. PCB (Printed Consequently, Circuit aBoard) matching do influence circuit is commonlythe search of placed 𝑍. They between should the be antenna taken andinto theaccount rectifier in theto maximize circuits in the order power to avoid transfer. the frequency However, displace the designment of thethey matching cause. Once circuit they su haveffers frombeen theproperly same modeled,problems the associated circuit is with measured the nonlinearity in the laboratory of the rectifier.. If the measurement does not correspond with the simulations,The design the optimal method source that overcomes impedance these is recalculated, difficulties andby taking maximizes now into the account rectifier the effi ciencyeffect of is thepresented parasitics in Figure that was2, as measured, an iterative and process. the matching First, we circuit must select is improved the components until acceptable that are partresults of theare achieved.rectifier circuit, trying to reduce the losses in the diode and the output voltage ripple of the rectified DC signal.The approach Then, we proposed must design here the is matching not limited circuit. to Theany designparticular of the power matching or circuitfrequency is based range. on Furthermore,the search, for complementary a given load ZL ,toolsof the can optimal be utilized source in impedance any particularZs that stage maximizes of the design the power method. transfer As anbetween example, the the antenna vector and network the rectifier. analyzer Thus, (VNA) the can components be utilized of for the hand-tuning matching circuit the matching are estimated circuit. in Trimmableorder to maximize (variable) the rectifiercomponents efficiency. can be However, added to the the parasitics matching of the circuit, components so the andefficiency PCB (Printed of the rectifiersCircuit Board) can be do optimized influence thewith search the VNA. of Zs. TheyHowever, should this be takenapproach into accountshould be in theseen circuits as an inad order hoc solution,to avoid thespecific frequency and displacementunique for each they design. cause. OnceAs a theyconsequence, have been it properly could be modeled, difficult the to circuit extract is conclusionsmeasured in about the laboratory. the deviations If the measurementthat the parasitics does cause not correspond and to quantify with the their simulations, effect on thethe optimalcircuit, whichsource is impedance the main purpose is recalculated, of the method by taking we propose. now into Gaining account insight the e ffonect the of parasitics’ the parasitics impact that could was potentiallymeasured, andease thethe matchingdesign of circuitfuture isefficient improved rectifiers. until acceptable results are achieved.

FigureFigure 2. 2. FlowchartFlowchart for for the the efficient eﬃcient design design of of rectifier rectiﬁer circuits.

The approach proposed here is not limited to any particular power or frequency range. Furthermore, complementary tools can be utilized in any particular stage of the design method. As an example, the vector network analyzer (VNA) can be utilized for hand-tuning the matching circuit. Trimmable (variable) components can be added to the matching circuit, so the efficiency of the rectifiers can be optimized with the VNA. However, this approach should be seen as an ad hoc solution, specific and unique for each design. As a consequence, it could be difficult to extract conclusions about Sensors 2019, 19, 4939 4 of 16 the deviations that the parasitics cause and to quantify their effect on the circuit, which is the main purpose of the method we propose. Gaining insight on the parasitics’ impact could potentially ease the design of future efficient rectifiers.

3. Choice of Components In this section, some advice is given in order to select the components that are part of the rectifier circuit. The diode is the critical element in the circuit design. It must switch quickly to ensure its operation in the GHz range, and it must consume very little power. Compared to p–n diodes, Schottky diodes (metal–semiconductor (M–S) junctions) benefit from a faster switching time and a lower forward voltage drop (0.2 0.3 V versus 0.6 0.7 V), which makes them perfect for use in RF energy harvesting. − − Two diodes frequently used in this context are the HSMS-2822, specifically designed for input power levels above 20 dBm at frequencies below 4 GHz; and the HSMS-2850 (single mode), optimized for use − with small signals (P < 20 dBm) at frequencies below 1.5 GHz. According to their datasheets [19], in − HSMS-2822 diodes can provide 0.1 mA with a maximum voltage drop of 0.22 V, while HSMS-2850 diodes can provide the same current with a maximum voltage drop of 0.15 V. Some studies point out that the power levels foreseen in RF energy harvesting are normally higher than 20 dBm [4,10,12,14]. − Thus, we decided to use the HSMS 2822 diode. The choice of the capacitor is a trade-off between the output ripple of the circuit, and the self-resonant frequency (SRF) of the capacitor itself. The higher the value of the capacitor, the lower the output ripple is, and normally, the lower its SRF. The SRF is directly related to the parasitics of a certain component and is calculated as

1 SRF [Hz] = (1) 2π √LC

The lower the SRF is, the higher the value of the parasitic element and the more harmful its eﬀect on the circuit. With the use of Equation (1), we show an estimate in Section5 for the parasitic elements associated with inductors and capacitors.

4. Circuit Design In this section, we describe the development of the procedure to design the lossless matching circuit that maximizes the rectifier efficiency. The design is particularized for the two topologies of the rectifiers under study: the CW multiplier and the half-wave rectifier. The matching circuit is implemented with a L network in both circuits. However, the same procedure is still applicable for different topologies of rectifier and matching schemes. The measurement setup and the fabricated circuits are visualized in Figures3 and4. The circuits were implemented in perforated boards: the components were placed in the top layer and the tracks in the bottom layer. Two different boards of similar characteristics were used in the design of the half-wave rectifiers and the Cockcroft–Walton multipliers. In Figure4, label “Test” refers to the test CW multiplier and half-wave rectifier used to study the effect of the parasitic elements, and label “Final” refers to the redesigned final CW multiplier and half-wave rectifier.

Optimal Source Impedance Usually, the input power of the circuit (the power acquired by the antenna) is a combination of carriers with diﬀerent amplitudes and frequencies [4]. As illustrated in Figure5, a smart approach can be applied in this scenario. The antenna impedance and the matching circuit were replaced together, by a source impedance Zs = Rs + jXs. Afterwards, an L network was designed in order to transform the antenna impedance Zant into the optimal source impedance Zs at the frequency of interest (870 MHz, in this case). SensorsSensors2019 2019,,19 19, 4939FOR PEER REVIEW 5 of 165 Sensors 2019, 19 FOR PEER REVIEW 5

Figure 3. Measurement setup. Figure 3. Measurement setup.

(a) (a)

(b) (b) FigureFigure 4. ManufacturedManufactured (a ()a )half-wave half-wave rectifiers rectifiers and and (b) ( bCockcroft–Walton) Cockcroft–Walton multipliers. multipliers. The Thefinal finalhalf- Figurehalf-wavewave rectifier 4. Manufactured rectifier was wasobserved observed (a) half-wave under under the rectifiers themicroscope. microscope. and (Lab) belsCockcroft–Walton Label “Test” “Test” and refers “Final” multipliers. to the refer test to CWThe the multiplierfinalcircuits half- of waveandFigures half-wave rectifier 10 and was rectifier 11, observedand usedFigures tounder study 13 and the the 14,microscope. eff respectively.ect of the La parasiticbels “Test” elements, and “Final” and label refer “Final” to the refers circuits to the of Figuresredesigned 10 and final 11, CW and multiplier Figures 13 and and half-wave 14, respectively. rectifier.

To make a fair comparison between the performances of both circuits (CW and half–wave rectifiers), the input powers and the frequencies for both were kept the same (Pin = 0 dBm, f = 870 MHz). However, the load was different, ZL = 2.34 kΩ in the CW and ZL = 8 kΩ in the half-wave rectifier. For the two given loads ZL, the optimal source impedance Zs was found via an optimization process in a harmonic balance simulation [20] performed in commercial software ADS. Since Zs is a complex value, the efficiency of the rectifier may be visualized in a 3D plot with respect to the resistance Rs and the reactance Xs. Thus, Figures6 and7 illustrate the search of the optimal Zs in.

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Figure 5. Search of the optimal source impedance 𝑍 in the Cockcroft–Walton multiplier and the half- wave rectifier.

The CW and in the half-wave rectifiers, respectively, before and after considering the parasitics.

Despite the optimal values being different (𝑍 = 42 + 𝑗120 Ω and 𝑍 =10+𝑗50 Ω in the CW; 𝑍 = 30 + 𝑗280 Ω and 𝑍 = 10 + 𝑗130 Ω in the half-wave rectifier), both figures share some similarities. First, the reactance 𝑋 is positive in all the cases. This points out that the rectifiers show a mainly capacitive behavior (negative reactance), which should be neutralized with a positive reactance in the matching circuit to enhance a rectifier’s efficiency. In addition, the optimal reactance

𝑋 decreases (but remains positive) after including the effect of the parasitics. This is due to the Sensorsparasitic 2019 series-inductances,, 19 ,FOR 4939 PEER REVIEW associated with the via holes (see Section 5), which contribute with6 of 16a6 positive reactance term and reduce the capacitive behavior of the rectifiers. Second, the shape of the 3D plot is completely different before and after considering the parasitic elements, which illustrates the importance of modeling them. Concretely, the curves show a steeper response after including the parasitics. This fact is directly related to the reduction of 𝑅 and indirectly indicates to us that the parasitic elements reduce the operation bandwidth of the circuit.

The CW and in the half-wave rectifiers, respectively, before and after considering the parasitics. 50 50 Despite the optimal values being different (𝑍 = 42 + 𝑗120 Ω and 𝑍 =10+𝑗50 Ω in the CW; 40 40 𝑍 = 30 + 𝑗280 Ω and 𝑍 = 10 + 𝑗130 Ω in the half-wave rectifier), both figures share some 30 30 similarities. First, the reactance 𝑋 is positive in all the cases. This points out that the rectifiers show 20 20 a mainly capacitive behavior (negative reactance), which should be neutralized with a positive 10 10 reactance in the matching circuit to enhance a rectifier’s efficiency. In addition, the optimal reactance Efficiency (%) 0 (%) Efficiency 0 𝑋 decreases80 (but remains positive) after including the80 effect of the parasitics. This is due to the 60 200 60 200 parasitic series-inductances40 associated with100 the via holes (see Section 5), which contribute100 with a 0 40 0 Ω 20 -100 Ω 20 -100 positive reactanceR ( ) term and0 -200 reduce theX capacitive(Ω) behaviorR of( the) rectifiers.0 Second,X the (Ω shape) of the s s s -200 s 3D plot is completely different(a) before and after considering the parasitic(b el) ements, which illustrates the importance of modeling them. Concretely, the curves show a steeper response after including the 𝑍= =𝑅+ +𝑗𝑋 parasitics.Figure This 6.6. EEfficiencyﬃ factciency is directly withwith respectrespect related to to the the to source sourcethe reduction impedance impedance ofZs 𝑅 Rands jXindirectlys in in the the Cockcroft–Walton indicatesCockcroft–Walton to us (CW) that the Sensors 2019, 19 FOR PEER REVIEW 7 parasitic(multiplierCW) elements multiplier before reduce before (a) and the(a after) and oper ( bafter)ation considering (b )bandwidth considering the parasitics. ofthe the parasitics. circuit.

With the use of the formulas presented in [21], the optimal source impedance 𝑍 is transformed into the lumped elements that form the L matching network. The antenna impedance 𝑍 was 50 50 assumed to be 𝑍 =50 Ω here. With the components available in the laboratory (Table 1), we 40 40 implemented the 𝐿 networks that can be seen in Figures 10a and 11a. The L network of the CW 30 30 multiplier lacks a capacitor, as far as the optimal impedance 𝑍 = 42 + 𝑗120 Ω can be approximated 20 20 by 𝑍 ≈ 50 + 𝑗120 Ω. Since the impedance of the antenna already covers 50 Ω, only a series 10 10 inductance is needed (two in series, in our case, due to inventory shortage) to achieve 𝑗120 Ω at 870 Efficiency (%) Efficiency (%) Efficiency 0 0 MHz. 80 80 60 400 60 200 100 40 200 40 0 Ω 20 0 Ω 20 -100 R ( ) X (Ω) R ( ) 0 X (Ω) s 0 -200 s s -200 s 50 (a) 50 (b) 40 40 𝑍 = = 𝑅++𝑗𝑋 FigureFigure30 7. 7.E Efficiencyfficiency with with respect respect to to the the source source impedance impedance30 Z S Rs jXs in in the the half-wave half-wave rectifier rectifier beforebefore20 (a ()a and) and after after (b ()b considering) considering the the parasitics. parasitics. 20 10 10 5. ParasiticThe CW Elements and in the half-wave rectifiers, respectively, before and after considering the parasitics. Efficiency (%) 0 (%) Efficiency 0 Despite80 the optimal values being different (Zs =8042 + j120 Ω and Zs = 10 + j50 Ω in the CW; Z = 30In+ thisj28060 section,and weZ =describe10 + j130 the parasiticsin the200 half-wave that are rectifier),associated60 both with figures the lumped share some elements similarities.200 and the s Ω40 s Ω 100 40 100 PCB. Thus, a circuit20 model was0 derived to correct the frequency displacement0 they cause. First, the reactanceΩ Xs is positive-100 in all theΩ cases. This pointsR (Ω) out20 that the rectifiers-100 showΩ a mainly R ( ) 0 -200 X ( ) s 0 -200 X ( ) capacitiveFurthermore, behaviors the contribution (negative reactance), of eachs parasitic which should was quantified be neutralized and the with most a positive harmfuls reactance parasitics in were the identified. (a) (b) matching circuit to enhance a rectifier’s efficiency. In addition, the optimal reactance Xs decreases (but remainsFigure positive) 6. Efficiency after including with respect the to eff theect ofsource theparasitics. impedanceThis 𝑍 =𝑅 is due +𝑗𝑋 to thein the parasitic Cockcroft–Walton series-inductances 5.1. Circuit Model associated(CW) multiplier with the before via holes (a) and (see after Section (b) considering5), which the contribute parasitics. with a positive reactance term and reduceFrom the capacitive previous behavior studies of[14] the and rectifiers. our observatio Second, thens, shape the necessity of the 3D plotof a isrobust completely model di ffforerent the beforecomplete and aftercircuit considering is clear. theFirstly, parasitic the SRF elements, of the which inductors illustrates and thecapacitors importance was of estimated modeling them.in the laboratory by connecting the component in series in a 50 Ω line. As described in Figure 8, capacitors and inductors are modeled as series and a shunt LC tank, respectively, since the effect of the parasitic

resistances 𝑅 can be neglected. Their parasitics are related with the self-resonant frequency (SRF), according to Equation (1). Furthermore, their SRF can be measured in the laboratory with the 50 Ωline shown in Figure 9a and with the use of a network analyzer. In the case of the inductor, its SRF was

determined via the non-transmission peak in the |𝑆| parameter (red curve in Figure 9b). In the case of the capacitor, its SRF was determined via the non-reflection peak in the |𝑆| parameter (blue curve in Figure 9b). Subsequently, the parasitic element of the component was obtained by using Equation (1). To avoid considering unwanted terms in the calculus (parasitics associated with the cables in the measurement, to the microstrip line, etc.), the system should be calibrated beforehand. Table 1 shows the parasitic elements of the lumped elements used in the CW multiplier and the half- wave rectifier. The diode is also the critical element from the point of view of the parasitics. Ohmic losses in the

diode are modeled through the series resistance 𝑅 =7.8 Ω and the junction resistance 𝑅 . The series resistance has little effect on the circuits, so it was neglected in this work. However, the junction resistance is dependent on the current 𝐼 flowing through the diode: the lower the current is, the

higher 𝑅. According to the datasheet of the diode, 𝑅 can be calculated as [19]: 8.33 ⋅ 10 𝑁𝑇 0.026 𝑅𝐼 = ≈ @ 25 C (2) 𝐼 +𝐼 𝐼 +𝐼

where 𝐼 is the saturation current, 𝑁 is an ideality factor and 𝑇 is the temperature. For the HSMS- 2822 diode [19], 𝐼 =48 nA, and 𝑁 = 1.067. For the current levels foreseen in the work (0.1–1 mA), we may expect junction resistances within the interval 𝑅 = 26– 260 Ω. The junction capacitance of a Schottky diode can be modeled by:

𝐶 𝐶𝑉 = , 𝑉 (3) 1− 𝜙

Sensors 2019, 19, 4939 7 of 16

Concretely, the curves show a steeper response after including the parasitics. This fact is directly related to the reduction of Rs and indirectly indicates to us that the parasitic elements reduce the operation bandwidth of the circuit. With the use of the formulas presented in [21], the optimal source impedance Zs is transformed into the lumped elements that form the L matching network. The antenna impedance Zant was assumed to be Zant = 50 Ω here. With the components available in the laboratory (Table1), we implemented the L networks that can be seen in Section 5.2. The L network of the CW multiplier lacks a capacitor, as far as the optimal impedance Z = 42 + j120 Ω can be approximated by Z 50 + j120 Ω. Since the S S ≈ impedance of the antenna already covers 50 Ω, only a series inductance is needed (two in series, in our case, due to inventory shortage) to achieve j120 Ω at 870 MHz.

Table 1. SRF and parasitics of the lumped elements.

Model Value SRF (GHz) Parasitic 4,841,372 (Fair-Rite) 33 nH 1.50 0.34 pF 106–909 (Murata) 8.2 nH 4.00 0.19 pF 795–8290 (TDK) 4.3 nH 7.64 0.10 pF 464–6773 (AVX) 33 pF 2.20 0.16 nH 532–2945 (TE Connect.) 47 nH 1.96 0.14 pF CW160,808 (Bourns) 27 nH 2.10 0.21 pF 2,310,325 (Multicomp) 2.7 pF 4.97 0.38 nH ATC 500S (ATC) 4.7 pF 8.32 0.078nH 2,809,454 (Kemet) 27 pF 4.84 0.040 nH

5. Parasitic Elements In this section, we describe the parasitics that are associated with the lumped elements and the PCB. Thus, a circuit model was derived to correct the frequency displacement they cause. Furthermore, the contribution of each parasitic was quantiﬁed and the most harmful parasitics were identiﬁed.

5.1. Circuit Model From previous studies [14] and our observations, the necessity of a robust model for the complete circuit is clear. Firstly, the SRF of the inductors and capacitors was estimated in the laboratory by connecting the component in series in a 50 Ω line. As described in Figure8, capacitors and inductors are modeled as series and a shunt LC tank, respectively, since the effect of the parasitic resistances Rp can be neglected. Their parasitics are related with the self-resonant frequency (SRF), according to Equation (1). Furthermore, their SRF can be measured in the laboratory with the 50 Ωline shown in Figure9a and with the use of a network analyzer. In the case of the inductor, its SRF was determined via the non-transmission peak in the S parameter (red curve in Figure9b). In the case of the capacitor, | 21| its SRF was determined via the non-reflection peak in the S parameter (blue curve in Figure9b). | 11| Subsequently, the parasitic element of the component was obtained by using Equation (1). To avoid considering unwanted terms in the calculus (parasitics associated with the cables in the measurement, to the microstrip line, etc.), the system should be calibrated beforehand. Table1 shows the parasitic elements of the lumped elements used in the CW multiplier and the half-wave rectifier. The diode is also the critical element from the point of view of the parasitics. Ohmic losses in the diode are modeled through the series resistance Rsd = 7.8 Ω and the junction resistance Rj. The series resistance has little effect on the circuits, so it was neglected in this work. However, the junction resistance is dependent on the current I flowing through the diode: the lower the current is, the higher Rj. According to the datasheet of the diode, Rj can be calculated as [19]:

5NT 8.33 10− 0.026 ◦ Rj(I) = · @ 25 C (2) Is + I ≈ Is + I Sensors 2019, 19 FOR PEER REVIEW 8 where 𝐶 is the zero-bias junction capacitance and 𝜙 is the built-in potential. For the HSMS-2822 diode [19], 𝐶 =0.65 pF and 𝜙 =26.7 V. For the voltage values foreseen in the article (𝑉<2 V), we may expect junction capacitances within the interval 𝐶 = 0.65 − 0.68 pF. Additionally, the capacitive coupling between the metallic pins of the diode package can significantly affect the performance of the circuit. This term is modeled with a parallel parasitic capacitance 𝐶, whose value is slightly tuned in simulation to 𝐶 =0.75 pF to fit the measurements. The parasitics associated with the lumped components have already been considered and modeled. The main contribution from the PCB comes from the via holes. The parasitic inductance associated with the via holes can be estimated as in [22]:

𝐿 nH = 5.08ℎ ln +1, (4) where ℎ is the height of the PCB and 𝑑 the diameter of the hole, both in inches. Variations in the height of the PCB can modify the value of the parasitic inductance associated with the vias. On the other hand, variations in the diameter of the via have less influence on the parasitic inductance due Sensorsto the2019 logarithm, 19, 4939 involved in Equation (4). In the case of the Cockcroft–Walton multiplier, the height8 of 16 of the PCB is 1.61 mm, and the diameter is 1 mm, which leads to a theoretical parasitic inductance 𝐿 =0.92 nH. In the case of the half–wave rectifier, both the height of the PCB (1.51 mm) and whereIs is the saturation current, N is an ideality factor and T is the temperature. For the HSMS-2822 𝐿 =0.88 diodethe diameter [19], Is =of48 thenA, hole and (0.90N = mm)1.067 are. For smaller, the current which levels leads foreseen to a smaller in the inductance work (0.1–1 mA), we may expectnH. In junctionmanufactured resistances circuits, within these the values interval willR bej = hi26gher–260 sinceΩ. The the junctionvias are not capacitance perfect cylinders. of a Schottky The diodeeffective can height be modeled of the by: PCB is normally higher, and the welding process causes additional series inductances. Thus, the parasitic inductances associatedCj0 with the via holes are slightly tuned in C (V) = , (3) simulation, resulting in 𝐿 =1.30 nH forj the CWq multiplier and 𝐿 =1.20 nH for the half–wave 1 V rectifier. − φB where Cj0 is the zero-bias junction capacitance and φB is the built-in potential. For the HSMS-2822 5.2. Discussion diode [19], Cj0 = 0.65 pF and φB = 26.7 V. For the voltage values foreseen in the article (V < 2 V), we may expect junction capacitances within the interval C = 0.65 0.68 pF. Additionally, the capacitive Figures 10 and 11 show the effect of the parasiticj elements− in the CW multiplier and the half– couplingwave rectifier, between respectively. the metallic The pins frequency of the diode displace packagement can they significantly cause (black affect dashed the performance line versus ofblack the circuit.solid line) This is term noticeable is modeled in both with circuits. a parallel Howeve parasiticr, note capacitance the goodCpd agreement, whose value between is slightly the complete tuned in simulationsimulation tomodelCpd = (orange0.75 pF dashed to fit the line) measurements. and the measurement (black solid line).

Sensors 2019, 19 FOR PEER REVIEW 9 FigureFigure 8.8. Model ofof thethe parasiticsparasitics forfor thethe lumpedlumped elements.elements.

(a) (b)

FigureFigure 9. Extraction9. Extraction of the of parasitic the parasitic elements elements from inductors from inductors and capacitors and capacitors through their through self-resonant their self- frequenciesresonant (SRFs):frequencies (a) measurement (SRFs): (a) measurement board and (b )board S-parameters. and (b) S-parameters. The SRF of an The inductor SRF of is determinedan inductor is viadetermined the non-transmission via the non-tr peakansmission in the S peak. The in SRF the of |𝑆 a capacitor|. The SRF isdetermined of a capacitor via is the determined non-reﬂection via the | 21| peaknon-reflection in the S11 . peak in the |𝑆 |. | |

The contribution of each parasite to the total displacement has been quantified, and some conclusions were extracted. In both cases, the contribution of the parasitic inductance associated with the capacitors (green dashed line) was completely negligible. On the other hand, the parasitic shunt

capacitance 𝐶 associated with the diode package (red dashed line) was the most harmful element, with a total contribution over of 64% to the total frequency displacement in both circuits. In that sense, recent works have shown the benefits of two-dimensional materials, e.g., MoS2 (molybdenum disulfide) [23–24], being applied to RF electronics. In particular, [24] presents a MoS2-based Schottky diode used as a rectifier in a RF energy harvesting system. To explain the different behavior of traditional Schottky diodes though, the junction and parasitic capacitances of this MoS2-based diode are in the order of 20 fF, 35 times less than those shown in Figures 10 and 11. Since the parasitics of the diode are the most damaging, the performance of the rectifiers could be potentially improved with the development of MoS2 diodes. Additionally, their cutoff frequency is also higher, which allows one to reduce losses at higher operating frequencies. As a comparison, the MoS2-based diode presented in [24] has a cutoff frequency of 10 GHz (zero external bias), while the HSMS 2822 diode utilized in this work only reaches up to 4 GHz. The contribution of the parasitic capacitance associated with inductors in the L matching networks is represented in blue in Figures 10b and 11b. In the case of the CW multiplier (Figure 10b), the frequency displacement they cause (9.67%) is lower compared to other parasitic terms, since the SRFs of the 4.3 nH and 8.2 nH inductors (see Table 1) are large. In addition, the contribution to the frequency displacement of the parasitic inductance associated with via holes (yellow curve in Figure 10b) is higher in this case, 22.25%. On the other hand, Figure 11b shows that the contribution, in the half-wave rectifier, of the parasitic capacitance associated with the inductor in the L matching network (blue curve), is appreciable—26.57%. However, the contribution of the parasitic inductance associated with the via holes (yellow curve) is less, 9.05%. As a comparison between both circuits, the inductor used in the L network of the half-wave rectifier possesses a lower SRF than the inductors of the CW multiplier (see Table 1). Thus, the parasitics of the latter are less harmful. Conversely, the contribution of the parasitic inductance associated with via holes is more prominent in the CW multiplier, despite its value being

approximately a third of the inductance 𝐿 and a sixth of 𝐿. However, since the parasitic capacitors C and C may be neglected in this circuit, there would be three parasitic inductances 𝐿 in series, and the sum of their values (31.3 nH) is of the order of 𝐿 = 4.3 nH. Figure 12 presents a Monte Carlo analysis on the effect of the variability of the components on the circuit efficiency. The analysis was applied to the CW multiplier and half-wave rectifier of Figures 10 and 11, respectively, after all the parasitics were included in the model. Capacitors (𝐶,𝐶 ,and 𝐶′, inductors (𝐿, 𝐿,and 𝐿′ and loads (𝑅 and 𝑅′ were assumed to follow a Gaussian distribution of standard deviation 5% from their nominal values. Figure 12a presents the Monte Carlo analysis

Sensors 2019, 19, 4939 9 of 16

The parasitics associated with the lumped components have already been considered and modeled. The main contribution from the PCB comes from the via holes. The parasitic inductance associated with the via holes can be estimated as in [22]: ! ! 4h L [nH] = 5.08h ln + 1 , (4) d where h is the height of the PCB and d the diameter of the hole, both in inches. Variations in the height of the PCB can modify the value of the parasitic inductance associated with the vias. On the other hand, variations in the diameter of the via have less influence on the parasitic inductance due to the logarithm Sensors 2019, 19 FOR PEER REVIEW 10 involved in Equation (4). In the case of the Cockcroft–Walton multiplier, the height of the PCB is 1.61on mm, the andCW themultiplier, diameter and is Figure 1 mm, 12b which shows leads one to on a theoretical the half-wave parasitic rectifier. inductance The minimumLvTheory deviation= 0.92 nH. In theobserved case of in the both half–wave figures rectifier,between both the thenominal height simulation of the PCB and (1.51 the mm) measurement and the diameter is within of thethe hole = (0.90variability mm) are range smaller, of the which components. leads to a As smaller observed, inductance the frequencyLvTheory0 deviation0.88 nH. caused In manufactured by the variability circuits, theseof valuesthe components will be higher was much since smaller the vias than are the not one perfect caused cylinders. by the parasitics The effective in Figures height 10 ofand the 11. PCB It is normallycan be higher,noticed and in Figure the welding 12 that process the half-wave causes additionalrectifier is seriesmore inductances.sensitive to deviation Thus, the in parasitic the inductancescomponents associated than the with CW themultiplier. via holes This are is slightly due to variations tuned in simulation, in the capacitor resulting C′ in in theLv L= network1.30 nH for of the half-wave rectifier. the CW multiplier and Lv0 = 1.20 nH for the half–wave rectifier. It is worth noticing that, in general terms, the most harmful parasitics are associated with 5.2.lumped Discussion elements and not with the PCB. Even in the worst scenario, the CW multiplier, the effect of the vias was not so important and easily neutralized with the circuit model. A particularly important Figures 10 and 11 show the effect of the parasitic elements in the CW multiplier and the half–wave conclusion can be extracted: despite us using a perforated PCB (perfboard), considered a low-quality rectifier,board respectively. in RF, its parasitics The frequency are not displacementespecially harmful they cause at these (black frequencies. dashed line Therefore, versus blackif carefully solid line) is noticeablechosen, low-quality in both circuits. RF PCBs However, can be utilized note at the frequencies good agreement below 1 betweenGHz in order the completeto ease the simulation design modeland (orangereduce costs dashed of the line) rectifier and thestage measurement in a harvesting (black system. solid line).

(a)

(b)

FigureFigure 10. 10.Model Model forfor the the parasitic parasitic elements elements in the in Cockcroft–Walton the test Cockcroft–Walton multiplier ( multipliera) and their (relevancea) and their relevancein the efficiency in the e ﬃof ciencythe circuit of the(b). circuitThe values (b). of The the components values of the are: components 𝐿 = 1.30 nH, are: CL v == 0.101.30 pF, nH, 𝐿 = 4.3 nH, 𝐶 = 0.19 pF, 𝐿 = 8.2 nH, 𝐶 = 33 pF, 𝐿 = 0.16 nH, 𝐶 = 0.75 pF, and 𝑅 = Cp1 =0.10 pF, LL1 = 4.3 nH, Cp2 = 0.19 pF, LL2 = 8.2 nH, C = 33 pF, Lp = 0.16 nH, Cpd = 0.75 pF , and 2.34 kΩ. The input power was 𝑃 = 0 dBm. Black and green dashed lines overlap. RL = 2.34 kΩ. The input power was Pin = 0 dBm. Black and green dashed lines overlap.

(a)

Sensors 2019, 19 FOR PEER REVIEW 10

on the CW multiplier, and Figure 12b shows one on the half-wave rectifier. The minimum deviation observed in both figures between the nominal simulation and the measurement is within the variability range of the components. As observed, the frequency deviation caused by the variability of the components was much smaller than the one caused by the parasitics in Figures 10 and 11. It can be noticed in Figure 12 that the half-wave rectifier is more sensitive to deviation in the

components than the CW multiplier. This is due to variations in the capacitor C′ in the L network of the half-wave rectifier. It is worth noticing that, in general terms, the most harmful parasitics are associated with lumped elements and not with the PCB. Even in the worst scenario, the CW multiplier, the effect of the vias was not so important and easily neutralized with the circuit model. A particularly important conclusion can be extracted: despite us using a perforated PCB (perfboard), considered a low-quality board in RF, its parasitics are not especially harmful at these frequencies. Therefore, if carefully chosen, low-quality RF PCBs can be utilized at frequencies below 1 GHz in order to ease the design and reduce costs of the rectifier stage in a harvesting system.

(a)

(b)

Figure 10. Model for the parasitic elements in the Cockcroft–Walton multiplier (a) and their relevance

in the efficiency of the circuit (b). The values of the components are: 𝐿 = 1.30 nH, C = 0.10 pF, Sensors 𝐿2019 =, 19 4.3, 4939 nH, 𝐶 = 0.19 pF, 𝐿 = 8.2 nH, 𝐶 = 33 pF, 𝐿 = 0.16 nH, 𝐶 = 0.75 pF, and 𝑅 10= of 16 2.34 kΩ. The input power was 𝑃 = 0 dBm. Black and green dashed lines overlap.

Sensors 2019, 19 FOR PEER REVIEW 11 (a)

(b)

Figure 11. ModelModel for for the the parasitic parasitic elements elements in in the the half–wave test half–wave rectifier rectiﬁer (a) and (a their) and relevance their relevance in the = = efficiencyin the eﬃ ciencyof the ofcircuit the circuit(b). The (b ).values The valuesof the components of the components are: 𝐿 are: = 1.20Lv0 nH,1.20 C nH= ,2.7CL0 pF, 𝐿2.7 pF =, = = = = = = = L 0.38p0 1 nH,0.38 𝐿nH =, L47L0 nH,47 𝐶nH , =Cp0 0.140.14 pF,pF 𝐶,Cpd = 0.750.75 pF,pF 𝐶, C =0 2727 pF,pF, 𝐿Lp0 2 = 0.04 nHnH,, andand 𝑅RL0 = 8 kkΩ.Ω. = The input power was P𝑃in =0 0 dBm. dBm. Black Black and and green green dashed dashed lines lines overlap. overlap.

The contribution of each parasite to the total displacement has been quantified, and some conclusions were extracted. In both cases, the contribution of the parasitic inductance associated with the capacitors (green dashed line) was completely negligible. On the other hand, the parasitic shunt capacitance Cpd associated with the diode package (red dashed line) was the most harmful element, with a total contribution over of 64% to the total frequency displacement in both circuits. In that sense, recent works have shown the benefits of two-dimensional materials, e.g., MoS2 (molybdenum disulfide) [23,24], being applied to RF electronics. In particular, [24] presents a MoS2-based Schottky diode used as a rectifier in a RF energy harvesting system. To explain the different behavior of traditional Schottky diodes though, the junction and parasitic capacitances of this MoS -based diode 2 are in the order of 20 fF, 35 times less than those shown in Figures 10 and 11. Since the parasitics of the (a) (b) diode are the most damaging, the performance of the rectifiers could be potentially improved with the Figure 12. Monte Carlo analysis on the variability of the components in (a) the Cockcroft–Walton development of MoS2 diodes. Additionally, their cutoff frequency is also higher, which allows one multiplier and (b) the half–wave rectifier. The nominal simulation and the measurements are also to reduce losses at higher operating frequencies. As a comparison, the MoS2-based diode presented in [24plotted.] has a cutoff frequency of 10 GHz (zero external bias), while the HSMS 2822 diode utilized in this work only reaches up to 4 GHz. Table 1. SRF and parasitics of the lumped elements. The contribution of the parasitic capacitance associated with inductors in the L matching networks is represented in blue in FiguresModel 10 b and 11b.Value In the caseSRF of (GHz) the CW Parasitic multiplier (Figure 10b), the frequency displacement4,841,372 they cause (Fair-Rite) (9.67%) is lower 33 nH compared 1.50 to other parasitic 0.34 pF terms, since the SRFs of the 4.3 nH and 8.2 nH106–909 inductors (Murata) (see Table 1) are 8.2 large. nH In addition, 4.00 the contribution 0.19 pF to the frequency displacement of the parasitic795–8290 inductance (TDK) associated 4.3 nH with via 7.64 holes (yellow 0.10 pF curve in Figure 10b) is higher in this case, 22.25%.464–6773 On the (AVX) other hand, Figure 33 pF 11 b shows 2.20 that the contribution, 0.16 nH in the half-wave rectifier, of the parasitic532–2945 capacitance (TE Connect.) associated 47 with nH the inductor 1.96 in the 0.14L matching pF network (blue CW160,808 (Bourns) 27 nH 2.10 0.21 pF 2,310,325 (Multicomp) 2.7 pF 4.97 0.38 nH ATC 500S (ATC) 4.7 pF 8.32 0.078nH 2,809,454 (Kemet) 27 pF 4.84 0.040 nH

5.3. Final Circuits With the use of the circuit model that contemplates the effect of the parasitics, the CW multiplier and the half-wave rectifier were redesigned to center their operation frequency at 870 MHz. Figures 13 and 14 show the parasitic model of the final circuits. The frequency displacement caused by the parasitic elements is noticeable: more than 700 MHz from the ideal response. Again, the most

Sensors 2019, 19, 4939 11 of 16 Sensors 2019, 19 FOR PEER REVIEW 11 curve), is appreciable—26.57%. However, the contribution of the parasitic inductance associated with the via holes (yellow curve) is less, 9.05%. As a comparison between both circuits, the inductor used in the L network of the half-wave rectifier possesses a lower SRF than the inductors of the CW multiplier (see Table1). Thus, the parasitics of the latter are less harmful. Conversely, the contribution of the parasitic inductance associated with via holes is more prominent in the CW multiplier, despite its value being approximately a third of the inductance LL1 and a sixth of LL2. However, since the parasitic capacitors Cp1 and Cp2 may be neglected in this circuit, there would be three parasitic inductances Lv in series, and the sum of their values (3 1.3 nH) is of the order of L = 4.3 nH. × L1 Figure 12 presents a Monte Carlo analysis on the effect of the variability of the components on the circuit efficiency. The analysis was applied to the CW multiplier and half-wave rectifier of Figures 10 and 11, respectively, after all the parasitics were included in the model. Capacitors (C, C0, and CL0), inductors (LL1, LL2, and LL0) and loads (RL and RL0) were assumed to follow a Gaussian distribution of standard deviation 5% from their nominal values. Figure 12a presents the Monte Carlo ± analysis on the CW multiplier, and Figure 12b shows one on the half-wave rectifier. The minimum deviation observed in both figures between the nominal(b) simulation and the measurement is within the variabilityFigure range 11. Model of the for components. the parasitic Aselements observed, in the the half–wave frequency rectifier deviation (a) and caused their byrelevance the variability in the of the componentsefficiency of wasthe muchcircuit smaller(b). The thanvalues the of one the caused components by the are: parasitics 𝐿 = 1.20 in Figures nH, C = 10 2.7 and pF, 11 𝐿. It can= be noticed 0.38 in FigurenH, 𝐿 =12 that47 nH, the 𝐶 half-wave = 0.14 pF, rectifier 𝐶 = is more0.75 pF, sensitive 𝐶 = 27 to pF, deviation 𝐿 = 0.04 in the nH, components and 𝑅 = 8 thankΩ. the CW multiplier.The input power This iswas due 𝑃 to = variations 0 dBm. Black in the and capacitor green dashedCL0 in lines the Loverlap.network of the half-wave rectifier.

(a) (b)

FigureFigure 12.12. Monte Carlo analysis on the variability of the components in (a) thethe Cockcroft–WaltonCockcroft–Walton multipliermultiplier andand ( b()b the) the half–wave half–wave rectifier. rectifier. The The nominal nominal simulation simulation and the and measurements the measurements are also are plotted. also plotted. It is worth noticing that, in general terms, the most harmful parasitics are associated with lumped elements and not with the PCB.Table Even 1. SRF in and the worstparasitics scenario, of the lumped the CW elements. multiplier, the effect of the vias was not so important and easily neutralized with the circuit model. A particularly important conclusion Model Value SRF (GHz) Parasitic can be extracted: despite us using a perforated PCB (perfboard), considered a low-quality board in RF, its parasitics are not especially4,841,372 harmful (Fair-Rite) at these frequencies. 33 nH Therefore, 1.50 if carefully 0.34 pF chosen, low-quality RF PCBs can be utilized106–909 at frequencies (Murata) below 1 GHz 8.2 nH in order to 4.00 ease the design 0.19 pF and reduce costs of the rectifier stage in a harvesting795–8290 system. (TDK) 4.3 nH 7.64 0.10 pF 464–6773 (AVX) 33 pF 2.20 0.16 nH 5.3. Final Circuits 532–2945 (TE Connect.) 47 nH 1.96 0.14 pF CW160,808 (Bourns) 27 nH 2.10 0.21 pF With the use of the circuit model that contemplates the effect of the parasitics, the CW 2,310,325 (Multicomp) 2.7 pF 4.97 0.38 nH multiplier and the half-wave rectifier were redesigned to center their operation frequency at 870 MHz. ATC 500S (ATC) 4.7 pF 8.32 0.078nH Figures 13 and 14 show the parasitic model of the final circuits. The frequency displacement caused 2,809,454 (Kemet) 27 pF 4.84 0.040 nH by the parasitic elements is noticeable: more than 700 MHz from the ideal response. Again, the most damaging parasitic contribution comes from the shunt capacitance of the diode. The parasitic 5.3. Final Circuits capacitance of the inductor had a bigger impact on the performance of the final circuits than for the test circuitsWith the since use theof the operating circuit model frequency that wascontemplates higher (900 the MHz effect versus of the 600 parasitics, MHz). the CW multiplier and the half-wave rectifier were redesigned to center their operation frequency at 870 MHz. Figures 13 and 14 show the parasitic model of the final circuits. The frequency displacement caused by the parasitic elements is noticeable: more than 700 MHz from the ideal response. Again, the most

Sensors 2019, 19 FOR PEER REVIEW 12 damaging parasitic contribution comes from the shunt capacitance of the diode. The parasitic capacitance of the inductor had a bigger impact on the performance of the final circuits than for the test circuits since the operating frequency was higher (900 MHz versus 600 MHz). Sensors 2019, 19, 4939 12 of 16 A slight difference in amplitude existed between the simulated and measured efficiencies in Figures 13 and 14. In order to study the cause of this difference, a Monte Carlo analysis was performedA slight on dithefference variability in amplitude of the components. existed between Capacitors, the simulatedinductors and and the measured load were effi assumedciencies into Figuresbe random 13 and variables 14. In orderthat follow to study a Gaussian the cause distribution of this difference, of standard a Monte deviation Carlo analysis 5% from was their performed nominal onvalues. the variability As seen in of Figure the components. 15, the measurement Capacitors, inductorscurve fits and within the loadthe selected were assumed variability to be range random in variablessimulation. that As follow a result, a Gaussianthe difference distribution in efficiency of standard could be deviation explained 5% by fromthe effect their of nominal the component values. Asvariability. seen in Figure 15, the measurement curve fits within the selected variability range in simulation. As a result,Figure the16 direpresentsfference inthe effi efficienciesciency could of beboth explained circuits by(see the their effect schematic) of the component as a function variability. of the inputFigure power. 16 representsAs it can thebe eseen,fficiencies the ofefficiency both circuits rapidly (see drops their schematic) below 5% as due a function to the of frequency the input power.displacement As it can the beparasitics seen, the cause. efficiency After rapidly including drops them below in our 5% circuit due to model, the frequency the rectifier displacement efficiency therose parasitics to over 30% cause. in both After circuits, including which them is appr inoximately our circuit twice model, the thevalues rectifier (15%–20%) efficiency typically rose to shown over 30%in the in literature both circuits, [10,12,13]. which The is approximatelynonlinearity of twiceboth circuits the values is appreciated (15%–20%) in typically Figure 16. shown In a inlinear the literaturescheme, the [10 ,efficiency12,13]. The curve nonlinearity would be of completely both circuits flat. is appreciated However, the in Figure efficiency 16. In response a linear scheme,is flatter thefor ethefficiency half–wave curve rectifier would becompared completely to the flat. CW. However, This implies the effi thatciency theresponse Cockcroft–Walton is flatter for multiplier the half–wave has a rectifierhigher nonlinear compared dependence to the CW. This with implies respect that to the Cockcroft–Waltoninput power, compared multiplier to the has half–wave a higher nonlinear rectifier. dependenceAdditionally, with there respect was toa drop the input in the power, efficiency compared of both to the circuits half–wave above rectifier. 13 dBm. Additionally, The diodes there are wassaturated a drop by in high the einputfficiency powers of both and circuits the performanc above 13 dBm.e of the The rectifiers diodes aredegrade. saturated The bydrop high is inputmore powerspronounced and the in performancethe case of the of thehalf–wave rectifiers rectifier degrade. (red The curve) drop due is more to the pronounced non-linearity in the effect case in of the half–wavecircuit. rectifier (red curve) due to the non-linearity effect in the circuit.

(a)

(b)

FigureFigure 13.13. Model for the parasitic elements in the ﬁnalfinal Cockcroft–Walton multiplier (a) andand theirtheir relevancerelevance inin the the e ﬃefficiencyciency of of the the circuit circuit (b). ( Theb). The values values of the of components the components are: L vare:= 1.30𝐿 nH = 1.30, Cp nH,= 4.7 CpF =, L 4.7p1 =pF,0.078 LnH =, 0.078Cp1 = nH,0.10 CpF , =LL 0.101 = 4.3pF,nH 𝐿, C =p2 4.3= nH,0.19 pF𝐶, L =L2 0.19= 8.2 pF,nH 𝐿, C = =33 8.2pF nH,, L p 𝐶= 0.16 = 33nH pF,, C𝐿pd == 0.75 0.16 pF, nH, and 𝐶R =L = 0.752.34 pF, kΩ and. The 𝑅 input = 2.34 power kΩ. was TheP inputin = 0 power dBm. was 𝑃 = 0 dBm.

Sensors 2019, 19, 4939 13 of 16 SensorsSensors 2019 2019, 19, 19 FOR FOR PEER PEER REVIEW REVIEW 1313

(a(a) )

(b(b) )

FigureFigureFigure 14. 14. Model14. Model Model for for for the the the parasiticparasitic parasitic elements elementselements in in inthe the the final final final half-wave half-wave half-wave rectifierrectifier rectifier ((aa)) andand (a their)their and relevancerelevance their relevance inin thethe efficiency efficiency of of the the circuit circuit ( b(b).). The The values values of of the the components components are:are: 𝐿𝐿== 1 1 nH, nH, CC = = 4.74.7 pF,pF, 𝐿𝐿 == in the efficiency of the circuit (b). The values of the components are: Lv0 = 1 nH, C0 = 4.7 pF, 0.078 nH, 𝐿 = 27 nH, 𝐶 = 0.21 pF, 𝐶 = 0.75 pF, 𝐶 = 27 pF, 𝐿 = 0.04 nH, and 𝑅 =L 8 kΩ. = 0.078 nH, 𝐿 = 27= nH, 𝐶 = 0.21= pF, 𝐶 = 0.75= pF, 𝐶 = =27 pF, 𝐿 = 0.04= nH, and 𝑅 = 8 kΩ.= Lp0 1 0.078 nH, LL0 27 nH, Cp0 0.21 pF, Cpd 0.75 pF, C0 27 pF, Lp0 2 0.04 nH, and RL0 8 kΩ. TheThe input input power power was was 𝑃 𝑃 = = 0 0 dBm. dBm. The input power was Pin = 0 dBm.

(a(a) ) ((bb))

FigureFigureFigure 15. 15. 15.Monte Monte Monte CarloCarlo Carlo analysis analysisanalysis onon on thethe the variabilityvariability variability ofof thethe of componentscomponents the components inin thethe final infinal the circuits:circuits: ﬁnal (( circuits:aa)) Cockcroft–Walton multiplier and (b) half-wave rectifier. The nominal simulation and the (a) Cockcroft–WaltonCockcroft–Walton multiplier multiplier and and (b ()b )half-wave half-wave rectifier. rectiﬁer. The Thenominal nominal simulation simulation and the and the Sensorsmeasurements 2019, 19 FOR arePEER also REVIEW plotted. 14 measurementsmeasurements are are also also plotted. plotted.

Figure 16.FigureEﬃ 16.ciency Efficiency (measured (measured at 870at 870 MHz) MHz) as as a a function function of the input input power power in inthe the CW CW multiplier multiplier (blue) and(blue) the and half-wave the half-wave rectiﬁer rectifier (red). (red).

5.4. Performance Comparison of Passive Rectifiers Finally, Table 2 summarizes a performance comparison among previous rectifier designs published in the literature [25–31]. For a fair comparison, only passive rectifiers that operate with an input power close to 0 dBm (1 mW) were considered. Note that active rectifiers are able to reach efficiency values of 75%–80%. However, they are not suitable for energy harvesting, and hence, were not considered in the study, since they need an external power supply. Most of the passive implementations presented make use of half-wave and Cockcroft–Walton schemes, as they usually offer the least losses by using the minimum number of diodes. To the best of our knowledge, the highest efficiency found in the literature (from a passive rectifier) was recently presented in [29], reaching a value of 60%. Conversely, the vast majority of works present low rectifier efficiencies, close to 20% or even much lower in some cases. As a consequence, the detailed study on the parasitic effects presented in this work could help to significantly improve the performance of future rectifier circuits and RF energy harvesting systems.

Table 2. Performance comparison of passive rectifiers.

Input Power Circuit Efficiency Ref. Freq. (GHz) Rectifier Circuit (dBm) (%) [10] − Half–Wave 4 20 [25] 2.4 CW 0 21 [26] 0.95 CMOS 0 9 [27] − CW 0 21 [28] 0.87 CW 0 30 [29] 0.85 CW 0 60 [30] 2.4 Half–Wave 0 14 2.4 36 [31] Full–Wave 0 5.5 5 CW 30 This Work 0.87 0 Half-Wave 27.5

6. Conclusions This work presents guidelines for the design of efficient rectifier circuits in RF energy harvesting. Some advice was given in order to face the problems associated with the nonlinearity and parasitic elements of the circuits. Without loss of generality, two different configurations were tested: a CW

multiplier and a half-wave rectifier. For a given load Z, it was shown that there is an optimal source impedance Z that maximizes the rectifier efficiency, which was used to design an optimal matching circuit. Subsequently, the contribution of each parasitic element to the total frequency displacement

Sensors 2019, 19, 4939 14 of 16

5.4. Performance Comparison of Passive Rectifiers Finally, Table2 summarizes a performance comparison among previous rectifier designs published in the literature [25–31]. For a fair comparison, only passive rectifiers that operate with an input power close to 0 dBm (1 mW) were considered. Note that active rectifiers are able to reach efficiency values of 75%–80%. However, they are not suitable for energy harvesting, and hence, were not considered in the study, since they need an external power supply.

Table 2. Performance comparison of passive rectiﬁers.

Ref. Freq. (GHz) Rectiﬁer Circuit Input Power (dBm) Circuit Eﬃciency (%) [10] Half–Wave 4 20 − [25] 2.4 CW 0 21 [26] 0.95 CMOS 0 9 [27] CW 0 21 − [28] 0.87 CW 0 30 [29] 0.85 CW 0 60 [30] 2.4 Half–Wave 0 14 2.4 36 [31] Full–Wave 0 5.5 5 CW 30 This Work 0.87 0 Half-Wave 27.5

Most of the passive implementations presented make use of half-wave and Cockcroft–Walton schemes, as they usually offer the least losses by using the minimum number of diodes. To the best of our knowledge, the highest efficiency found in the literature (from a passive rectifier) was recently presented in [29], reaching a value of 60%. Conversely, the vast majority of works present low rectifier efficiencies, close to 20% or even much lower in some cases. As a consequence, the detailed study on the parasitic effects presented in this work could help to significantly improve the performance of future rectifier circuits and RF energy harvesting systems.

6. Conclusions This work presents guidelines for the design of efficient rectifier circuits in RF energy harvesting. Some advice was given in order to face the problems associated with the nonlinearity and parasitic elements of the circuits. Without loss of generality, two different configurations were tested: a CW multiplier and a half-wave rectifier. For a given load ZL, it was shown that there is an optimal source impedance Zs that maximizes the rectifier efficiency, which was used to design an optimal matching circuit. Subsequently, the contribution of each parasitic element to the total frequency displacement was quantified and the most harmful parasitics were identified. In summary, the following conclusions have been extracted from the analyses:

1. The most harmful parasitics come from the components and not from the PCB. Therefore, if carefully chosen, cheaper PCBs can be utilized in order to reduce costs. 2. Although the diode was known to be the limiting component in terms of losses, this work has demonstrated that it also causes a large deviation with respect to the expected frequency response. Actually, it has the most harmful parasitic element, contributing two-thirds of the total frequency displacements in both Cockcroft–Walton and half–wave circuits. In that sense, future MoS2 diodes could potentially help to improve the efficiency of rectifier circuits, since their parasitics are shown to be very low [24] compared to traditional Schottky diodes. 3. The parasitic inductance associated with the capacitors is completely negligible. This fact allows one to use cheaper capacitors and reduce costs. It also allows one to use higher values of the capacitor in the rectifier stage, in order to reduce the DC output ripple when feeding the sensor. Note that the choice of this capacitor is a trade-off between the output ripple of the circuit, and Sensors 2019, 19, 4939 15 of 16

its self-resonant frequency (SRF). The higher the value of the capacitor is, the lower the output ripple and the higher the parasitics. However, they do not aﬀect the behavior of the circuit.

Finally, the circuit model of the parasitic elements was used to redesign both circuits, without considering the parasitics. The efficiency did not exceed the 5% in both circuits. After modeling them, the efficiency was shown to be over the 30%, twice the value compared to the passive rectifiers typically shown in the literature.

Author Contributions: A.A.-A. designed, simulated, manufactured and measured the Cockcroft-Walton multiplier and wrote the document. J.M.-N. designed, simulated, manufactured and measured the half-wave rectifier. J.E. helped with modeling the parasitic elements and creating the circuit models. J.M.F.-G. and P.P. supervised the whole study. All the authors participated in revising the article. Funding: This work was supported in part by the Spanish Research and Development National Program under projects TIN2016-75097-P, TEC2017-85529-C3-1-R and RTI2018-102002-A-I00. Conflicts of Interest: The authors declare no conflict of interest.

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