An E-Band 21-Db Variable-Gain Amplifier with 0.5-V Supply in 40

Article An E-Band 21-dB Variable-Gain Ampliﬁer with 0.5-V Supply in 40-nm CMOS

Gibeom Shin, Kyunghwan Kim , Kangseop Lee , Hyun-Hak Jeong and Ho-Jin Song *

Department of Electronic and Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang 37673, Korea; [email protected] (G.S.); [email protected] (K.K.); [email protected] (K.L.); [email protected] (H.-H.J.) * Correspondence: [email protected]

Abstract: This paper presents a variable-gain amplifier (VGA) in the 68–78 GHz range. To reduce DC power consumption, the drain voltage was set to 0.5 V with competitive performance in the gain and the noise figure. High-Q shunt capacitors were employed at the gate terminal of the core transistors to move input matching points for easy matching with a compact transformer. The four stages amplifier fabricated in 40-nm bulk complementary metal oxide semiconductor (CMOS) showed a peak gain of 24.5 dB at 71.3 GHz and 3-dB bandwidth of more than 10 GHz in 68–78 GHz range with approximately 4.8-mW power consumption per stage. Gate-bias control of the second stage in which feedback capacitances were neutralized with cross-coupled capacitors allowed us to vary the gain by around 21 dB in the operating frequency band. The noise figure was estimated to be better than 5.9 dB in the operating frequency band from the full electromagnetic (EM) simulation.

Keywords: variable-gain amplifier (VGA), E-band; variable-gain; low power consumption; compact layout Citation: Shin, G.; Kim, K.; Lee, K.; Jeong, H.-H.; Song, H.-J. An E-Band 21-dB Variable-Gain Amplifier with 0.5-V Supply in 40-nm CMOS. 1. Introduction Electronics 2021, 10, 804. For the past few years, automotive radar sensing systems have been massively stud- https://doi.org/10.3390/ ied for autonomous cars and relative applications. In addition, a vehicle-to-everything electronics10070804 (V2X) system connecting vehicles with vehicles, pedestrians, infrastructure, and networks is believed to another essential technology for future intelligent vehicle applications. Academic Editor: Egidio Ragonese Most recently, unified V2X and radar systems operating in E-band (60 GHz–90 GHz) allocated for radar sensing have been reported [1,2]. Received: 26 February 2021 The unified V2X and radar system demands more advanced radio frequency (RF) Accepted: 25 March 2021 Published: 29 March 2021 frontends to accommodate all requirements for each operation modes. Particularly, receiver frontends need to have very high sensitivity for the sensing mode and large gain tunability

Publisher’s Note: MDPI stays neutral for the data link mode. In addition, massive phased-array configuration [3] at mm-wave with regard to jurisdictional claims in frequencies requires all function blocks to consume less energy with compact occupying published maps and institutional affil- area even for variable-gain amplifiers (VGAs). Obviously, large operating bandwidth iations. performance is mandatory. This paper presents a variable-gain amplifier (VGA) fabricated in 40-nm CMOS technology in E-band for the unified V2X and radar application. As shown in Figure1, there are several methods to tune amplifier gain such as the attenuator control technique [4–6], current steering technique [7–11], and digital switching technique [12–14]. Insertion of an attenua- Copyright: © 2021 by the authors. Licensee MDPI, Basel, Switzerland. tor between constant gain blocks provides reliable gain control and wideband operation at This article is an open access article the cost of relatively high loss and degradation in the noise performance, particularly in the distributed under the terms and millimeter-wave frequency band. The current steering technique has the advantages of wide conditions of the Creative Commons and linear gain control range, low dc power, and simple configuration, but the operating Attribution (CC BY) license (https:// bandwidth would be limited by the current steering circuits. Despite the merit for accurate gain creativecommons.org/licenses/by/ control, the digital switching techniques replying on a lot of transistors for switching are not 4.0/). suitable for low power and beamforming transceivers. In this paper, we adopt a bias current

Electronics 2021, 10, 804. https://doi.org/10.3390/electronics10070804 https://www.mdpi.com/journal/electronics Electronics 2021, 2, x FOR PEER REVIEW 2 of 11

Electronics 2021, 10, 804 2 of 11 of transistors for switching are not suitable for low power and beamforming transceivers. In this paper, we adopt a bias current control technique [15,16] that directly adjusts the transconductancecontrol (gm technique) of the transistor [15,16] that by directlyadaptively adjusts controlling the transconductance the gate bias (ofgm an) of am- the transistor by plifying stage.adaptively It is advantageous controlling for the wide gate gain bias range, of an amplifying low power stage. operation, It is advantageous compact de- for wide gain sign, and widerange, bandwidth. low power However, operation, when compact gm varies, design, input and and wide output bandwidth. impedances However, of an when gm varies, amplifier varyinput a lot. and Thus, output it is hard impedances to maintain of an good amplifier impedance vary a matching lot. Thus, for it iswhole hard gain to maintain good range. To dealimpedance with this matchingissue, we for employed whole gain the range. capacitive To deal cross-coupling with this issue, neutralization we employed the capacitive technique to improvecross-coupling reverse neutralization isolation of techniqueeach stage to of improve the amplifier reverse [17]. isolation In Section of each 2, stage we of the ampli- present the VGAfier [17design,]. In Section followed2, we by present the meas theurement VGA design, results followed of the by VGA the measurementin Section 3. results of the Section 4 concludesVGA in this Section paper.3. Section 4 concludes this paper.

Figure 1. FourFigure topologies 1. Four of topologies variable-gain of variable-gain ampliﬁers (VGAs) amplifiers utilized (VGAs) in millimeter-wave. utilized in millimeter-wave. (a) Attenuator (a control) At- technique, (b) current steeringtenuator technique, control technique, (c) digital ( switchingb) current technique, steering technique, and (d) bias (c) currentdigital switching control technique. technique, and (d) bias current control technique.

2. Design Approach2. Design Approach Figure 2 showsFigure the circuit2 shows schematic the circuit of the schematic 4-stage differential of the 4-stage VGA. differential In this work, VGA. we In this work, aimed to havewe a compact aimed to and have low a power compact consumption and low power variable consumption amplifier for variable the unified amplifier for the V2X-radar phased-arrayunified V2X-radar receiver phased-array applications in receiver E-band. applications For the low in DC E-band. power For require- the low DC power ment, we reducedrequirement, the drain we voltage reduced (VD) the down drain to voltage 0.5 V [18]. (VD) In down order toto 0.5estimate V [18]. the In per- order to estimate formance degradationthe performance caused degradationby the lowered caused VD, bya simple the lowered simulation VD, a for simple maximum simulation gain for maximum gain and minimum noise figure (NF ) was conducted; the results are shown in Figure3. and minimum noise figure (NFmin) was conducted;min the results are shown in Figure 3. Note that the drainNote current that was the fixed drain to current 10 mA wasfor an fixed N-MOSFET to 10 mA differential for an N-MOSFET pair in this differential calcu- pair in this lation. When calculation.VD decreased When from VD 1 V decreased to 0.5 V, fromthe gain 1 V and to 0.5 the V, noise the gain figure and degraded the noise figureby degraded by approximately 1.8 dB and 0.3 dB, respectively. Those are believed acceptable for the approximately 1.8 dB and 0.3 dB, respectively. Those are believed acceptable for the ben- benefit in the DC power consumption reduction by half. The amplifier consists of four efit in the DC power consumption reduction by half. The amplifier consists of four stages stages of an N-MOSFET differential core to get a high gain and to decrease common mode of an N-MOSFET differential core to get a high gain and to decrease common mode noise. noise. The total gate width of the core transistors is 34.5 µm (1.5 µm × 23 fingers) and The total gate width of the core transistors is 34.5 μm (1.5 μm × 23 fingers) and impedance impedance matching was achieved using low-k transformers for wideband operation. matching was achieved using low-k transformers for wideband operation.

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Figure 2. SchematicFigureFigure of 2.the Schematic 2. 4-stageSchematic cascade of the of the 4-stage differential 4-stage cascade cascade VGA. differential differential VGA. VGA.

Figure 3. Maximum stable/available gain (MSG/MAG) and NFmin depending on drain voltage FigureFigure 3.3. Maximum stable/availablestable/available gaingain (MSG/MAG)(MSG/MAG) and NFminmin dependingdepending on drain voltage (VD) (VD) at 77 GHz. at(VD) 77 GHz.at 77 GHz.

In the bias current control technique, when gm varies, input and output impedances InIn thethe biasbias currentcurrent controlcontrol technique,technique, whenwhen ggmm varies,varies, inputinput andand outputoutput impedancesimpedances of an amplifierofof vary an amplifier amplifier a lot. Thus, vary vary it isa alot.hard lot. Thus, to Thus, maintain it is it hard is good hard to maintain impedance to maintain good matching good impedance impedance for wholematching matching for whole for gain range. Accordingwholegain range. gain to range.Accordingthe two-port According to networthe two-port to thek theory, two-port networ input networkk theory,and output theory, input reflection and input output and coeffi- output reflection reflection coefficients are givencoefficientscients by Equations are given are given by(1) Equationsand by (2) Equations below (1) and (1) (2) and below (2) below

𝑍 −𝑍 𝑍 −𝑍𝑆𝑆Γ 𝑆 𝑆 Γ Γ = =Z 𝑆 +− Z , S S Γ Γ =IN 0 = 𝑆 + 12 21 L , (1) (1) 𝑍Γ+𝑍IN = 𝑍 +𝑍1−𝑆=SΓ11 + 1−𝑆 Γ , (1) ZIN + Z0 1 − S22ΓL 𝑍 −𝑍 𝑍 −𝑍𝑆𝑆Γ 𝑆 𝑆 Γ Γ = = 𝑆+ , (2) 𝑍 +𝑍Γ =ZOUT −1−𝑆Z0 =Γ 𝑆 + S12S21ΓS , (2) ΓOUT = 𝑍 +𝑍=S22 + 1−𝑆Γ , (2) ZOUT + Z0 1 − S11ΓS Γ Γ IN where andwhere Γare and input Γ and are output input reflection and output coefficients, reflection respectively.coefficients, respectively.Z and ZIN and where ΓIN and ΓOUT are input and output reflection coefficients, respectively. ZIN and ZOUT are inputZ andOUT are output input impedances, and output respectively,impedances, andrespectively, Z0 is the systemand Z0 impedanceis the system that impedance that Z are input and output impedances, respectively, and Z is the system impedance is constant. As OUTcan be seen, small changes in the input or output impedance0 can signifi- thatis constant. is constant. As can As be can seen, be seen,small smallchanges changes in the ininput the or input output or outputimpedance impedance can signifi- can cantly affect the reflection coefficients on the other side, particularly for high gain stage, significantlycantly affect affectthe reflection the reflection coefficients coefficients on the on other the otherside, particularly side, particularly for high for gain high stage, gain which can be a serious problem in VGAs based on the bias-control scheme. However, if stage,which which can be can a serious be a serious problem problem in VGAs in VGAs based based on the on thebias-control bias-control scheme. scheme. However, However, if S12 is low enough,S12 is suchlow enough, influences such from influences the other from port the can other be significantly port can be reducedsignificantly and reduced and if S12 is low enough, such influences from the other port can be significantly reduced and thus input and output reflection coefficients remain to S11 and S22 of the core N-MOSFETs. thusthus inputinput andand outputoutput reflectionreflection coefficientscoefficients remainremain to toS S11 and S 22 ofof the the core core N-MOSFETs. N-MOSFETs. In this work, we improve the reverse isolation by applying neutralization11 to 22core transis- InIn thisthis work,work, we we improve improve the the reverse reverse isolation isolation by by applying applying neutralization neutralization to coreto core transistors transistors of the amplifier. oftors the of amplifier. the amplifier. Neutralization has been widely employed to improve reverse isolation and gain of NeutralizationNeutralization has been been widely widely employed employed to to improve improve reverse reverse isolation isolation and and gain gain of amplifiers by amplifierseliminating by parasitic eliminating gate-drain parasitic capacitance gate-drain (C capacitancegd) of transistors (Cgd) of[15–19]. transistors This [15–19]. This of amplifiers by eliminating parasitic gate-drain capacitance (Cgd) of transistors [15–19]. unintended feedback path caused by Cgd led to an unstablegd amplifier and caused signal Thisunintended unintended feedback feedback path pathcaused caused by C by ledC gdtoled an tounstable an unstable amplifier amplifier and caused and caused signal loss and gainsignalloss reduction. and loss gain and Each reduction. gain stage reduction. of Each the amplifierstage Each stageof thewas of amplifier thecapacitively amplifier was neutralizedcapacitively was capacitively with neutralized neutralized with cross-coupling neutralization capacitor (Cnue) to cancel Cgd. Figure 4 is the small signal withcross-coupling cross-coupling neutra neutralizationlization capacitor capacitor (Cnue (C)nue to) tocancel cancel CgdC.gd Figure. Figure 44 is is the smallsmall signalsignal equivalent circuitequivalentequivalent with capacitive circuit with with neutralization capacitive capacitive neutralization considering neutralization only considering considering parasitic only gate-drain only parasitic parasitic ca- gate-drain gate-drain capacitance. Y-parameterscapacitance.pacitance. Y-parameters of Y-parameters the 2-port networkof of the the 2-port 2-portcan benetwork networkwritten can as can follows:be be written written as as follows: follows: 𝑌 =−𝑗𝜔𝐶 −𝐶 , 𝑌 =−𝑗𝜔𝐶 −𝐶, (3) (3) Y12 = −jω Cgd − Cneu , (3) 𝑌 =𝑔 − 𝑗𝜔𝐶 −𝐶 𝑌=𝑔− 𝑗𝜔𝐶 −𝐶 (4) (4)

Electronics 2021, 2, x FOR PEER REVIEW 4 of 11

Electronics 2021, 10, 804 4 of 11

Electronics 2021, 2, x FOR PEER REVIEW Equations (3) and (4) from Figure 4 show that capacitive neutralization4 of 11 can improve reverse isolation and gain [17].Y Theoretically,21 = gm − jω theCgd perfect− Cneu isolation can be implemented(4) as Cneu is equal to the Cgd. Equations (3) and (4) from Figure 4 show that capacitive neutralization can improve reverse isolation and gain [17]. Theoretically, the perfect isolation can be implemented as Cneu is equal to the Cgd.

Figure 4. Small signal equivalent circuit with capacitive neutralization.

EquationsTo verify effect (3) and of neutralization, (4) from Figure we4 show configured that capacitive a one-stage neutralization amplifier and can conducted improve reverse isolation and gain [17]. Theoretically, the perfect isolation can be implemented as a simulation as changing the value of Cneu. Figure 5 shows the simulated maximum gain Figure 4. Small signalCneu isequivalent equal to circuit the C with. capacitive neutralization. and isolation performancegd with respect to Cnue at 70 GHz. As can be seen, with the opti- To verify effect of neutralization, we conﬁgured a one-stage ampliﬁer and conducted a mum Cnue, overall gain and the isolation can be greatly improved. When Cneu equals Cgd, To verify effectsimulation of neutralization, as changing we the configured value of Cneu a .one-stage Figure5 shows amplifier the simulatedand conducted maximum gain and S12 is −39.5 dB, which is 22.1-dB lower than that with no neutralization. The gain begins to a simulation asisolation changing performance the value of withCneu. respectFigure 5 to showsC at the 70 simulated GHz. As can maximum be seen, gain with the optimum increase thanks to the effect of neutralization.nue According to equation (5), stability factor k and isolation performanceCnue, overall with gain respect and the to isolation Cnue at 70 can GHz. be greatly As can improved.be seen, with When the Copti-neu equals Cgd, S12 is inversely proportional to S12. Thus, as S12 becomes lower, k becomes greater than 1. Then, mum Cnue, overallis − gain39.5 dB,and whichthe isolation is 22.1-dB can lowerbe greatly than improved. that with no When neutralization. Cneu equals TheCgd, gain begins to the gain starts to decrease, and turns to increase as S12 rises again. When k reduces under S12 is −39.5 dB, whichincrease is thanks22.1-dB to lower the effect than ofthat neutralization. with no neutralization. According toThe equation gain begins (5), stability to factor k is 1, however, the gain decreases again. increase thanksinversely to the effect proportional of neutralization. to S12. Thus, According as S12 becomesto equation lower, (5), kstabilitybecomes factor greater k than 1. Then, is inversely proportionalthe gain starts to S12 to. Thus, decrease, as S121− and becomes| turns𝑆| − tolower,| increase𝑆| k− becomes|𝛥 as| S12 rises greater again. than When 1. Then,k reduces under 1, 𝑘= ,𝛥=𝑆𝑆 −𝑆𝑆 (5) the gain starts tohowever, decrease, the and gain turns decreases to increase again. 2as|𝑆 S12𝑆 rises| again. When k reduces under 1, however, the gain decreases again. 2 2 2 1 − |S11| − |S22| − |∆| 1−|𝑆|k =− |𝑆| − |𝛥| , ∆ = S11S22 − S12S21 (5) 𝑘= 2|S12,𝛥=𝑆S21| 𝑆 −𝑆𝑆 (5) 2|𝑆𝑆|

Figure 5. MSG/MAG, stability factor, and reverse isolation according to Cneu at 70 GHz.

In addition, the neutralization technique makes the input and output impedances

less sensitive to change of the bias voltage for gain control. Figure 6 shows the simulated Figure 5. MSG/MAG, stability factor, and reverse isolation according to Cneu at 70 GHz. Figure 5. MSG/MAG,input and stabilityoutput factor,impedances and reverse at various isolation gate according bias voltages. to Cneu at As 70 GHz.can be seen, the magnitudes of the input and output impedance variations are 24.5 Ω and 69.0 Ω, respectively, In addition, theIn neutralization addition, the neutralization technique makes technique the input makes and the output input andimpedances output impedances less when gate bias voltage is changed from 0.55 V to 0.25 V without Cneu at 73 GHz. With the less sensitive tosensitive change of to the change bias ofvoltage the bias for voltage gain control. for gain Figure control. 6 shows Figure the6 shows simulated the simulated input optimum Cneu for best isolation, however, the input and output impedance variations are input and outputand impedances output impedances at various at variousgate bias gate voltages. bias voltages. As can be As seen, can be the seen, magni- the magnitudes of reduced to 3.0 Ω and 14.9 Ω for input and output ports, respectively. These are about 87 tudes of the inputthe inputand output and output impedance impedance variations variations are 24.5 are Ω 24.5 andΩ 69.0and 69.0Ω, respectively,Ω, respectively, when gate % and 78 % reductions in the impedance variations for each port. Thus, the large imped- when gate biasbias voltage voltage is changed is changed from from 0.55 0.55V to V 0.25 to 0.25V without V without Cneu Catneu 73at GHz. 73 GHz. WithWith the the optimum ance variation can be significantly reduced with the neutralization technique, which will optimum Cneu forCneu bestfor isolation, best isolation, however, however, the input the input and andoutput output impedance impedance variations variations are are reduced to be of great help for the reliable operation of the VGA. From the full EM simulation, we reduced to 3.0 3.0Ω andΩ and 14.9 14.9 Ω forΩ forinput input and and output output ports, ports, respectively. respectively. These These are are about about 87 87 % and 78 % selected 9-fF Cneu for the reverse isolation that is the highest priority. % and 78 % reductionsreductions in inthe the impedance impedance variations variations for for each each port. port. Thus, Thus, the the large large imped- impedance variation ance variation can be signiﬁcantlysignificantly reducedreduced withwith thethe neutralizationneutralization technique, technique, which which will will be of great help be of great help for the reliable operation of the VGA. From the full EM simulation, we selected 9-fF Cneu for the reverse isolation that is the highest priority.

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Electronics 2021, 2, x FOR PEER REVIEW 5 of 11 for the reliable operation of the VGA. From the full EM simulation, we selected 9-fF Cneu for the reverse isolation that is the highest priority.

(a)

(b)

Figure 6. (a) Magnitude of input and output impedances (Zin and Zout) of a single-stage differential Figure 6. (a) Magnitude of input and output impedances (Zin and Zout) of a single-stage differential ampliﬁer core without neutralizationamplifier and (b )core with without neutralization. neutralization and (b) with neutralization.

Transformers (TFs)Transformers have been (TFs) commonly have been used commonly for impedance used matching for impedance in differen- matching in differ- tial CMOS radioential frequency CMOS integrated radio frequency circuits integrated (RFICs) [20–24]. circuits TFs (RFICs) provide [20 –compact24]. TFs lay- provide compact out compared layoutto other compared techniques to; however, other techniques; they still occupy however, large they area still in occupygeneral. large Given area in general. transistors or impedanceGiven transistors need to or be impedance matched to need 50-Ω to; the be required matched inductances to 50-Ω; the of required the TFs inductances of are determinedthe from TFs the are simple determined circuit fromtheory the and simple therefore circuit there theory is no and freedom therefore for therecom- is no freedom pact layout. Infor this compact work, we layout. introduce In this a work,small shunt we introduce capacitor a smallat the shunt gate nodes, capacitor which at the gate nodes, led small TFs requiredwhich led for small the given TFs required matching for points. the given Figure matching 7a shows points. a schematic Figure7a of shows the a schematic impedance matchingof the impedance circuit with matching a transfor circuitmer with and a a transformer shunt capacitor, and a shuntand Figure capacitor, 7b and Figure7b shows the equivalentshows thecircuit equivalent for the impedance circuit for the matching. impedance The matching. input impedance The input (Zin impedance`) and (Zin‘) and the input sourcethe impedance input source (Zs impedance) seen from (theZs) gate seen node from are the derived gate node as arefollows: derived as follows: 1 𝑍 `= , 1 (6) 𝑌 + 𝑗Z2𝜔𝐶in = , (6) Yin + j(2ωCshunt) 𝐿 𝐿 𝑍 =50+𝑗𝜔 −𝑀//L𝑗𝜔𝑀 + 𝑗𝜔 −𝑀, L (7) Z = 250 + jω 1 − M //2jωM + jω 2 − M , (7) S 2 2 where Yin is the input admittance of the amplifier core and M is mutual inductance of the where Y is the input admittance of the amplifier core and M is mutual inductance of the transformer. Assumingin conjugate impedance matching, Zin` = Zs* should be satisfied at the desired frequency.transformer. In order Assuming to verify conjugate the effectiveness impedance of matching, the shuntZ capacitor,in‘ = Zs* should we con- be satisfied at the ducted simple desiredcalculation frequency. with the In device order to parameters verify the effectivenessused in this ofwork. the shuntThe length capacitor, and we conducted simple calculation with the device parameters used in this work. The length and width of width of the MOSFET for the calculation was selected to 0.04 μm and 34.5 μm, respec- the MOSFET for the calculation was selected to 0.04 µm and 34.5 µm, respectively, which tively, which has the conductance (G) and susceptance (B) of 0.005 ℧ and 0.015 ℧, respec- has the conductance (G) and susceptance (B) of 0.005 ℧ and 0.015 ℧, respectively. L1 was tively. L1 was assumed to equal L2. Figure 7c shows the calculated secondary inductance assumed to equal L . Figure7c shows the calculated secondary inductance of the impedance of the impedance matching TF as2 a function of the shunt capacitance. This function is ob- matching TF as a function of the shunt capacitance. This function is obtained by calculating tained by calculating Zin` = Zs* with equations (6) and (7). As shown in the figure, the shunt Z ‘ = Z * with Equations (6) and (7). As shown in the figure, the shunt capacitor helps capacitor helps toin matchs the given impedance with a small TF, leading compact matching to match the given impedance with a small TF, leading compact matching circuit. It is circuit. It is assumed that this approach would improve conduction loss and quality factor assumed that this approach would improve conduction loss and quality factor of the TF of the TF as well. In this work, an 8-fF capacitor is added in the core, and the layout is shown in Figure 8. Based on the results shown in Figure 7c, the occupied area of the matching TF was reduced by approximately 30 %. In the proposed amplifier, values of the coupling coefficient (k) of the transformers were selected to be k1 = −0.63, k2 = −0.24 and

Electronics 2021, 10, 804 6 of 11

as well. In this work, an 8-fF capacitor is added in the core, and the layout is shown in Electronics 2021, 2, x FOR PEER REVIEW Figure8. Based on the results shown in Figure7c, the occupied area of the6 of matching 11 TF was reduced by approximately 30 %. In the proposed amplifier, values of the coupling coefficient (k) of the transformers were selected to be k1 = −0.63, k2 = −0.24 and k3 = −0.53. A low-k k3 = −0.53. A low-transformerk transformer that that assisted assisted wide wide bandwidth bandwidth design design was was used used in in an an inter-stage inter- impedance stage impedancematching matching network. network. Thick Thick metal metal layer layer waswas used for signal signal lines lines to to reduce reduce signal losses. signal losses. AA lower lower metal metal layer layer at at the the gate gate paths paths was was used used to to make make input input impedance impedance of of the amplifier the amplifier corecore capacitive capacitive and and thus thus easy easy to impedance-match. ItIt shouldshould be be noted noted here here that large shunt that large shuntcapacitors capacitors may may limit limit the the gain gain and and the the noise noiseperformance performanceof of thethe amplifieramplifier because of the because of the limited quality factorfactor ofof thethe capacitor.capacitor. In this work, 8-fF capacitance is selectedse- based on lected based onthe the available available space space and and the the performance performance degradation. degradation. Quality Quality factor factor of the of shunt capacitor the shunt capacitorwasaround was around 20 at 7320 GHzat 73from GHz the from full the EM full simulation. EM simulation. As shown As inshown Figure in3 , the gain and Figure 3, the gainthe and noise the degradation noise degradation due to thedue 8-fF to the capacitor 8-fF capacitor were estimated were estimated to be around to 0.6 dB and be around 0.6 dB0.3 and dB, respectively.0.3 dB, respectively.

(a) (b)

(c)

Figure 7. (aFigure) A transformer-based 7. (a) A transformer-based impedance impedance matching network. matching (b network.) A simple (b equivalent) A simple circuitequivalent of the circuit matching of network is presentedthe by matching a half circuit network for easy is presented analysis. by (c) a The half calculated circuit for secondary easy analysis. inductance (c) The calculated according secondary to coupling coefﬁcient inductance according to coupling coefficient against Cshunt at 73 GHz. against Cshunt at 73 GHz. In addition, core transistors were weakly degenerated with the thick metal intercon- nections, of which inductance (Ldegen) was around 1.5 pH. This moved the conjugate input matching point to the middle of the noise circle, resulting in the return loss less than 13 dB even with the noise matching condition.

Figure 8. 3D view of the amplifier core. Electronics 2021, 2, x FOR PEER REVIEW 6 of 11

k3 = −0.53. A low-k transformer that assisted wide bandwidth design was used in an inter- stage impedance matching network. Thick metal layer was used for signal lines to reduce signal losses. A lower metal layer at the gate paths was used to make input impedance of the amplifier core capacitive and thus easy to impedance-match. It should be noted here that large shunt capacitors may limit the gain and the noise performance of the amplifier because of the limited quality factor of the capacitor. In this work, 8-fF capacitance is selected based on the available space and the performance degradation. Quality factor of the shunt capacitor was around 20 at 73 GHz from the full EM simulation. As shown in Figure 3, the gain and the noise degradation due to the 8-fF capacitor were estimated to be around 0.6 dB and 0.3 dB, respectively.

(a) (b)

(c) Electronics 2021, 10, 804 Figure 7. (a) A transformer-based impedance matching network. (b) A simple equivalent circuit7 of 11of the matching network is presented by a half circuit for easy analysis. (c) The calculated secondary inductance according to coupling coefficient against Cshunt at 73 GHz.

Electronics 2021, 2, x FOR PEER REVIEW 7 of 11

In addition, core transistors were weakly degenerated with the thick metal intercon- nections, of which inductance (Ldegen) was around 1.5 pH. This moved the conjugate input matching point to the middle of the noise circle, resulting in the return loss less than 13 dB even with the noise matching condition. FigureFigure 8. 8.3D 3D viewview ofof thethe amplifieramplifier core. core. 3. Measurement Results 3. Measurement Results TheThe four-stage four-stage variable-gain variable-gain VGA VGA was was fabricated fabricated in in the the 40-nm 40-nm CMOS CMOS technology, technology, andand the the microphotograph microphotograph is is shown shown in in Figure Figure 99.. The active areaarea ofof thethe proposedproposed amplifieramplifier isis 668 668 μµm × 159159 μµmm without without DC DC and and RF RF pads. pads. The The tota totall drain drain current current was was 38.2 38.2 mA mA from 0.5-V0.5-V supply supply at the peak gain condition.condition. RFRF measurementmeasurement was was performed performed with with an an on-wafer on-wa- ferprobing probing system system and and a 110-GHz a 110-GHz vector vector network networ analyzer.k analyzer. The The effect effect of the of the RF padsRF pads was was not notde-embedded de-embedded here. here. Figure Figure 10 shows 10 shows measured measured small small signal signal S-parameters S-parameters of the of amplifier. the amplifier.The VGA The achieved VGA achieved peak gain peak of gain 24.5 of dB 24.5 at 71.3 dB GHzat 71.3 with GHz 3-dB with bandwidth 3-dB bandwidth of around of around10 GHz 10 in GHz 68 GHz–78 in 68 GHz–78 GHz span.GHz span. Thanks Than toks the to inductivethe inductive degeneration, degeneration, good good input in- putreturn return loss loss less less than than−10 − dB10 dB was was achieved achieved in thein the operating operating frequency frequency band band even even with with the thenoise noise matching. matching.

FigureFigure 9. 9. PhotographPhotograph of of the the fabricated fabricated four-s four-stagetage variable-gain variable-gain amplifier amplifier (VGA). In this paper, we control inter-stage gate bias voltages to tune the amplifier gain. In this measurement, to get a variable gain, we controlled the second gate bias voltage, and the measurement results are shown in Figure 11. The peak and minimum gains were achieved with the gate voltages of 0.55 V and 0.225 V, respectively. Meanwhile, DC power consumption of the amplifier was reduced from 19.1 mW to 15.5 mW accordingly. As can be seen, S21 could be tuned by approximately 21 dB in maximum while maintaining the 3-dB bandwidth of 10 GHz. Meanwhile, return losses at input and output ports were rarely changed and remained below 10 dB approximately in overall. At 73 GHz, input and output return loss variations were around 5.4 dB and 1.9 dB, respectively.

Figure 10. Measured S-parameters of the VGA.

In this paper, we control inter-stage gate bias voltages to tune the amplifier gain. In this measurement, to get a variable gain, we controlled the second gate bias voltage, and the measurement results are shown in Figure 11. The peak and minimum gains were achieved with the gate voltages of 0.55 V and 0.225 V, respectively. Meanwhile, DC power consumption of the amplifier was reduced from 19.1 mW to 15.5 mW accordingly. As can be seen, S21 could be tuned by approximately 21 dB in maximum while maintaining the

Electronics 2021, 2, x FOR PEER REVIEW 7 of 11

3. Measurement Results The four-stage variable-gain VGA was fabricated in the 40-nm CMOS technology, and the microphotograph is shown in Figure 9. The active area of the proposed amplifier is 668 μm × 159 μm without DC and RF pads. The total drain current was 38.2 mA from 0.5-V supply at the peak gain condition. RF measurement was performed with an on-wafer probing system and a 110-GHz vector network analyzer. The effect of the RF pads was not de-embedded here. Figure 10 shows measured small signal S-parameters of the amplifier. The VGA achieved peak gain of 24.5 dB at 71.3 GHz with 3-dB bandwidth of around 10 GHz in 68 GHz–78 GHz span. Thanks to the inductive degeneration, good input return loss less than −10 dB was achieved in the operating frequency band even with the noise matching.

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Figure 9. Photograph of the fabricated four-stage variable-gain amplifier (VGA).

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3-dB bandwidth of 10 GHz. Meanwhile, return losses at input and output ports were Figurerarely 10.changed MeasuredMeasured and S-parameters remained S-parameters below of of the the 10 VGA. VGA.dB approximately in overall. At 73 GHz, input and output return loss variations were around 5.4 dB and 1.9 dB, respectively. In this paper, we control inter-stage gate bias voltages to tune the amplifier gain. In this measurement, to get a variable gain, we controlled the second gate bias voltage, and the measurement results are shown in Figure 11. The peak and minimum gains were achieved with the gate voltages of 0.55 V and 0.225 V, respectively. Meanwhile, DC power consumption of the amplifier was reduced from 19.1 mW to 15.5 mW accordingly. As can be seen, S21 could be tuned by approximately 21 dB in maximum while maintaining the

(a)

(b)

(c)

Figure 11. Measured (a) S21, (b) S11, and (c)S22 at various gate-bias voltages. The highest gain is Figure 11. Measured (a) S21,(b) S11, and (c)S22 at various gate-bias voltages. The highest gain is when VG = 0.55 V, and the lowest gain is when VG = 0.225 V. when VG = 0.55 V, and the lowest gain is when VG = 0.225 V. Table 1 summarizes the results of this work along with several prior works operating at similar frequencies. Even with low power consumption and compact layout, competitive performance in gain and tuning range was achieved. In particular, thanks to the compact matching circuit design with the optimum combination of the transformer and shunt capacitors, area reduction of 30% or more was achieved. In addition, the gain in dB per mW of around 1 was achieved by operating the amplifier with 0.5 V supply, which is superior to other prior works.

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Table1 summarizes the results of this work along with several prior works operating at similar frequencies. Even with low power consumption and compact layout, competitive performance in gain and tuning range was achieved. In particular, thanks to the compact matching circuit design with the optimum combination of the transformer and shunt capacitors, area reduction of 30% or more was achieved. In addition, the gain in dB per mW of around 1 was achieved by operating the ampliﬁer with 0.5 V supply, which is superior to other prior works.

Table 1. Comparison with variable-gain ampliﬁers (VGAs) in literature.

[5][6][9][10][11][12][15][16] This Work 55-nm 0.12-µm 65-nm 90-nm 40-nm 28-nm 28-nm 65nm 40-nm Technology BiCMOS SiGe CMOS CMOS CMOS CMOS CMOS CMOS CMOS 2-cascode 1- 5-CE + 2-current 2-cascode + 1-current Topology attenuator 2- steering+ (1-current 3-CS 4-CS 3-CS 4-CS steering + + 1-CB attenuator 1-splitting steering) 1-CS Freq. (GHz) 73.5 81 60 78 57 79 82.3 58 73 Peak gain (dB) 4.8 24 21 23 6.7 23.8 29.6 25 24.5 4.5 11.8 # 33 # 19.1 # 5.7 11.6 # 17 21.3 # Gain range (dB) 20 (19.3– (−7–4.8) (−12–21) (4.6–23.7) (1.0–6.7) (18.0–29.6) (8–25) (3.2–24.5) 23.8) >5 >5 17 18.8 11 28.3 7.5 10.4 3-dB BW (GHz) 10 (<71–>76) (<81–>86) (52–69) (68.8–87.6) (51–62) (68.1–96.4) (53.5–61) (67.8–78.2) 3-dB BW (%) > 6.8 > 6.2 28.3 24.1 19.3 12.7 34.4 12.9 14.2 NF (dB) - 4.5 7.9 5.3 5.1 4.9 6.4 4.8 4.8 (sim)

OP1dB (dBm) ------1.5 - −3.6 (sim) OIP3 (dBm) - - - 0.2 - - - - 6.5 (sim) PDC (mW) 18.4 67 11 55 12.1 30.6 31.3 47.5 19.1 VD (V) 1.6 1.6 1 1.2 1.1 0.9 0.9 1.3 0.5 Core area 0.078 1.179 0.25 * 0.573 * 0.237 ** 0.148 * 0.131 ** 0.258 * 0.106 (mm2) #: Maintaining 3-dB BW, *: chip size, including RF and DC pads, and ** estimated chip size without the pads.

4. Conclusions This paper shows a variable-gain VGA fabricated in 40-nm CMOS technology in E-band. For the low DC power requirement, we reduced the VD down to 0.5 V, resulting in unity gain in dB per mW. The high-Q shunt capacitor enabled us to achieve approximately 30% TF area reduction, resulting in a very compact chip. One of the most serious draw- backs of the gate-bias control was migrated with the cross-coupled capacitor neutralization technique. Due to the high isolation of each gain stage, the propagation of impedance mis- match with the gate-bias control was avoided. Meanwhile, the comparative performance was achieved. The presented VGA achieved peak gain of 24.5 dB at 71.3 GHz and a 3-dB bandwidth of more than 10 GHz in 68 GHz–78 GHz range with approximately 4.8-mW power consumption per stage. The 21-dB variable-gain range was obtained by tuning the second gate voltage while maintaining 3-dB Bandwidth. The VGA performed promisingly, not only in gain tuning range and bandwidth but also in area and power dissipation for the beamforming transceivers for the uniﬁed V2X and radar applications.

Author Contributions: Conceptualization, G.S. and H.-J.S.; methodology, G.S., K.L. and K.K.; validation, G.S. H.-H.J.; formal analysis, G.S. and H.-J.S.; investigation, G.S.; writing—original draft preparation, G.S.; writing—review and editing, H.-J.S.; supervision, H.-J.S.; project administra- tion, H.-J.S.; funding acquisition, H.-J.S. All authors have read and agreed to the published version of the manuscript. Electronics 2021, 10, 804 10 of 11

Funding: This work was supported by Institute of Information and communications Technology Planning and Evaluation (IITP) grant funded by the Korea government (MSIT) (IITP-2018-0-00823; investigation on future mm-Wave circuits, packages, and systems, IITP-2019-0-00060; development of 300 GHz band Tbps beamforming transceiver chip for next generation short range communication; and IITP-2019-0-00762, next-generation multistatic radar imaging system for smart monitoring). Data Availability Statement: Some of the data presented in this study are available on request from the corresponding author. Acknowledgments: The authors would like to thank Keysight Technologies, Inc. for supporting the circuit design software and measurement instruments. Conﬂicts of Interest: The authors declare no conﬂict of interest.

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