EE-612: Lecture 23: RF CMOS
Mark Lundstrom Electrical and Computer Engineering Purdue University West Lafayette, IN USA Fall 2008
NCN www.nanohub.org Lundstrom EE-612 F08 1 why analog /RF why CMOS? many applications involve analog / rf signals:
1) many natural signals are analog (sensors) 2) disk drive electronics 3) wireless receivers 4) optical receivers 5) microprocessors / memories CMOS:
1) many systems are both analog and digital 2) CMOS is the dominate technology for digital electronics 3) CMOS performance has recently become suitable for analog
Reference: B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001.
Lundstrom EE-612 F08 2 CMOS device metrics (digital)
1) on-current: ION
2) off-current: IOFF
3) subthreshold swing: S =∂(log10 I D ) ∂VGS VDS
4) device delay: τ = CGVDD ION
5) DIBL, etc.
Lundstrom EE-612 F08 3 CMOS device metrics (analog)
1) transconductance: gm =∂I D ∂VGS VDS
2) output resistance: ro =∂I D ∂VDS VGS
3) fT and fmax: fT = 12π τ
4) noise, mismatch, I D linearity, etc.
VDS
Lundstrom EE-612 F08 4 outline
1) Introduction 2) Small signal model 3) Transconductance 4) Self-gain 5) Gain bandwidth product 6) Unity power gain 7) Noise, mismatch, linearity… 8) Examples
Lundstrom EE-612 F08 5 small signal model
i = I + i D D d i g id g d iG = IG + ig C υgs gs gmυgs
s s
id ∂I D id = gmυgs gm = ≈ υgs ∂VGS VDS (quasi-static assumption)
Lundstrom EE-612 F08 6 additional parameters in the s.s. model
rg r C S gd rD
Csb Cdb
Cgb gmb
rB
Lundstrom EE-612 F08 7 small signal model (ii)
ro =∂I D ∂VDS gmb =∂I D ∂VBS VDS VDS C r gd g d g g υ + mb bs
Cgs υ g υ r − gs m gs o Cgb Cdb s + C υ sb − sb b b
Lundstrom EE-612 F08 8 outline
1) Introduction 2) Small signal model 3) Transconductance 4) Self-gain 5) Gain bandwidth product 6) Unity power gain 7) Noise, mismatch, linearity 8) Examples
Lundstrom EE-612 F08 9 transconductance
bipolar MOS (above VT , saturated)
gm =∂I D ∂VGS gm =∂IC ∂VBE VDS VCE
qVBE /kBT I D = WCoxυsat ()VGS − VT IC = IC 0e
gm = WCoxυsat gm = IC (kBT / q)
gm I D = 1 ()VGS − VT gm IC = 1 (kBT / q)
-1 -1 gm I D = 11.1()− 0.17 ≈ 1 V gm IC = 1( 0.026)≈ 40 V
(65 nm HP) Lundstrom EE-612 F08 10 MOSFET transconductance
g m 65 nm
90 nm
130 nm
gm = WCoxυsat
VGS
Tox scaling, high-k, mobility improvements (e.g. strain) increase gm. Lundstrom EE-612 F08 11 transconductance (subthreshold)
bipolar MOS (below VT , saturated)
g =∂I ∂V gm =∂I D ∂VGS m C BE V VDS CE
qVGS /mkBT qVBE /kBT I D = IOFF e IC = IC 0e
g = I k T / q gm = I D ()mkBT / q m C ( B )
g I = 1 k T / q gm I D = 1 ()mkBT / q m C ( B )
-1 -1 gm I D = 1 1.3() 0.026 ≈ 30 V gm IC = 1( 0.026)≈ 40 V
Lundstrom EE-612 F08 12 gm / ID figure of merit
g 1 40 m = I ()kBT / q BJT
gm g 1 I D m = I D ()mkBT / q
gm I D = 1 (VGS − VT ) MOSFET
VGS (VBE ) B. Murmann, P. Nikaeen, D.J. Connelly, and R. W. Dutton, “Impact of Scaling in Analog Performance and Associated Modeling Needs, IEEE Trans. Electron Dev., 2006. Lundstrom EE-612 F08 13 Outline
1) Introduction 2) Small signal model 3) Transconductance 4) Self-gain 5) Gain bandwidth product 6) Maximum power gain 7) Noise, mismatch, linearity 8) Examples
Lundstrom EE-612 F08 14 small signal gain
VDD − id = gmυin RD υout =−gmυin RD +
υout
υin υout = Aυ =−gm RD υin
Lundstrom EE-612 F08 15 effect of output resistance
I D ro =∂I D ∂VDS VDS id g d
υ C gs gs gmυgs ro
s
Aυ = −gm RD || ro VDS
Lundstrom EE-612 F08 16 self-gain
VDD high impedance current source
υout Aυ (max)= −gmro
υin ro
Lundstrom EE-612 F08 17 self-gain for 65 nm digital CMOS
0.2 mA/μm g ≈ = 1mS/μm m 0.2 V 1.2 V r ≈ ≈ 7 Kž -μm o 0.18 mA/μm
Aυ (max) = gmro ≈ 7
C.-H. Jan. et al., 2005 IEDM Lundstrom EE-612 F08 18 self-gain vs. scaling
50
40 Analog designers are frequently forced to use non-minimum length 30 (NML) devices.
Self-gain 20
10
180 130 90 65 45 Technology node (nm)
Lundstrom EE-612 F08 19 outline
1) Introduction 2) Small signal model 3) Transconductance 4) Self-gain 5) Gain bandwidth product 6) Unity power gain 7) Noise, mismatch, linearity 8) Examples
Lundstrom EE-612 F08 20 short-current current gain
iin g Cgd d
rg gmυgs i ω r iout in () Cgs o
s s
i ≈ g υ out m gs g 1 i ≈ m i υ = i out in gs in jωCTOT jω ()Cgs + Cgd (should include Cgb too) Lundstrom EE-612 F08 21 gain-bandwidth product
gm gm iout ≈ iin βω()T = 1 = jωCTOT ωT CTOT g βω ≈ m () gm ωCTOT fT = 2πCTOT 20log βω( ) = C − 20log ω β (dB) 10 10 gain falls at 20 dB per decade
0 log10 ω ωT
‘extrapolated ωT’
Lundstrom EE-612 F08 22 gain-bandwidth product (ii)
gm ωT = CTOT
g ≈ WC υ m ox SAT ωT (fT) is independent of W and increases as channel CTOT ≈ WLCox length, L, decreases
υSAT 1 ωT ≈ = L tt
Lundstrom EE-612 F08 23 fT vs. scaling
gm 1 fT = ~ 300 2π CTOT 2π tt 250
200 (GHz) T f 150
100
180 130 90 65 45 Technology node (nm)
Lundstrom EE-612 F08 24 gm / ID x fT
gm good for low power good for high freq fT I D “sweet spot” V − V ≈ 100 mV 30 ( GS T )
()gm I D × fT
VT VGS (VBE ) B. Murmann, P. Nikaeen, D.J. Connelly, and R. W. Dutton, “Impact of Scaling in Analog Performance and Associated Modeling Needs, IEEE Trans. Electron Dev., 2006. Lundstrom EE-612 F08 25 outline
1) Introduction 2) Small signal model 3) Transconductance 4) Self-gain 5) Gain bandwidth product 6) Unity power gain 7) Noise, mismatch, linearity 8) Examples
Lundstrom EE-612 F08 26 fmax
g ωT m f ≈ fT = MAX 2πC ⎛ 1 ⎞ TOT 4r + ω C g ⎝⎜ r T gd ⎠⎟ insensitive to rg and ro o independent of W sensitive to channel length scaling parasitics -r ~W increases fT g -ro ~ 1/W -Cgd ~W another figure of merit is f , MAX f ~ 1/W, need small W the maximum frequency of MAX oscillation or the unity power gain channel length scaling increases rg and lowers ro Lundstrom EE-612 F08 27 outline
1) Introduction 2) Small signal model 3) Transconductance 4) Self-gain 5) Gain bandwidth product 6) Unity power gain 7) Noise, mismatch, linearity… 8) Examples
Lundstrom EE-612 F08 28 noise
iD (t) i 2 2 VD n in
I D
2 in = Si (f )Δf
IG
VS t (ps)
Lundstrom EE-612 F08 29 thermal noise
thermal noise Johnson noise RD
− +
R 2 R Vn G 2 2 in = 4kBTγ gm Vn = S f ()f Δf = 4kBTRΔf
“white noise”
RS
Lundstrom EE-612 F08 30 1/f “flicker” noise
polysilicon 1 f
S f (f )
SiO2 thermal
dangling bonds fC f silicon “traps” corner frequency
fC ≈ 100 kHz Lundstrom EE-612 F08 31 mismatch differential pair analog circuits make use of matched transistors
sources of mismatch:
-variations in geometry M1 M 2 -ΔVT, ΔTox , … -thermal effects, etc. K ΔA = WL
dealing with mismatch: -circuit design -careful layout
Lundstrom EE-612 F08 32 linearity
VDD Δυ D = out max υ out max υout
RD υ out max
υout Δυ out max υin
jωt e υ υ in max in
(below threshold)
Lundstrom EE-612 F08 33 harmonic distortion
VDD
R D jωt j 2ωt j 3ωt A1e + A2e + A3e + ...
υout ∂I 1 ∂2 I 1 ∂3I i = D υ + D υ 2 + D υ 3 + ... υin d gs 2 gs 3 gs ∂Vgs 2! ∂Vgs 3! ∂Vgs i = g υ + g υ 2 + g υ 3 + ... e jωt d m1 gs m2 gs m2 gs
VIP2 VIP3 extrapolated gate voltage amplitude at which the amplitude of the harmonic = amplitude of fundamental Lundstrom EE-612 F08 34 distortion and the devices
VDD jωt j 2ωt j 3ωt A1e + A2e + A3e + ...
2 3 ∂I D 1 ∂ I D 2 1 ∂ I D 3 RD id = υgs + 2 υgs + 3 υgs + ... ∂Vgs 2! ∂Vgs 3! ∂Vgs
υout
υ in α I D ~ (VGS − VT ) (above threshold) jωt e DIBL
qVGS /kBT I D ~ e (below threshold)
Lundstrom EE-612 F08 35 outline
1) Introduction 2) Small signal model 3) Transconductance 4) Self-gain 5) Gain bandwidth product 6) Unity power gain 7) Noise, mismatch, linearity… 8) Recent examples
Lundstrom EE-612 F08 36 IEDM 2007
“Record RF Performance of 45-nm SOI CMOS Technology,” by Sungjae Lee, et al., IBM.
45 nm SOI technology 1.16 nm gate oxide strained Si technology
Lundstrom EE-612 F08 37 Sungjae Lee, et al. IEDM 2007
1 fT ≈ 2π tt
t < 0.33 ps 6 tN υ N > 8.8 × 10 cm/s
ttP < 0.46 ps υ P > 6.7 cm/s
Lundstrom EE-612 F08 38 Sungjae Lee, et al. IEDM 2007
1 fT = 2π tt
L t = t υ
L = 10 nm, υ = 107 cm/s
→ tt = 0.1 ps, fT = 1.6THz
gm fT = 2π CTOT
Lundstrom EE-612 F08 39 Sungjae Lee, et al. IEDM 2007
gm fT = 2π CTOT
Lundstrom EE-612 F08 40 Sungjae Lee, et al. IEDM 2007
AV = gmro
Lundstrom EE-612 F08 41 IEDM 2007
“A 32nm CMOS Low Power SoC Platform Technology for Foundry Applications with Functional High Density SRAM,” by Shien-Yang Wu, et al., Taiwan Semiconductor Manufacturing Company.
“A suitable SoC process technology needs to support both digital and analog functions with high density embedded memories.”
Lundstrom EE-612 F08 42 Shien-Yang Wu, et al, IEDM 2007
“Potential 1/f noise degradation induced by gate oxide nitridation and local strain process has been one of the critical concerns in analog applications [8]. Gate oxide with different nitrogen profiles and strain process with different film stacks are studied.”
Lundstrom EE-612 F08 43 outline
1) Introduction 2) Small signal model 3) Transconductance 4) Self-gain 5) Gain bandwidth product 6) Unity power gain 7) Noise, mismatch, linearity… 8) Recent examples
Lundstrom EE-612 F08 44 references
1) Paul R. Gray and Robert G. Meyer, Analysis and Design of Integrated Circuits,” 3rd Ed., Wiley, 1993
2) Behzad Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001.
Lundstrom EE-612 F08 45