Ne5517, Ne5517a, Au5517

NE5517, NE5517A, AU5517

Dual Operational Transconductance Amplifier

The AU5517 and NE5517 contain two current-controlled transconductance amplifiers, each with a differential input and push-pull output. The AU5517/NE5517 offers significant design and performance advantages over similar devices for all types of http://onsemi.com programmable gain applications. Circuit performance is enhanced through the use of linearizing diodes at the inputs which enable a MARKING 10 dB signal-to-noise improvement referenced to 0.5% THD. The DIAGRAMS AU5517/NE5517 is suited for a wide variety of industrial and consumer applications. Constant impedance of the buffers on the chip allow general use of SOIC−16 the AU5517/NE5517. These buffers are made of Darlington xx5517DG 1 D SUFFIX AWLYWW transistors and a biasing network that virtually eliminate the change of CASE 751B 1 offset voltage due to a burst in the bias current IABC, hence eliminating the audible noise that could otherwise be heard in high quality audio applications.

Features • Constant Impedance Buffers • D 1 PDIP−16 VBE of Buffer is Constant with Amplifier IBIAS Change NE5517yy N SUFFIX • AWLYYWWG Excellent Matching Between Amplifiers CASE 648 • Linearizing Diodes 1 • High Output Signal-to-Noise Ratio • Pb−Free Packages are Available* xx = AU or NE yy = AN or N Applications A = Assembly Location • WL = Wafer Lot Multiplexers YY, Y = Year • Timers WW = Work Week • Electronic Music Synthesizers G = Pb−Free Package • Dolby® HX Systems • Current-Controlled Amplifiers, Filters PIN CONNECTIONS • Current-Controlled Oscillators, Impedances N, D Packages

IABCa 1 16 IABCb Da 2 15 Db

+INa 3 14 +INb −INa 4 13 −INb VOa 5 12 VOb V− 6 11 V+

INBUFFERa 7 10 INBUFFERb VOBUFFERa 8 9 VOBUFFERb

(Top View)

ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

PIN DESCRIPTION Pin No. Symbol Description

1 IABCa Amplifier Bias Input A

2 Da Diode Bias A

3 +INa Non-inverted Input A

4 −INa Inverted Input A

5 VOa Output A 6 V− Negative Supply

7 INBUFFERa Buffer Input A

8 VOBUFFERa Buffer Output A

9 VOBUFFERb Buffer Output B

10 INBUFFERb Buffer Input B 11 V+ Positive Supply

12 VOb Output B

13 −INb Inverted Input B

14 +INb Non-inverted Input B

15 Db Diode Bias B

16 IABCb Amplifier Bias Input B

V+ 11

D4 D6 Q14 Q12 Q13 Q6 Q10 7,10

8,9

Q7 Q11

2,15

D2 D3 VOUTPUT

−INPUT Q4 Q5 +INPUT 5,12 4,13 3,14

Q15 Q16 1,16 Q3 AMP BIAS Q2 INPUT D7 Q9 R1 Q1 Q8 D8

D1 D5 V− 6 Figure 1. Circuit Schematic

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B AMP B B B B B BIAS DIODE INPUT INPUT B BUFFER BUFFER INPUT BIAS (+) (−) OUTPUT V+ (1) INPUT OUTPUT 16 15 14 13 12 11 10 9

−

123 45 6 7 8

AMP DIODE INPUT INPUT OUTPUT V− BUFFER BUFFER BIAS BIAS (+) (−) A INPUT OUTPUT INPUT AA A A A A NOTE: V+ of output buffers and amplifiers are internally connected.

Figure 2. Connection Diagram

MAXIMUM RATINGS Rating Symbol Value Unit ± Supply Voltage (Note 1) VS 44 VDC or 22 V ° Power Dissipation, Tamb = 25 C (Still Air) (Note 2) PD mW NE5517N, NE5517AN 1500 NE5517D, AU5517D 1125 ° Thermal Resistance, Junction−to−Ambient RqJA C/W D Package 140 N Package 94 ± Differential Input Voltage VIN 5.0 V

Diode Bias Current ID 2.0 mA

Amplifier Bias Current IABC 2.0 mA

Output Short-Circuit Duration ISC Indefinite

Buffer Output Current (Note 3) IOUT 20 mA ° Operating Temperature Range Tamb C NE5517N, NE5517AN 0 °C to +70 °C AU5517T −40 °C to +125 °C ° Operating Junction Temperature TJ 150 C

DC Input Voltage VDC +VS to −VS ° ° ° Storage Temperature Range Tstg −65 C to +150 C C ° Lead Soldering Temperature (10 sec max) Tsld 230 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. For selections to a supply voltage above ±22 V, contact factory. 2. The following derating factors should be applied above 25 °C N package at 10.6 mW/°C D package at 7.1 mW/°C. 3. Buffer output current should be limited so as to not exceed package dissipation.

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ELECTRICAL CHARACTERISTICS (Note 4) AU5517/NE5517 NE5517A

Characteristic Test Conditions Symbol Min Typ Max Min Typ Max Unit

Input Offset Voltage VOS 0.4 5.0 0.4 2.0 mV Overtemperature Range 5.0 m IABC 5.0 A 0.3 5.0 0.3 2.0 D D m ° VOS/ T Avg. TC of Input Offset Voltage 7.0 7.0 V/ C

VOS Including Diodes Diode Bias Current 0.5 5 0.5 2.0 mV m (ID) = 500 A m ≤ ≤ m Input Offset Change 5.0 A IABC 500 A VOS 0.1 0.1 3.0 mV

Input Offset Current IOS 0.1 0.6 0.1 0.6 mA D D m ° IOS/ T Avg. TC of Input Offset Current 0.001 0.001 A/ C

Input Bias Current IBIAS 0.4 5.0 0.4 5.0 mA Overtemperature Range 1.0 8.0 1.0 7.0 D D m ° IB/ T Avg. TC of Input Current 0.01 0.01 A/ C

Forward Transconductance gM 6700 9600 13000 7700 9600 12000 mmho Overtemperature Range 5400 4000

gM Tracking 0.3 0.3 dB m m Peak Output Current RL = 0, IABC = 5.0 A IOUT 5.0 3.0 5.0 7.0 A m RL = 0, IABC = 500 A 350 500 650 350 650 RL = 0, Overtemperature 300 300 500 Range

Peak Output Voltage VOUT V ∞ m ≤ ≤ m Positive RL = , 5.0 A IABC 500 A +12 +14.2 +12 +14.2 ∞ m ≤ ≤ m Negative RL = , 5.0 A IABC 500 A −12 −14.4 −12 −14.4 m Supply Current IABC = 500 A, both channels ICC 2.6 4.0 2.6 4.0 mA

VOS Sensitivity mV/V D D Positive VOS/ V+ 20 150 20 150 D D Negative VOS/ V− 20 150 20 150 Common-mode Rejection CMRR 80 110 80 110 dB Ration

Common-mode Range ±12 ±13.5 ±12 ±13.5 V Crosstalk Referred to Input (Note 5) 100 100 dB 20 Hz < f < 20 kHz ± Differential Input Current IABC = 0, Input = 4.0 V IIN 0.02 100 0.02 10 nA

Leakage Current IABC = 0 (Refer to Test Circuit) 0.2 100 0.2 5.0 nA

Input Resistance RIN 10 26 10 26 kW

Open-loop Bandwidth BW 2.0 2.0 MHz Slew Rate Unity Gain Compensated SR 50 50 V/ms

Buffer Input Current 5 INBUFFER 0.4 5.0 0.4 5.0 mA

Peak Buffer Output Voltage 5 VOBUFFER 10 10 V D VBE of Buffer Refer to Buffer VBE Test 0.5 5.0 0.5 5.0 mV Circuit (Note 6) ± ° m 4. These specifications apply for VS = 15 V, Tamb = 25 C, amplifier bias current (IABC) = 500 A, Pins 2 and 15 open unless otherwise specified. The inputs to the buffers are grounded and outputs are open. ± m W 5. These specifications apply for VS = 15 V, IABC = 500 A, ROUT = 5.0 k connected from the buffer output to −VS and the input of the buffer is connected to the transconductance amplifier output. ± W m ≤ ≤ m 6. VS = 15, ROUT = 5.0 k connected from Buffer output to −VS and 5.0 A IABC 500 A.

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TYPICAL PERFORMANCE CHARACTERISTICS

3 4 5 10 10 4 ± V = ±15V V = ±15V VS = 15V S S 3 2 3 2 +125°C 10 10 ° 1 -55°C -55 C 0 -1 ° 2 +25 C 10 10 -2 +125°C +25°C

-3 ° +125°C -55 C -4 -5 1 10 INPUT BIAS CURRENT (nA) INPUT OFFSET CURRENT (nA)

INPUT OFFSET VOLTAGE (mV) INPUT OFFSET VOLTAGE -6 +125°C -7 +25°C -8 0.1 1 m m m m m m m m m m 0.1mA1mA10mA 100mA 1000mA 0.1 A1A10A 100 A 1000 A 0.1 A1A10A 100 A 1000 A AMPLIFIER BIAS CURRENT (I ) AMPLIFIER BIAS CURRENT (I ) AMPLIFIER BIAS CURRENT (IABC) ABC ABC Figure 3. Input Offset Voltage Figure 4. Input Bias Current Figure 5. Input Bias Current

5 10 4 5 10 ± V VS = 15V 4 OUT (+)VIN = (−)VIN = VOUT = 36V ° 3 VCMR μ +125 C 10 3 2 10 4 ± 1 VS = 15V ∞ +25°C 0 RLOAD = -55°C -1 Tamb = 25°C 10 2 10 3 -2 -3 VCMR 0V -4 10 10 2 -5 LEAKAGE CURRENT (pA) COMMON-MODE RANGE (V) PEAK OUTPUT VOLTAGE AND PEAK OUTPUT VOLTAGE PEAK OUTPUT CURRENT ( A) PEAK OUTPUT CURRENT ( -6 VOUT -7 1 -8 10 m m m m m ° ° ° ° ° ° ° ° 0.1 A1A10A 100 A 1000 A 0.1mA1mA10mA 100mA 1000mA -50 C -25 C0C25C50C75C100 C125 C AMPLIFIER BIAS CURRENT (I ) AMBIENT TEMPERATURE (TA) ABC AMPLIFIER BIAS CURRENT (IABC) Figure 6. Peak Output Current Figure 7. Peak Output Voltage and Figure 8. Leakage Current Common-Mode Range

2 10 4 10 5 10 PINS 2, 15 +125°C gM PINS 2, 15 OPEN mq OPEN μ m ± V = 15V Ω M S 1 10 3 10 4 10

10 2 10 3 1

+25°C -55°C +125°C 10 10 2 0.1

+25°C (MEG ) INPUT RESISTANCE INPUT LEAKAGE CURRENT (pA) TRANSCONDUCTANCE (gM) — ( ohm) TRANSCONDUCTANCE 1 10 0.01 m m m m m m m m m m 01234567 0.1 A1A10A 100 A 1000 A 0.1 A1A10A 100 A 1000 A INPUT DIFFERENTIAL VOLTAGE AMPLIFIER BIAS CURRENT (IABC) AMPLIFIER BIAS CURRENT (IABC) Figure 9. Input Leakage Figure 10. Transconductance Figure 11. Input Resistance

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)

2000 7 100 V = ±15V T = +25°C R = 10kW 1800 S amb L ° 6 -55 C IABC = 1mA 1600 10 1400 5 CIN +25°C 1200 4 C 1000 OUT 1 +125°C 3 800

600 (pF) CAPACITANCE 2 0.1 OUTPUT DISTORTION (%) OUTPUT DISTORTION 400

AMPLIFIER BIAS VOLTAGE (mV) AMPLIFIER BIAS VOLTAGE 1 200 0.01 0 0 0.1mA1mA10mA 100mA 1000mA 0.1mA1mA10mA 100mA 1000mA 1 10 100 1000 DIFFERENTIAL INPUT VOLTAGE (mVP-P) AMPLIFIER BIAS CURRENT (IABC) AMPLIFIER BIAS CURRENT (IABC) Figure 12. Amplifier Bias Voltage vs. Figure 13. Input and Output Figure 14. Distortion vs. Differential Amplifier Bias Current Capacitance Input Voltage

20 VS = ±15V 600 RL = 10kW 0 500 VIN = 80mVP-P -20 400 VIN = 40mVP-P

-40 300

I = 1mA -60 ABC

1 VOLT RMS (dB) 1 VOLT 200

OUTPUT NOISE -80 20kHz BW 100 OUTPUT VOLTAGE RELATIVE TO RELATIVE OUTPUT VOLTAGE IABC = 100mA OUTPUT NOISE CURRENT (pA/Hz)

-100 0 m m m m m 0.1 A1A10A 100 A 1000 A 10 100 1k 10k 100k IABC AMPLIFIER BIAS CURRENT (mA) FREQUENCY (Hz) Figure 15. Voltage vs. Amplifier Bias Current Figure 16. Noise vs. Frequency

+36V +15V

4, 13 4V 4, 13 A − 11 A − 11

5, 12 7, 10 2, 15 2, 15 5, 12 NE5517 NE5517 8, 9 1, 15 1, 10 3, 14 3, 14 + 6 + 6

−15V

Figure 17. Leakage Current Test Circuit Figure 18. Differential Input Current Test Circuit

V+

V 50kW

V−

Figure 19. Buffer VBE Test Circuit

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APPLICATIONS

+15V 0.01mF

W 3, 14 10k 62kW INPUT − 11

390pF 1, 16 2, 15 7, 10 W 51 NE5517 8, 9 5, 12 4, 13 OUTPUT 1.3kW m + 6 0.01 F 5kW

−15V 10kW −15V 0.001mF

Figure 20. Unity Gain Follower

CIRCUIT DESCRIPTION If VIN is small, the ratio of I5 and I4 will approach unity and The circuit schematic diagram of one-half of the the Taylor series of In function can be approximated as AU5517/NE5517, a dual operational transconductance I I * I KT 5 [ KT 5 4 (eq. 3) amplifier with linearizing diodes and impedance buffers, is q In q I4 I4 shown in Figure 21. ^ ^ and I4 I5 IB Transconductance Amplifier I I * I I * I KT 5 [ KT 5 4 + 2KT 5 4 + (eq. 4) The transistor pair, Q4 and Q5, forms a transconductance q In q ń q VIN I4 1 2IB IB stage. The ratio of their collector currents (I4 and I5, ǒ qǓ respectively) is defined by the differential input voltage, VIN, IB I * I + V which is shown in Equation 1. 5 4 IN 2KT I + KT 5 (eq. 1) The remaining transistors (Q to Q ) and diodes (D to D ) VIN q In 6 11 4 6 I4 form three current mirrors that produce an output current equal Where VIN is the difference of the two input voltages to I5 minus I4. Thus: KT ≅ 26 mV at room temperature (300°k). q V ǒI Ǔ + I (eq. 5) Transistors Q1, Q2 and diode D1 form a current mirror which IN B 2KT O focuses the sum of current I4 and I5 to be equal to amplifier bias ǒ qǓ IB current IB: The term is then the transconductance of the amplifier ) + 2KT I4 I5 IB (eq. 2) and is proportional to IB.

V+ 11

D4 D6 Q14 Q12 Q13 Q6 Q10 7,10

8,9

Q7 Q11

2,15

D2 D3 VOUTPUT −INPUT Q4 Q5 +INPUT 5,12 4,13 3,14 Q15 Q16 1,16 Q3 AMP BIAS Q2 INPUT D7 Q9 R1 Q1 Q8 D8

D1 D5 V− 6 Figure 21. Circuit Diagram of NE5517

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Linearizing Diodes Impedance Buffer For VIN greater than a few millivolts, Equation 3 becomes The upper limit of transconductance is defined by the invalid and the transconductance increases non-linearly. maximum value of IB (2.0 mA). The lowest value of IB for Figure 22 shows how the internal diodes can linearize the which the amplifier will function therefore determines the transfer function of the operational amplifier. Assume D2 overall dynamic range. At low values of IB, a buffer with and D3 are biased with current sources and the input signal very low input bias current is desired. A Darlington current is IS. Since I4 + I5 = IB and I5 − I4 = I0, amplifier with constant-current source (Q14, Q15, Q16, D7, that is: I4 = (IB − I0), I5 = (IB + I0) D8, and R1) suits the need.

+VS APPLICATIONS

ID Voltage-Controlled Amplifier In Figure 23, the voltage divider R2, R3 divides the IB I + 2I ǒ Ǔ 0 S I input-voltage into small values (mV range) so the amplifier I D ID D * I ) I operates in a linear manner. 2 S 2 S + * I0 I5 I4 It is: I4 I5 +* @ R3 @ D3 D2 IOUT VIN ) gM; R2 R3 1/2ID Q I + @ 4 5 VOUT IOUT RL; I IS S 1/2I V R D A + OUT + 3 @ g @ R IB ) M L VIN R2 R3

−VS (3) gM = 19.2 IABC m (gM in mhos for IABC in mA) Figure 22. Linearizing Diode Since gM is directly proportional to IABC, the amplification is controlled by the voltage VC in a simple way. For the diodes and the input transistors that have identical When VC is taken relative to −VCC the following formula geometries and are subject to similar voltages and is valid: temperatures, the following equation is true: * (VC 1.2V) ID I + ) I 1ń2(I ) I ) (eq. 6) ABC R T In 2 S + KT In B O 1 q I q ń * D * 1 2(IB IO) The 1.2 V is the voltage across two base-emitter baths in 2 IS the current mirrors. This circuit is the base for many I I + 2 B t D applications of the AU5517/NE5517. IO IS for |IS| ID 2 The only limitation is that the signal current should not exceed ID.

INT VC +VCC

+VCC R1 IABC R4 = R2/ /R3 3 + 11 1 5 7 NE5517 R2 − 6 VIN 8 4 VOUT IOUT RL

R3 RS INT −VCC

TYPICAL VALUES: R1 = 47kW R2 = 10kW R3 = 200W R4 = 200W RL = 100kW RS = 47kW Figure 23.

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Stereo Amplifier With Gain Control Modulators Figure 24 shows a stereo amplifier with variable gain via Because the transconductance of an OTA (Operational a control input. Excellent tracking of typical 0.3 dB is easy Transconductance Amplifier) is directly proportional to IABC, to achieve. With the potentiometer, RP, the offset can be the amplification of a signal can be controlled easily. The adjusted. For AC-coupled amplifiers, the potentiometer output current is the product from transconductance×input may be replaced with two 510 W resistors. voltage. The circuit is effective up to approximately 200 kHz. Modulation of 99% is easy to achieve.

+VCC

W 10k 3 V + 11 IN1 INT RIN W 15k +VCC RP NE5517/A 1k RD +VCC − IABC 8 4 1 V RL OUT1 30kW 10kW VC 5.1kW RC W 10k 14 16 VIN2 + −V I CC RIN 15kW ABC 15 10 +VCC RP NE5517/A 1k R 12 +VCC D − 6 9 13 VOUT2 RL 10kW RS

−VCC INT

Figure 24. Gain-Controlled Stereo Amplifier

RC 30kW VIN2 1 SIGNAL I ABC +VCC

11 ID INT 3 +V + CC 15kW 2 5 7 NE5517/A 1kW VOS V − IN1 4 8 CARRIER W 10k RL VOUT 10kW 6 RS

−VCC −VCC INT Figure 25. Amplitude Modulator

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Voltage-Controlled Resistor (VCR) Voltage-Controlled Oscillators Because an OTA is capable of producing an output current Figure 32 shows a voltage-controlled triangle-square proportional to the input voltage, a voltage variable resistor wave generator. With the indicated values a range from can be made. Figure 26 shows how this is done. A voltage 2.0 Hz to 200 kHz is possible by varying IABC from 1.0 mA presented at the RX terminals forces a voltage at the input. to 10 mA. This voltage is multiplied by gM and thereby forces a current The output amplitude is determined by IOUT × ROUT. through the RX terminals: Please notice the differential input voltage is not allowed to be above 5.0 V. ) With a slight modification of this circuit you can get the + R RA Rx ) sawtooth pulse generator, as shown in Figure 33. gM RA where gM is approximately 19.21 mMHOs at room APPLICATION HINTS temperature. Figure 27 shows a Voltage Controlled Resistor To hold the transconductance gM within the linear range, using linearizing diodes. This improves the noise IABC should be chosen not greater than 1.0 mA. The current performance of the resistor. mirror ratio should be as accurate as possible over the entire current range. A current mirror with only two transistors is Voltage-Controlled Filters not recommended. A suitable current mirror can be built Figure 28 shows a Voltage Controlled Low-Pass Filter. with a PNP transistor array which causes excellent matching The circuit is a unity gain buffer until XC/gM is equal to and thermal coupling among the transistors. The output R/RA. Then, the frequency response rolls off at a 6dB per current range of the DAC normally reaches from 0 to octave with the −3 dB point being defined by the given −2.0 mA. In this application, however, the current range is equations. Operating in the same manner, a Voltage set through RREF (10 kW) to 0 to −1.0 mA. Controlled High-Pass Filter is shown in Figure 29. Higher order filters can be made using additional amplifiers as + @ VREF + @ 5V + IDACMAX 2 2 W 1mA shown in Figures 30 and 31. RREF 10k

) R RA R + X g @ R 30kW M A +VCC VC INT 3 +V + 11 CC IO 2 NE5517/A 5 7 − C 4 8 VOUT 200W 200W RX R −VCC 100kW 10kW

−VCC INT

Figure 26. VCR

+VCC 1 30kW VC +VCC ID INT 3 11 +VCC RP V 2 OS NE5517/A W 1k 5 7 6 C 4 8 RX R −VCC 100kW 10kW

−VCC INT Figure 27. VCR with Linearizing Diodes

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1 30kW VC +VCC I ABC INT 100kW 3 +V VIN + 11 CC 2 NE5517/A 5 7 − 6 C 4 150pF 8 VOUT W R 200 R 200W −V A CC 100kW 10kW

−VCC INT

NOTE: RA gM f + O g(R ) RA) 2pC Figure 28. Voltage-Controlled Low-Pass Filter

1 30kW VC +VCC +VCC I ABC INT 100kW V 3 +V OS + 11 CC NULL 2 NE5517/A 5 -VCC 7 − 6 C 4 0.005mF 8 VOUT R W A R 1k 1kW −VCC 100kW 10kW

−VCC INT

NOTE: RA gM f + O g(R ) RA) 2pC

Figure 29. Voltage-Controlled High-Pass Filter

15kW VC +VCC +VCC INT +VCC VIN + +

NE5517/A NE5517/A 100kW 200pF − C − C2 100pF R V 200W A OUT R 100 RA 200W −V W W RA CC 100kW 10kW kW 200 10k 200 −VCC -VCC INT

NOTE: RA gM f + O ) p (R RA)2 C Figure 30. Butterworth Filter − 2nd Order

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W 1 16 15k VC +VCC +VCC INT 10kW 3 14 +VCC + 11 + 2 5 7 12 10 NE5517/A 20kW 15 NE5517/A LOW PASS − 6 − 800pF VOUT 800pF 13 9 1kW 1kW −V 20kW 5.1kW CC 20kW 5.1kW

−VCC −VCC INT BANDPASS OUT

Figure 31. State Variable Filter

30kW +VCC VC

+VCC INT +VCC INT 47kW 4 13 +VCC − 11 − 1 5 7 12 10 NE5517/A NE5517/A 16 3 + 6 C + 0.1mF 8 14 9 VOUT2

−V 20kW CC 10kW

−VCC −VCC VOUT1 INT GAIN CONTROL

Figure 32. Triangle−Square Wave Generator (VCO)

I IC B W 470k 1 +VCC VC +V 16 CC INT +VCC INT +VCC W W 4 13 47k 30k + 11 − 5 7 12 10 2 NE5517/A NE5517/A

3 − 6 C + m 8 0.1 F 14

R R 1 −VCC 20kW 2 30kW 30kW −VCC

−VCC VOUT1 NOTE: VOUT2 (V * 0.8) R I INT C 1 2VPK xC 2VPKxC C V + T + T + f I ttI PK ) H I L I OSC C B R1 R2 B C 2VPKxC

Figure 33. Sawtooth Pulse VCO

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ORDERING INFORMATION Device Temperature Range Package Shipping† AU5517DR2 SOIC−16

AU5517DR2G −40 to +125 °C SOIC−16 2500 Tape & Reel (Pb−Free)

NE5517D SOIC−16

NE5517DG SOIC−16 48 Units/Rail (Pb−Free)

NE5517DR2 SOIC−16

NE5517DR2G SOIC−16 2500 Tape & Reel (Pb−Free) 0 to +70 °C NE5517N PDIP−16

NE5517NG PDIP−16 (Pb−Free) 25 Units/Rail NE5517AN PDIP−16

NE5517ANG PDIP−16 (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.

Intel is a registered trademark of Intel Corporation in the U.S. and/or other countries.

http://onsemi.com 13 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS

PDIP−16 CASE 648−08 ISSUE V 16 DATE 22 APR 2015 1 SCALE 1:1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. D A 2. CONTROLLING DIMENSION: INCHES. 16 9 E 3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK- H AGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3. 4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE NOT TO EXCEED 0.10 INCH. E1 5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR TO DATUM C. 6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE 18 c LEADS UNCONSTRAINED. NOTE 8 b2 7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE B END VIEW LEADS, WHERE THE LEADS EXIT THE BODY. TOP VIEW WITH LEADS CONSTRAINED 8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE NOTE 5 CORNERS). A2 e/2 INCHES MILLIMETERS A DIM MIN MAX MIN MAX NOTE 3 A −−−− 0.210 −−− 5.33 L A1 0.015 −−−− 0.38 −−− A2 0.115 0.195 2.92 4.95 b 0.014 0.022 0.35 0.56 b2 0.060 TYP 1.52 TYP A1 SEATING C 0.008 0.014 0.20 0.36 C PLANE M D 0.735 0.775 18.67 19.69 D1 D1 0.005 −−−− 0.13 −−− e eB E 0.300 0.325 7.62 8.26 E1 0.240 0.280 6.10 7.11 16X END VIEW b e 0.100 BSC 2.54 BSC NOTE 6 0.010 M CAM B M eB −−−− 0.430 −−− 10.92 SIDE VIEW L 0.115 0.150 2.92 3.81 M −−−− 10 ° −−− 10 ° GENERIC MARKING DIAGRAM* 16 XXXXXXXXXXXX XXXXXXXXXXXX STYLE 1: STYLE 2: AWLYYWWG PIN 1. CATHODE PIN 1. COMMON DRAIN 1 2. CATHODE 2. COMMON DRAIN 3. CATHODE 3. COMMON DRAIN 4. CATHODE 4. COMMON DRAIN XXXXX = Specific Device Code 5. CATHODE 5. COMMON DRAIN A = Assembly Location 6. CATHODE 6. COMMON DRAIN WL = Wafer Lot 7. CATHODE 7. COMMON DRAIN 8. CATHODE 8. COMMON DRAIN YY = Year 9. ANODE 9. GATE WW = Work Week 10. ANODE 10. SOURCE 11. ANODE 11. GATE G = Pb−Free Package 12. ANODE 12. SOURCE 13. ANODE 13. GATE *This information is generic. Please refer to 14. ANODE 14. SOURCE device data sheet for actual part marking. 15. ANODE 15. GATE G 16. ANODE 16. SOURCE Pb−Free indicator, “G” or microdot “ ”, may or may not be present.

Electronic versions are uncontrolled except when accessed directly from the Document Repository. DOCUMENT NUMBER: 98ASB42431B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. DESCRIPTION: PDIP−16 PAGE 1 OF 1

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others.

SOIC−16 CASE 751B−05 ISSUE K SCALE 1:1 DATE 29 DEC 2006 −A− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 16 9 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. −B− P 8 PL 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION M S 180.25 (0.010) B SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

MILLIMETERS INCHES DIM MIN MAX MIN MAX G A 9.80 10.00 0.386 0.393 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F F 0.40 1.25 0.016 0.049 K R X 45_ G 1.27 BSC 0.050 BSC J 0.19 0.25 0.008 0.009 C K 0.10 0.25 0.004 0.009 M 0 ____ 7 0 7 −T− SEATING P 5.80 6.20 0.229 0.244 PLANE M J R 0.25 0.50 0.010 0.019 D 16 PL 0.25 (0.010)M T B S A S

STYLE 1: STYLE 2: STYLE 3: STYLE 4: PIN 1. COLLECTOR PIN 1. CATHODE PIN 1. COLLECTOR, DYE #1 PIN 1. COLLECTOR, DYE #1 2. BASE 2. ANODE 2. BASE, #1 2. COLLECTOR, #1 3. EMITTER 3. NO CONNECTION 3. EMITTER, #1 3. COLLECTOR, #2 4. NO CONNECTION 4. CATHODE 4. COLLECTOR, #1 4. COLLECTOR, #2 5. EMITTER 5. CATHODE 5. COLLECTOR, #2 5. COLLECTOR, #3 6. BASE 6. NO CONNECTION 6. BASE, #2 6. COLLECTOR, #3 7. COLLECTOR 7. ANODE 7. EMITTER, #2 7. COLLECTOR, #4 8. COLLECTOR 8. CATHODE 8. COLLECTOR, #2 8. COLLECTOR, #4 9. BASE 9. CATHODE 9. COLLECTOR, #3 9. BASE, #4 10. EMITTER 10. ANODE 10. BASE, #3 10. EMITTER, #4 11. NO CONNECTION 11. NO CONNECTION 11. EMITTER, #3 11. BASE, #3 12. EMITTER 12. CATHODE 12. COLLECTOR, #3 12. EMITTER, #3 13. BASE 13. CATHODE 13. COLLECTOR, #4 13. BASE, #2 14. COLLECTOR 14. NO CONNECTION 14. BASE, #4 14. EMITTER, #2 SOLDERING FOOTPRINT 15. EMITTER 15. ANODE 15. EMITTER, #4 15. BASE, #1 8X 16. COLLECTOR 16. CATHODE 16. COLLECTOR, #4 16. EMITTER, #1 6.40

STYLE 5: STYLE 6: STYLE 7: 16X 1.12 PIN 1. DRAIN, DYE #1 PIN 1. CATHODE PIN 1. SOURCE N‐CH 2. DRAIN, #1 2. CATHODE 2. COMMON DRAIN (OUTPUT) 1 16 3. DRAIN, #2 3. CATHODE 3. COMMON DRAIN (OUTPUT) 4. DRAIN, #2 4. CATHODE 4. GATE P‐CH 5. DRAIN, #3 5. CATHODE 5. COMMON DRAIN (OUTPUT) 16X 6. DRAIN, #3 6. CATHODE 6. COMMON DRAIN (OUTPUT) 0.58 7. DRAIN, #4 7. CATHODE 7. COMMON DRAIN (OUTPUT) 8. DRAIN, #4 8. CATHODE 8. SOURCE P‐CH 9. GATE, #4 9. ANODE 9. SOURCE P‐CH 10. SOURCE, #4 10. ANODE 10. COMMON DRAIN (OUTPUT) 11. GATE, #3 11. ANODE 11. COMMON DRAIN (OUTPUT) 12. SOURCE, #3 12. ANODE 12. COMMON DRAIN (OUTPUT) 13. GATE, #2 13. ANODE 13. GATE N‐CH 1.27 14. SOURCE, #2 14. ANODE 14. COMMON DRAIN (OUTPUT) PITCH 15. GATE, #1 15. ANODE 15. COMMON DRAIN (OUTPUT) 16. SOURCE, #1 16. ANODE 16. SOURCE N‐CH 89

DIMENSIONS: MILLIMETERS

Electronic versions are uncontrolled except when accessed directly from the Document Repository. DOCUMENT NUMBER: 98ASB42566B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. DESCRIPTION: SOIC−16 PAGE 1 OF 1

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