Research Article Differential Difference Current Conveyor Transconductance Ampliﬁer: a New Analog Building Block for Signal Processing

Hindawi Publishing Corporation Journal of Electrical and Computer Engineering Volume 2011, Article ID 361384, 10 pages doi:10.1155/2011/361384

Research Article Differential Difference Current Conveyor Transconductance Ampliﬁer: A New Analog Building Block for Signal Processing

Neeta Pandey1 and Sajal K. Paul2

1 Department of Electronics and Communication Engineering, Delhi Technological University, Delhi 110042, India 2 Department of Electronics Engineering, Indian School of Mines, Jharkhand 826004, India

Correspondence should be addressed to Neeta Pandey, n66pandey@rediﬀmail.com

Received 30 March 2011; Revised 28 August 2011; Accepted 31 August 2011

Academic Editor: Raj Senani

Copyright © 2011 N. Pandey and S. K. Paul. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

A new active building block for analog signal processing, namely, differential difference current conveyor transconductance amplifier (DDCCTA), is presented, and performance is checked through PSPICE simulations which show the usability of the proposed element is up to 201 MHz. The proposed block is implemented using 0.25 μm TSMC CMOS technology. Some of the applications are presented using the proposed DDCCTA, namely, a voltage mode multifunction filter, a current mode universal filter, an oscillator, current and voltage amplifiers, and grounded inductor simulator. The feasibility of DDCCTA and its applications is confirmed via PSPICE simulations.

1. Introduction difference transconductance amplifier (CCCDTA) [13], dif- feren tial voltage current conveyor transconductance ampli- The analog integrated circuit design in current mode is fier (DVCCTA) [14], and differential voltage current con- receiving increased attention due to some potential per- trolled conveyor transconductance amplifier (DVCCCTA) formance features like wide bandwidth, less circuit com- [15], are reported in the literature. These may be constructed plexity, wide dynamic range, low power consumption, and by cascading of current mode building blocks with transcon- high operating speed [1]. The current mode approach has ductance amplifier (TA) analog building blocks in mono- emerged as an alternate method besides the traditional lithic chip for compact implementation of signal processing voltage mode circuits. The current mode active elements circuits and systems. It is well known that DDCC has some are appropriate to operate with signals in current or voltage advantages [7, 16, 17] specially for applications demanding or mixed mode and are gaining acceptance as building differential and floating inputs, over CCII or CCCII owing to blocks in high-performance circuit designs. A number of three high input impedance terminals for DDCC compared current mode active elements such as operational transcon- to one high input impedance terminal for CCII or CCCII. ductance amplifier (OTA) [2], current conveyors (CCs) However, DDCC does not have a powerful inbuilt tuning [3–5], differential voltage current conveyor (DVCC) [6], property in contrast to CCCII. The DDCC is more versatile differential difference current conveyor (DDCC) [7], current than DVCC as it has an extra high input impedance feedback operational amplifier (CFOA) [8] are available in terminal. the literature. The main intention of this paper is to propose a new Recently some new analog building blocks, such as active building block, namely, differential difference current current conveyor transconductance amplifier (CCTA) [9, conveyor transconductance amplifier (DDCCTA), which has 10], current controlled current conveyor transconductance DDCC [7] as input block and is followed by a TA. The amplifier (CCCCTA) [11], current difference transconduc- DDCCTA has all the good properties of CCTA, CCCCTA, tance amplifier (CDTA) [12], current controlled current and DVCCTA including the possibility of inbuilt tuning 2 Journal of Electrical and Computer Engineering

Ibias 2.1. Relationship between Voltages of X Port and Y1, Y2, and IY1 Y3 Ports. The voltage at X port may be found by analyzing VY1 I Y1 Z1+ Z1+ the differential difference part (comprising of transistors M1 DDCCTA I V Z2+ Z2+ to M10) of the circuit of Figure 2 as follows: Y2 Y2 I − = − Y2 O1 IO1− VX β1VY1 β2VY2 + βVY3 + εV ,(2) V Y3 Y3 X − O2 IO2− IY3 where IX 1 gm3 gm4gm5 − gm3gm6 β1 = gm3gm6 + , P1 gm3 + gm4 VX 1 gm1 gm1gm5 − gm2gm6 Figure 1: Circuit symbol of the proposed DDCCTA. β2 = gm1gm5 + , P1 gm1 + gm2 1 gm2 gm1gm5 − gm2gm6 β3 = gm2gm6 + , (3) of the parameters of the signal processing circuits to be P1 gm1 + gm2 implemented and also all the versatile and special properties of DDCC such as easy implementation of differential and − − = − IB gm1gm5 gm2gm6 gm4gm5 gm3gm6 floating input circuits. However, the same may be imple- εV + , P1 gm1 + gm2 gm3 + gm4 mented using separate DDCC and OTA analog building blocks, but it will be more convenient and useful if DDCCTA gm4 gm4gm5 − gm3gm6 is implemented in monolithic chip which will result in P1 = gm4gm5 − , compact implementation of signal processing circuits and gm3 + gm4 systems. Section 2 deals with the proposed DDCCTA circuit and IB represents current through transistor Mi (i = and some of its properties. Section 3 is devoted for some 7, 8, 10, 12, 14). With matched transconductances gm1 = of its applications in developing signal processing circuits gm2 = gm3 = gm4 and gm5 = gm6, VX is obtained as such as voltage mode (VM) filter, current mode (CM)

filter, oscillator, current and voltage amplifier, and grounded VX = VY1 − VY2 + VY3. (4) inductor simulator. The functionality of all the proposed circuits has been verified using SPICE simulations. The 2.2. Relationship between Currents at Z1+, Z2+, and X Ports. conclusion is given in Section 4. The analysis of the portion of the circuit comprising of transistors M9 to M14 of the circuit of Figure 2 gives 2. Proposed DDCCTA IZ1+ = α1IX + εI1, The DDCCTA is based on DDCC [7] and consists of (5) = differential amplifier, current mirrors, and TA. The port IZ2+ α2IX + εI2, relationships of the DDCCTA as shown in Figure 1 can be where characterized by the following matrix: gm11 gm11 ⎡ ⎤ ⎡ ⎤ ⎡ ⎤ α1 = , εI1 = 1 − IB, IY1 0 0 00 0 000 VY1 g 9 g 9 ⎢ ⎥ ⎢ ⎥ ⎢ ⎥ m m ⎢ ⎥ ⎢ ⎥ ⎢ ⎥ (6) ⎢ IY2 ⎥ ⎢0 0 00 0 000⎥ ⎢ VY2 ⎥ ⎢ ⎥ ⎢ ⎥ ⎢ ⎥ gm13 gm13 ⎢ ⎥ ⎢ ⎥ ⎢ ⎥ α = , ε = 1 − I . ⎢ ⎥ ⎢0 0 00 0 000⎥ ⎢ ⎥ 2 I2 B ⎢ IY3 ⎥ ⎢ ⎥ ⎢ VY3 ⎥ gm9 gm9 ⎢ ⎥ ⎢ ⎥ ⎢ ⎥ ⎢ ⎥ ⎢ − ⎥ ⎢ ⎥ ⎢ VX ⎥ ⎢1 110 0 000⎥ ⎢ IX ⎥ = = ⎢ ⎥ = ⎢ ⎥ × ⎢ ⎥,(1)For matched transconductances gm9 gm11 gm13, the port ⎢ ⎥ ⎢ ⎥ ⎢ ⎥ ⎢IZ1+ ⎥ ⎢0 0 01 0 000⎥ ⎢VZ1+ ⎥ currents are simplified to ⎢ ⎥ ⎢ ⎥ ⎢ ⎥ ⎢ ⎥ ⎢ ⎥ ⎢ ⎥ ⎢IZ2+ ⎥ ⎢0 0 01 0 000⎥ ⎢VZ2+ ⎥ ⎢ ⎥ ⎢ ⎥ ⎢ ⎥ IZ1+ = IZ2+ = IX . (7) ⎢ ⎥ ⎢ − ⎥ ⎢ ⎥ ⎣I01 ⎦ ⎣0000 gm 000⎦ ⎣VO1−⎦ − 2.3. Relation for Currents at O1− and O2− Ports. The IO2− 0000 gm 000 VO2− proposed DDCCTA contains a transconductor cell compris- where g is transcon/ductance of the DDCCTA. ing of transistors M15 to M24. Assuming gate voltages of m transistors M17 and M18 as V and V , the output currents The CMOS-based internal circuit of DDCCTA in CMOS T1 T2 I − and I − may be found, respectively, as is depicted in Figure 2. It consists of the circuit of DDCC O1 O2 [7] (transistors M1 to M14) followed by a transconductance IO1− = − γ1VT1 − γ2VT2 + εT1 , amplifier (transistors M15 to M24). The derivation of port (8) relationships is given in Sections 2.1 to 2.3 [13]. IO2− = − γ3VT1 − γ4 VT2 + εT2 , Journal of Electrical and Computer Engineering 3

VDD

M5 M6 M9 M11 M13 M15 M16 M19 M20 M23

X Z1+ Z2+ M4 M17 M18 O1− O2− M1 M2 M3 Y2 Y3 Y1

I VBB M14 bias M21 M24 M7 M8 M12 M22 M10

VSS

Figure 2: DDCCTA implementation.

where With gm17 = gm18, gm21 = gm22 = gm24, gm15 = gm16 = gm19 = gm20 = gm23, the output currents IO1− and IO2− reduce to gm16gm22 1 γ1 = gm17 − gm15gm21 gm15gm19gm21 IO1− = − gm17VT1 − gm18VT2 , (10) g g g g − g g g g = − − × m16 m17 m19 m22 m15 m18 m20 m21 , IO2− gm17VT1 gm18VT2 . (11) gm17 + gm18 In the circuit, VT1 = VZ1+ and VT2 = 0; hence the output gm20 1 γ2 = gm18 + currents are simpliﬁed to gm19 gm15gm19gm21 = − = − g g g g − g g g g IO1− gm17VZ1+, IO2− gm17VZ1+. (12) × m16 m17 m19 m22 m15 m18 m20 m21 , gm17 + gm18 gm16gm24 1 The value of gm17 is obtained as 2μCox(W/L)17IBias γ3 = gm17 − gm15gm21 gm15gm19gm21 if transistors are biased in strong inversion region and 2IBias/VT (VT = KT/q) if transistors are biased in subthresh- g g g g − g g g g old region which can be adjusted by bias current I . × m16 m17 m19 m24 m15 m18 m23 m21 , Bias gm17 + gm18 2.4. Simulation. To validate the behaviour of the proposed gm23 1 element, PSPICE simulations have been carried out using γ4 = gm18 + gm19 gm15gm19gm21 TSMC 0.25 μm CMOS process model parameters. The = − = = − supply voltages of VDD VSS 1.25 V and VBB 0.8V − are used. The aspect ratio of various transistors for DDCCTA × gm16gm17gm19gm24 gm15gm18gm23gm21 , is given in Table 1. The DC transfer characteristics of the gm17 + gm18 proposed DDCCTA from Y1, Y2, and Y3 terminals to X I terminal are shown in the Figure 3. It is clear that the voltage ε = − Bias T1 g g g at X terminal follows the Y terminal voltages in the range m15 m19 m21 of −200 mV to +200 mV. The variation of current at Z1+ and Z2+ terminals with X terminal current from −100 μA g g g g − g g g g × m16 m17 m19 m22 m15 m18 m20 m21 , to 100 μA is shown in Figure 4. It may be noted that there gm17 + gm18 is deviation for current below −80 μA. The variation of the transconductance value by changing IBias from 0 to 500 μAis IBias εT2 = − depicted in Figure 5. The decreases in transconductance for gm15gm19gm21 larger bias currents than 450 μA or so is due to transistors (M17,M18) entering in linear region of operation from − gm16gm17gm19gm24 gm15gm18gm23gm21 saturation region. The maximum transconductance is about × . gm17 + gm18 1.6 mS. The other circuit performance parameters of the (9) DDCCTA are summarised in Table 2. 4 Journal of Electrical and Computer Engineering

300 400

200 200

100 0 ) (mV) ) (mV) X X − V V 0 200

−100 −400 Voltage ( Voltage (

−200 −600

−300 −800 −300 −200 −100 0 100 200 300 −300−200 −100 0 100 200 300

Voltage (VY1) (mV) Voltage (VY2) (mV) (a) (b) 300

200

100 ) (mV) X

V 0

−100 Voltage (

−200

−300 −300−200 −100 0 100 200 300

Voltage (VY3)(mV)

Theoretical Simulated (c)

Figure 3: DC transfer characteristic for voltage transfer from (a) Y1porttoX port, (b) Y2porttoX port, and (c) Y3porttoX port.

100 Table 1: Aspect ratio of various transistors

Transistor Aspect ratio (W(μm)/L(μm)) 50 M1–M4 10/0.5 A) µ ( M5, M6 5/0.5 Z2+ I

, M7, M8 27.25/0.5 0 Z1+

I M9, M11, M13 8.5/0.5 M10, M12, M14 44/0.5 − Current 50 M15, M16, M19–M24 5/0.5 M17, M18 27/0.5

−100 −100 −50 0 50 100 Current IX (µA) 3. Applications Theoretical 3.1. Multifunction Voltage Mode Filter. In this section a Simulated multifunction voltage mode (VM) ﬁlter is proposed. It uses Figure 4: DC transfer characteristic for current transfer from X a single DDCCTA, two grounded capacitors, and a grounded port to Z1+ and Z2+ ports. resistor. The proposed multifunction VM ﬁlter is shown in Journal of Electrical and Computer Engineering 5

2 10

0 1.5

−10 1 − Gain (dB) 20

0.5 Transconductance (mS) −30

0 −40 0 100 200 300 400 500 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 100 MHz Bias current (µA) Frequency Figure 5: Variation of transconductance with bias current. Figure 7: Simulated responses of the proposed voltage mode ﬁlter.

Ibias

Ibias Y1 Z2+ Iout1

V DDCCTA Z1+ in I C Y1 Z2+ Y2 in4 1 − I Iin2 DDCCTA Z1+ Vout2 O1 out2 Y2 C Y3 X O2− C O1− 1 2 Iin1 X O2− Y3 Iin3 C2 R Vout1 R Vout3

Figure 8: Current mode universal ﬁlter. Figure 6: Proposed voltage mode ﬁlter. Figure 6. The analysis of circuit yields the output voltages at various nodes as V s2C C R out1 = 1 2 , Table 2: Circuit performance parameters of the DDCCTA. Vin D(s) V sC Power consumption 1.8 mW out2 = 2 , (13) Vin D(s) Input voltage linear range −200 mV to +200 mV (voltage inputs) V g out3 = − m , Input current linear range Vin D(s) −80 μA to 100 μA (current input) where

Parasitic at Y ports (RY , CY ) very high, 20 fF 2 D(s) = s C1C2R + sC2 + gm. (14) Parasitic at Z ports (RZ , CZ ) 218 kΩ,35fF It may be observed from (13) that high-pass, band-pass, Parasitic at O− ports 324 kΩ,20fF and low-pass responses are available simultaneously at Vout1, (RO−, CO−) Vout2,andVout3, respectively. Thus, the proposed structure

236 MHz for VX /VY is a single-input-and-three-output voltage mode ﬁlter. It −3 dB bandwidth may be noted that no component matching constraint is = (at IBias 100 μA) 223 MHz for IZ /Ix required. The responses are characterized by pole frequency ( ), bandwidth ( ), and quality factor ( )as 201 MHz for IO−/Vz ω0 ω0/Q0 Q0 Input bias range for 1/2 1/2 = gm ω0 = 1 = gmRC1 controlling transconductance 10 nA to 450 μA ω0 , , Q0 . RC1C2 Q0 RC1 C2 ampliﬁer (15) 6 Journal of Electrical and Computer Engineering

2 2

1.5 1.5

1 1 Gain Gain

0.5 0.5

0 0 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 100 MHz 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 100 MHz Frequency Frequency (a) (b) 2 2 180

1.5 1.5 100

1 1 0 Gain Gain Phase (deg)

0.5 0.5 −100

0 0 −180 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 100 MHz 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 100 MHz Frequency Frequency (c) (d)

Figure 9: Simulated responses of the proposed current mode universal ﬁlter: (a) low pass and band pass; (b) high pass and band pass; (c) notch; (d) all pass.

Table 3: Comparative study of the available similar type of single-active-element-based VM ﬁlters.

Active Number of No requirement element used Grounded Availability of LP, available No inversion No of gain of input Reference and number passive HP, BP, notch, and simultane- of input Tunability matching signal such as of passive components AP responses ous voltage condition 2V and 3V components responses in in [11] CCCCTA, 2 No All 1 No No Yes No [15] DVCCCTA, 2 Yes 2 2 Yes Yes Yes Yes [18] DBTA,5 No LP,HP,BP,Notch 1 Yes Yes Yes No [19] DBTA,4 No All 2 Yes Yes Yes No Proposed DDCCTA, 3 Yes LP, HP, BP 3 Yes Yes Yes Yes LP: low pass; HP: high pass; BP: band pass; Notch: notch response; AP: all pass.

Equation (15) reveals that for high-pass and band-pass only two MOS [17]. Equation (15) also indicates that high responses the pole frequency (ω0) and quality factor (Q0) values of Q-factor will be obtained from moderate values of can be adjusted by gm, that is, by bias current of DDCCTA, ratios of passive components, that is, from low component without disturbing ω0/Q0.Theω0 and Q0 are orthogonally spread [22]. These ratios can be chosen as gmR = (C1/C2) = adjustable with simultaneous adjustment of gm and R such Q0. Hence, the spread of the component values becomes of that the product gmR remains constant and the quotient gm/R the order of Q0. This feature of the ﬁlter related to the varies and vice versa. The resistance R being a grounded component spread allows the realization of high Q0 values one may easily be implemented as a variable resistance using more accurately compared to the topologies where the spread Journal of Electrical and Computer Engineering 7

Table 4: The Iin1, Iin2, Iin3,andIin4 values selection for each ﬁlter function response.

Inputs Filter responses Output Iin1 Iin2 Iin3 Iin4

Lowpass0010 Iout2

0010 Iout1

Band pass 1000 Iout2

0100 Iout2

Highpass1000 Iout1

Notch0101Iout2, R = 1/gm

Allpass0101Iout2, R = 1/gm

Table 5: Comparative study of the available similar type of single-active-element-based CM ﬁlters.

No Active Availability No requirement Output element used Grounded of LB, HP, require- Simple/no of gain of current at Reference and number passive BP, notch, ment of Tunability matching input signal high of passive components and AP current condition such as 2I impedance components responses inversion in and 3Iin [11] CCCCTA, 2 Yes Yes Yes No Yes Yes Yes [13] CCCDTA, 2 Yes Yes No Yes No Yes Yes [20] CCCDTA, 2 Yes Yes Yes No Yes Yes Yes [21] CCCCTA, 2 Yes No Yes Yes No Yes Yes Proposed DVCCTA, 3 Yes Yes Yes Yes Yes Yes Yes LP: low pass; HP: high pass; BP: band pass; Notch: notch response; AP: all pass.

I bias also use matching condition. Topology [11] needs input signal Vin, −Vin,and−2Vin; hence there is requirement of additional circuits. Thus, it reveals that although the Y1 Z2+ Iout proposed topology realizes only LP, HP, and BP responses, DDCCTA Z1+ it has two or more advantages over the other available Y2 C1 O1− topologies [11, 15, 18, 19]. Y3 X O2− To verify the functionality of the proposed single- C2 Vout2 DDCCTA-based voltage mode filter, SPICE simulations have V been carried out using TSMC 0.25 μm CMOS process model R out1 parameters and supply voltages of VDD = −VSS = 1.25 V and VBB = −0.8 V. The filter is designed for a pole frequency of f0 = 1.59 MHz, Q = 1, the component values are found to be C1 = C2 = 100 pF, R = 1kΩ,andbiascurrent of DVCCTA equals 100 μA. Figure 7 shows the simulation Figure 10: Proposed Oscillator. results for high-pass (Vout1), band-pass (Vout2), and low-pass (Vout3) filter responses which are available simultaneously.

2 of passive components becomes Q0 or Q0. It can also be 3.2. MISO Current Mode Universal Filter. A multiple-input easily evaluated to show that the sensitivities of pole ω0 and single-output (MISO) universal current mode (CM) filter pole Q0 are within unity in magnitude. Thus, the proposed is proposed in this section which is obtained by grounding structures, can be classified as insensitive. voltage input in Figure 6 and exciting it with current inputs A detailed study of the available similar type of single- as shown in Figure 8. It employs a single DDCCTA, two active-element-based (such as CCCTA, DBTA, and DVCC- grounded capacitors, and a grounded resistor. Analysis of this CTA) voltage mode filters and the proposed one is given in circuit gives the output current as Table 3. It reveals that the topology [18, 19] uses excessive number of passive components whereas the proposed topol- 2 −s C1C2RIin1 − sC2 + gm Iin2 + sC1Iin3 ogy uses one extra passive component, namely, resistor (R) Iout1 = , D(s) than [11, 15]. The proposed topology also provides the avail- (16) ability of a maximum number of simultaneous responses. (I − I )sC Rg + g I + D(s)I I = in1 in2 2 m m in3 in4 , Structures [11, 18, 19] use floating passive components and out2 D(s) 8 Journal of Electrical and Computer Engineering

50 50 A) µ 0 0 Current ( Voltage (mV)

−50 −50 50 51 52 53 54 55 50 51 52 53 54 55 Time (µs) Time (µs)

Vout1 Iout Vout2 (a) (b)

Figure 11: Outputs of the proposed oscillator: (a) quadrature output voltages at Vout1 and Vout2; (b) current oscillation at Iout.

where Ibias = 2 D(s) s C1C2R + sC2 + gm. (17) V in Y1 Z2+ Table 4 shows the availability of each filter response and DDCCTA Z1+ Vout the corresponding selection of input currents Iin1, Iin2, Iin3, Y2 O1− and Iin4. Thus, the proposed structure is a four-input-single- output current mode filter. It may be noted that there is Y3 X O2− no component matching constraint for obtaining any filter response. The filter parameters are the same as given in (15). R Thegroundedresistance(R) may easily be implemented as variable one using only two MOS [17] for full electronic control of filter parameters. The ω0, Q0,andω0/Q0 can be Figure 12: Voltage amplifier. orthogonally adjusted for low-pass, high-pass, and band-pass responses the way discussed in Section 3.1. A detailed study of the available similar type of active- Ibias element-based (such as CCCCTA, CCCDTA, and CCCCTA) CM filters and the proposed one is given in Table 5.Itreveals that although the proposed structure needs one extra resistor, Y1 Z2+ the reported structures [11, 13, 20, 21]suffer from one or DDCCTA Z1+ more features. In addition some active elements are required Y2 O1− I to sense current in [13, 21]. Thus, structures in [11, 13, out R 20, 21] will require some extra circuits to compensate the Y3 X O2− shortcomings in their features in comparison to the proposed one. The proposed universal MISO current mode filter is I validated through SPICE simulations. The circuit of Figure 8 in for a pole frequency of f = 1.59 MHz, Q = 1has 0 Figure 13: Current amplifier. been designed with the component values of C1 = C2 = 100 pF, R = 1kΩ, and bias current of DDCCTA equal to 100 μA. Figure 9(a) shows the simulation results for band pass (Iout1)andlowpass(Iout2) filter responses which are = = = = = Ω Ω = = = = with Iin Iin2 Iin4, Iin1 Iin3 0andR 1k and 2 k , available simultaneously for Iin Iin3, Iin1 Iin2 Iin4 0. respectively. Figure 9(b) shows the simulation results for band pass (Iout2) and high-pass (Iout1) filter responses which are available simultaneously for Iin = Iin1, Iin2 = Iin3 = Iin4 = 0. Notch 3.3. Oscillator. The current mode filter of Figure 8 may be and all pass responses are shown in Figures 9(c) and 9(d) used as oscillator when output Iout2 is connected to Iin1 as Journal of Electrical and Computer Engineering 9

Ibias 3.5

Iin Vin 3 Y1 Z2+ DDCCTA Y2 Z1+ C 2.5 O1− X Y3 O2− 2 Current gain

R 1.5

1 Figure 14: Grounded inductor simulator. 0 50 100 150 200 250 300 350 400 Bias current (µA) 3.5 Figure 16: Current gain.

3 100 k

2.5 10 k

2 Voltage gain 1k in 1.5 Z 100

1 0 50 100 150 200 250 300 350 400 10 Bias current (µA) Figure 15: Voltage gain. 1 10 kHz 100 kHz 1 MHz 10 MHz 100 MHz Frequency shown in Figure 10. The analysis of the circuit of Figure 10 Simulated Theoretical gives the following characteristic equation: Figure 17: Frequency response of grounded inductor. 2 s C1C2R + sC2 Rgm − 1 + gm = 0. (18)

The condition and frequency of oscillation may be computed 3.4. Voltage Amplifier, Current Amplifier, and Grounded as Inductor. The proposed DDCCTA may also be configured for voltage and current amplifiers and grounded inductor = 1 CO: gm , simulator as shown in Figures 12, 13,and14,respectively. R (19) The transfer functions may be expressed as follows: gm (i) voltage amplifier: FO: ω0 = . RC1C2 V 1 out = , (21) The oscillations are available at outputs Vout1 and Vout2,and Vin Rgm they are related as (ii) current amplifier: gm Vout1 = − Vout2. (20) Iout sC2 = Rgm, (22) Iin Thus, these voltages exhibit quadrature relationship. The (iii) grounded inductor simulator: current oscillations are also available at high output impedance at Iout. Vin sCR Zin = = . (23) To verify the proposed circuit, an oscillator was designed Iin gm for 1.59 MHz with C1 = C2 = 100 pF, R = 1kΩ,andbias current of 100 μA. The simulated current and quadrature It may be noted that the gain of amplifiers and inductance voltage waveforms are shown in Figure 11 for which the total can be adjusted by gm, that is, by varying bias current of harmonic distortion is 1.28%. DDCCTA. 10 Journal of Electrical and Computer Engineering

To verify the proposed amplifiers, the simulations have block for analog signal processing,” Electrical Engineering, vol. been carried out for R = 0.5kΩ (2 kΩ) for voltage (current) 90, no. 6, pp. 443–453, 2008. amplifier and bias current of 25 μA to 400 μA. The results are [12] D. Biolek, “CDTA—building block for current-mode analog depicted in Figures 15 and 16. The inductor simulator is also signal processing,” in Proceedings of the European Conference validated through simulation with R = 0.5KΩ, C = 100 pF, on Circuit Theory and Design, (ECCTD ’03), pp. 397–400, Krak and bias current of 90 μA. Figure 17 shows the simulated and ow,´ Poland, September 2003. theoretical results and there is close agreement between the [13] M. Siripruchyanun and W. Jaikla, “CMOS current-controlled current differencing transconductance amplifier and appli- two. cations to analog signal processing,” International Journal of Electronics and Communications, vol. 62, no. 4, pp. 277–287, 4. Conclusion 2008. [14] A. Jantakun, N. Pisutthipong, and M. Siripruchyanun, A new analog building block, namely, DDCCTA, is presented “A synthesis of temperature insensitive/electronically control- and some of its properties are discussed. It is found that lable floating simulators based on DV-CCTAs,” in Proceed- the proposed DDCCTA is useful up to about 201 MHz. As ings of the 6th International Conference on Electrical Engi- applications of the proposed DDCCTA, VM multifunction neering/Electronics, Computer, Telecommunications and Infor- filter, CM universal filter, quadrature oscillator, voltage mation Technology, (ECTI-CON ’09), pp. 560–563, Pattaya, and current amplifiers, and grounded inductor simulator Chonburi, Thailand, May 2009. topology are presented. The resistor being grounded may [15] W. Jaikla, M. Siripruchyanun, and A. Lahiri, “Resistorless easily be implemented as a variable one using only two MOS dual-mode quadrature sinusoidal oscillator using a single active building block,” Microelectronics Journal,vol.42,no.1,pp. [17]. The simulation results verify the theory. 135–140, 2010. [16] H. P. Chen, “Versatile universal voltage-mode filter employing References DDCCs,” International Journal of Electronics and Communica- tions, vol. 63, no. 1, pp. 78–82, 2009. [1] G. Ferri and N. C. Guerrini, Low-Voltage Low-Power CMOS [17] H. P. Chen, “High-input impedance voltage-mode multifunc- Current Conveyors, Kluwer Academic, London, UK, 2003. tion filter with four grounded components and only two plus- [2] R. L. Geiger and E. Sanchez-Sinencio, “Active filter design type DDCCs,” Active and Passive Electronic Components, vol. using operational transconductance amplifiers: a tutorial,” 2010, Article ID 362516, 5 pages, 2010. IEEE Circuits and Devices Magazine, vol. 1, no. 2, pp. 20–23, [18] N. Herencsar, K. Vrba, J. Koton, and I. Lattenberg, “The con- 1985. ception of differential-input buffered and transconductance [3]A.S.SedraandK.C.Smith,“Asecondgenerationcurrent amplifier (DBTA) and its application,” IEICE Electronics Ex- conveyor its application,” IEEE Transactions on Circuit Theory, press, vol. 6, no. 6, pp. 329–334, 2009. vol. 17, no. 1, pp. 132–134, 1970. [19] N. Herencsar,´ J. Koton, K. Vrba, and I. Lattenberg, “New [4] A. Fabre, O. Saaid, F. Wiest, and C. Boucheron, “High frequen- voltage-mode universal filter and sinusoidal oscillator using cy applications based on a new current controlled conveyor,” only single DBTA,” International Journal of Electronics, vol. 97, IEEE Transactions on Circuit and Systems I, vol. 43, pp. 82–91, no. 4, pp. 365–379, 2010. 1996. [20] M. Siripruchyanun and W. Jaikla, “Electronically control- [5] I. A. Awad and A. M. Soliman, “Inverting second generation lable current-mode universal biquad filter using single DO- current conveyors: the missing building blocks, CMOS real- CCCDTA,” Circuits, Systems, and Signal Processing, vol. 27, no. izations and applications,” International Journal of Electronics, 1, pp. 113–122, 2008. vol. 86, no. 4, pp. 413–432, 1999. [21] S. Mangkalakeeree, D. Duangmalai, and M. Siripruchyanun, [6] H. O. Elwan and A. M. Soliman, “Novel CMOS differential “Current-mode KHN filter using single CCCCTA,” in Proceed- voltage current conveyor and its applications,” IEE Proceed- ings of the 7th PSU Engineering Conference, pp. 306–309, Hat- ings—Circuits Devices Systems, vol. 144, pp. 195–200. Yai, Thailand, May 2009. [7] W. Chiu, S. I. Liu, H. W. Tsao, and J. J. Chen, “CMOS dif- [22] S. I. Liu, “High input impedance filters with low component ferential difference current conveyor and their applications,” spread using current-feedback amplifiers,” Electronics Letters, IEE Proceedings—Circuits Devices Systems, vol. 143, pp. 91–96, vol. 31, no. 13, pp. 1042–1043, 1995. 1996. [8] C. Toumazou and A. Payne, “Current feedback opamp: a blessing in disguise?” IEEE Circuits and Devices Magazine, vol. 10, pp. 43–47, 1994. [9] R. Prokop and V. Musil, “CCTA-a new modern circuit block and its internal realization,” in Proceedings of the International Conference on Electronic Devices and Systems, (IMAPSCZ ’05), pp. 89–93, Brno, Czech Republic, 2005. [10] W. Jaikla, P. Silapan, C. Chanapromma, and M. Siripruchya- nun, “Practical implementation of CCTA based on com- mercial CCII and OTA,” in Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, (ISPACS ’08), pp. 1–4, Bangkok, Thailand, February 2009. [11] M. Siripruchyanun and W. Jaikla, “Current controlled current conveyor transconductance amplifier (CCCCTA): a building Copyright of Journal of Electrical & Computer Engineering is the property of Hindawi Publishing Corporation and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use.