CMOS Cascode Transconductance Amplifier

■ Basic topology.

5 V

ISUP

iOUT Device Data + = = − V VTn 1 V VTp 1 V G2 M2 C v L OUT µ = µ / 2 nCox 50 A V R − S µ = µ / 2 pCox 25 A V M1 + λ = −1 λ = −1 = µ v n 0.05 V p 0.02 V @ L 2 m s − + V BIAS −

(a) (b)

■ Current supply must have a very high source resistance roc since otherwise it will limit the output resistance of the amplifier

EECS 105 Fall 1998 Lecture 26 Current Supply Topology

■ p-channel cascode current supply is a obvious solution

5 V

V G4 M4 ISUP

V G3 M3

iOUT

VG2 M2 CL vOUT − RS M1 v + s −

+ V BIAS −

■ need to design a totem pole voltage supply to generate VG2, VG3, and VG4

EECS 105 Fall 1998 Lecture 26 Totem Pole Voltage Reference

■ Match device sizes of M2B, M3B, and M4B to M2, M3, and M4

5 V

M4B VG4

M3B VG3

V M2B G2

IREF

EECS 105 Fall 1998 Lecture 26 Complete Transconductance Amplifier

■ ≈ VBIAS: user must supply a very precise DC voltage VBIAS 1.2 V so that the CS/CGcascode is biased so that it is in the high gain region

= / 5 V M1 200 2 = = / M2 M2B 50 2 M 3.5 V = = / 4B M4 M3 M3B 64 2 = = / 3.5 V M4 M4B 64 2 M 2.0 V 3B M3 i 2.0 V OUT + 2.0 V M M v 2B 2 CL OUT 0.6 V − RS M I = 100 µA 1 REF + v s − + V BIAS − 1.2 V

■ Overall two-port parameters: Gm = gm1

Output resistance: Rout = ro2(1 + gm2 ro1) || ro3(1 + gm3 ro4) ■ Output swing:

VOUT(max) = VD4 - VSD3(sat) = VDD - VSG4B - VSG3B + VSG3 - VSD3(sat)

VOUT(max) = 5 V - 1.5 V - 1.5 V + 1.5 V - 0.5 V = 3.0 V

VOUT(min) = VD1 + VDS2(sat) = VG2 - VGS2 + VDS2(sat) = 2 V - 1.4 V + 0.4 V = 1 V

EECS 105 Fall 1998 Lecture 26 Multistage Voltage Amplifier

■ Example to understand a complicated circuit

5 V

3.5 V M7 M7B M5 4.5 V R 35 kΩ 3.5 V Q M 2.0 V 3.0 V 4 6B M6 3.0 V 2.0 V M 1.5 V 3 100 µA Q 2.0 V 3.8 V 2B Q2 2.8 V vOUT 2.3 V

RS M1 + v s −

1.5 V M M 8 M + 10 9 V − BIAS

■ 10 MOSFETs, 3 BJTs, 1 resistor ... must identify building blocks Step-by-step approach to identifying the “important” transistors -- 1. replace all transistor current sources and voltage sources by their symbols -- look for diodes and current mirrors! (M5, M6/M6B, M7/M7B, and M10 and Q2B are part of current sources or a totem pole voltage reference.) 2. for the (few) remaining transistors, identify the type and use two-port small- signal models to understand the circuit’s operation. (For the above amplifier, the remaining transistors are M1, Q2, M3, and Q4.)

EECS 105 Fall 1998 Lecture 26 Eliminating Current and Voltage Sources

■ Replace current and voltage sources with symbols

VDD = 5 V

-ID5

-ID6 Q4

VB2 Q2 vOUT

RS + M v 1 s_ ID10 V + BIAS_

EECS 105 Fall 1998 Lecture 26 Identifying Amplifier Stages

■ n-channel MOSFET M1 has its source grounded --> common source

■ npn BJT Q2 has its gate tied to a voltage source (from “totem pole” string of diode-connected transistors) --> common base

■ p-channel MOSFET M3 has its drain connected to ground --> common drain

■ npn BJT Q4 has its collector tied to the positive supply --> common collector

Voltage amplifier is a cascade of two-port models:

CS CB CD CC

Rin Rout(CS/CB) Rout

1. common source/common base with cascoded current-source supply: very high output resistance Rout(CS/CB) --> can get extremely high output resistance, with a transconductance equal to that of the CS stage 2. common drain: no loading on previous stage since infinite input resistance 3. common collector: low output resistance

EECS 105 Fall 1998 Lecture 26 Cascode Stage Output Resistance

■ Cascode input stage output resistance determines gain

VDD = 5 V

-ID6

Rout,CB/CS

VB2 Q2

RS2 RS M1 V + BIAS _

■ Output resistance: note that RS2 = ro1 >> rπ2 ()β ()β ()() Rout,CB ==o2ro2 roc6 oro2 ro6 1 + gm6ro7

EECS 105 Fall 1998 Lecture 26 Overall Two-Port Parameters

■ Since CC and CD stages have unity gain (approximately), we can quickly estimate the voltage gain by finding vin3/vin where vin3 is the input to the CD stage ■ Voltage gain:

≈ () ()()β ()() Av –gm1 Rout,CB = –gm1 oro2 ro6 1 + gm6ro7

■ Output resistance: source resistance of CC output stage is relatively small, since it preceded by a CD stage.

R ≈ 1 S,CC 1 1 Rout = Rout,CC ------+ ------β = ------+ ------β - gm4 o4 gm4 gm3 o4

EECS 105 Fall 1998 Lecture 26 DC Bias and Output Swing

■ Assuming all n-channel devices have VGS = 1.5 V and p-channel devices have VSG = 1.5 V, we can find all the node voltages ... we also assume that VBIAS has been adjusted such that the circuit is in the high-gain region

5 V

3.5 V M7 M7B M5 4.5 V R 35 kΩ 3.5 V Q M 2.0 V 3.0 V 4 6B M6 3.0 V 2.0 V M 1.5 V 3 100 µA Q 2.0 V 3.8 V 2B Q2 2.8 V vOUT 2.3 V

RS M1 + v s −

1.5 V M M 8 M + 10 9 V − BIAS

■ Output swing: must consider more than output stage to find limits to VOUT

EECS 105 Fall 1998 Lecture 26