EECE488: Analog CMOS Integrated Circuit Design
Set 2: Background
Shahriar Mirabbasi
Department of Electrical and Computer Engineering University of British Columbia [email protected]
Technical contributions of Pedram Lajevardi in revising the slides is greatly acknowledged.
SM 1 EECE 488 – Set 2: Background
Overview
1. Reading Assignments 2. Structure of MOS Transistors 3. Threshold Voltage 4. Long-Channel Current Equations 5. Regions of Operation 6. Transconductance 7. Second-Order Effects 8. Short-Channel Effects 9. MOS Layout 10.Device Capacitances 11.Small-signal Models 12.Circuit Impedance 13.Equivalent Transconductance
SM 2 EECE 488 – Set 2: Background
SM 1 Reading Assignments
• Reading:
Chapter 2 of the textbook
Section 16.2 of the textbook
Chapter 17
All the figures in the lecture notes are © Design of Analog CMOS Integrated Circuits , McGraw-Hill, 2001, unless otherwise noted.
SM 3 EECE 488 – Set 2: Background
Transistor
• Transistor stands for …
• Transistor are semiconductor devices that can be classified as
– Bipolar Junction Transistors (BJTs)
– Field Effect Transistors (FETs)
• Depletion-Mode FETs or (e.g., JFETs)
• Enhancement-Mode FETs (e.g., MOSFETs)
SM 4 EECE 488 – Set 2: Background
SM 2 Simplistic Model
• MOS transistors have three terminals: Gate, Source, and Drain
• The voltage of the Gate terminal determines the type of connection between Source and Drain (Short or Open). • Thus, MOS devices behave like a switch
NMOS PMOS
VG high Device is ON Device is OFF D is shorted to S D & S are disconnected
VG low Device is OFF Device is ON D & S are disconnected D is shorted to S
SM 5 EECE 488 – Set 2: Background
Physical Structure - 1
• Source and Drain terminals are identical except that Source provides charge carriers, and Drain receives them. • MOS devices have in fact 4 terminals: – Source, Drain, Gate, Substrate (bulk)
© Microelectronic Circuits, 2004 Oxford University Press
SM 6 EECE 488 – Set 2: Background
SM 3 Physical Structure - 2
• Charge Carriers are electrons in NMOS devices, and holes in PMOS devices. • Electrons have a higher mobility than holes • So, NMOS devices are faster than PMOS devices • We rather to have a p-type substrate?!
LD: Due to Side Diffusion
Poly-silicon used instead of Metal for fabrication reasons
• Actual length of the channel (L eff ) is less than the length of gate
SM 7 EECE 488 – Set 2: Background
Physical Structure - 3
• N-wells allow both NMOS and PMOS devices to reside on the same piece of die.
• As mentioned, NMOS and PMOS devices have 4 terminals: Source, Drain, Gate, Substrate (bulk) • In order to have all PN junctions reverse-biased, substrate of NMOS is connected to the most negative voltage, and substrate of PMOS is connected to the most positive voltage.
SM 8 EECE 488 – Set 2: Background
SM 4 Physical Structure - 4
• MOS transistor Symbols:
• In NMOS Devices: Source electron → Drain Current flows from Drain to Source
• In PMOS Devices: Source hole→ Drain Current flows from Source to Drain
• Current flow determines which terminal is Source and which one is Drain. Equivalently, source and drain can be determined based on their relative voltages.
SM 9 EECE 488 – Set 2: Background
Threshold Voltage - 1
• Consider an NMOS: as the gate voltage is increased, the surface under the gate is depleted. If the gate voltage increases more, free electrons appear under the gate and a conductive channel is formed.
(a) An NMOS driven by a gate voltage, (b) formation of depletion region, (c) onset of inversion, and (d) channel formation • As mentioned before, in NMOS devices charge carriers in the channel under the gate are electrons.
SM 10 EECE 488 – Set 2: Background
SM 5 Threshold Voltage - 2
• Intuitively, the threshold voltage is the gate voltage that forces the interface (surface under the gate) to be completely depleted of charge (in NMOS the interface is as much n-type as the substrate is p-type)
• Increasing gate voltage above this threshold (denoted by VTH or Vt) induces an inversion layer (conductive channel) under the gate.
© Microelectronic Circuits, 2004 Oxford University Press
SM 11 EECE 488 – Set 2: Background
Threshold Voltage - 3
Analytically: Q = Φ + ⋅ Φ + dep VTH MS 2 F Cox Where: Φ = = Φ − Φ MS Built in- Potential gate Silicon = the difference between the work functions of the polysilico n gate and the silicon substrate
K ⋅T N Φ = Work Function (electrost atic potential) = ⋅ ln sub F q ni = = ⋅ ⋅ε ⋅ Φ ⋅ Qdep Charge in the depletion region 4 q si F N sub
SM 12 EECE 488 – Set 2: Background
SM 6 Threshold Voltage - 4
• In practice, the “native” threshold value may not be suited for circuit design, e.g., VTH may be zero and the device may be on for any positive gate voltage.
• Typically threshold voltage is adjusted by ion implantation into the channel surface (doping P-type material will increase VTH of NMOS devices).
• When VDS is zero, there is no horizontal electric field present in the channel, and therefore no current between the source to the drain.
• When VDS is more than zero, there is some horizontal electric field which causes a flow of electrons from source to drain.
SM 13 EECE 488 – Set 2: Background
Long Channel Current Equations - 1
• The voltage of the surface under the gate, V(x), depends on the voltages of Source and Drain.
• If VDS is zero, VD= VS=V(x). The charge density Qd (unit C/m) is uniform. − Q − C ⋅V − (C WL )⋅ (V −V ) Q = = = ox GS TH d L L L
= − − Qd WC ox (VGS VTH )
• If VDS is not zero, the channel is tapered, and V(x) is not constant. The charge density depends on x.
= − − − Qd (x) WC ox (VGS V (x) VTH )
SM 14 EECE 488 – Set 2: Background
SM 7 Long Channel Current Equations - 3
• Current : dQ dQ dx I = = × = Q ⋅ velocity dt dx dt d Velocity in terms of V(x): dV velocity = µ ⋅ E , E = − dt − dV (x) → velocity = (µ ⋅ ) dx Qd in terms of V(x): = − − − Qd (x) WC ox (VGS V (x) VTH ) • Current in terms of V(x): dV (x) © Microelectronic Circuits, 2004 Oxford University Press I = WC [V −V (x) −V ]µ D ox GS TH n dx L V = DS µ − − ∫ I D dx ∫WC ox n [VGS V (x) VTH ]dV x=0 V =0 • Long-channel current equation: W 1 I = µ C [( V −V )V − V 2 ] D n ox L GS TH DS 2 DS
SM 15 EECE 488 – Set 2: Background
Long Channel Current Equations - 4
• If V DS ≤ V GS -VTH we say the device is operating in triode (or linear) region. W 1 • Current in Triode Region: I = µ ⋅ C ⋅ ⋅ ()V −V ⋅V − ⋅V 2 D n ox L GS TH DS 2 DS
• Terminology: W Aspect Ratio = L = = − = Overdrive Voltage Effective Voltage VGS VTH Veff
SM 16 EECE 488 – Set 2: Background
SM 8 Long Channel Current Equations - 5
• For very small VDS (deep Triode Region):
ID can be approximated to be a linear function of VDS .
The device resistance will be independent of VDS and will only depend on Veff . The device will behave like a variable resistor
<< ( − ) If VDS 2 VGS VTH : W I = µ ⋅ C ⋅ ⋅ ()V −V ⋅V D n ox L GS TH DS V 1 R = DS = ON I W D µ ⋅C ⋅ ⋅()V −V n ox L GS TH
SM 17 EECE 488 – Set 2: Background
Long Channel Current Equations - 6
• Increasing VDS causes the channel to acquire a tapered shape. Eventually, as VDS reaches VGS –VTH the channel is pinched off at the drain. Increasing VDS above VGS –VTH has little effect (ideally, no effect) on the channel’s shape.
© Microelectronic Circuits, 2004 Oxford University Press
• When VDS is more than VGS –VTH the channel is pinched off, and the horizontal electric field produces a current.
SM 18 EECE 488 – Set 2: Background
SM 9 Long Channel Current Equations - 7
• If VDS > VGS –VTH , the transistor is in saturation (active) region, and the channel is pinched off.
L' V −V = GS TH µ − − ∫ I D dx ∫WC ox n [VGS V (x) VTH ]dV x=0 V =0 1 W I = µ C (V −V ) 2 D 2 n ox L' GS TH • Let’s, for now, assume that L’=L. The fact that L’ is not equal to L is a second-order effect known as channel-length modulation.
• Since ID only depends on VGS , MOS transistors in saturation can be used as current sources.
SM 19 EECE 488 – Set 2: Background
Long Channel Current Equations - 8
• Current Equation for NMOS:
0 ; if V < V (Cut − off ) GS TH µ ⋅ ⋅ W ⋅ − ⋅ > << − n Cox ()VGS VTH VDS ; if VGS VTH , VDS (2 VGS VTH () Deep Triode ) L = = I D I DS W 1 µ ⋅ ⋅ ⋅[]− ⋅ − ⋅ 2 > < − n Cox ()VGS VTH VDS VDS ; if VGS VTH , VDS VGS VTH (Triode ) L 2 1 W ⋅ µ ⋅ C ⋅ ⋅ (V −V ) 2 ; if V > V , V > V −V (Saturation ) 2 n ox L GS TH GS TH DS GS TH
SM 20 EECE 488 – Set 2: Background
SM 10 Long Channel Current Equations - 9
• Current Equation for PMOS:
< − 0 ; if VSG VTH (Cut off ) µ ⋅ ⋅ W ⋅ − ⋅ > << − p Cox ()VSG VTH VSD ; if VSG VTH , VSD (2 VSG VTH () Deep Triode ) L = = I D I SD W 1 µ ⋅ ⋅ ⋅[]− ⋅ − ⋅ 2 > < − p Cox ()VSG VTH VSD VSD ; if VSG VTH , VSD VSG VTH (Triode ) L 2 1 W ⋅ µ ⋅C ⋅ ⋅ (V − V )2 ; if V > V , V > V − V (Saturation ) 2 p ox L SG TH SG TH SD SG TH
SM 21 EECE 488 – Set 2: Background
Regions of Operation - 1
• Regions of Operation: Cut-off, triode (linear), and saturation (active or pinch-off)
© Microelectronic Circuits, 2004 Oxford University Press • Once the channel is pinched off, the current through the channel is almost constant. As a result, the I-V curves have a very small slope in the pinch-off (saturation) region, indicating the large channel resistance.
SM 22 EECE 488 – Set 2: Background
SM 11 Regions of Operation - 2
• The following illustrates the transition from pinch-off to triode region for NMOS and PMOS devices.
• ForNMOS devices:
If VD increases (V G Const.), the device will go from Triode to Pinch-off.
If VG increases (V D Const.), the device will go from Pinch-off to Triode.
** In NMOS, as VDG increases the device will go from Triode to Pinch-off. • ForPMOS devices:
If VD decreases (V G Const.), the device will go from Triode to Pinch-off.
If VG decreases (V D Const.), the device will go from Pinch-off to Triode.
** In PMOS, as VGD increases the device will go from Pinch-off to Triode.
SM 23 EECE 488 – Set 2: Background
Regions of Operation - 3
• NMOS Regions of Operation:
© Microelectronic Circuits, 2004 Oxford University Press
• Relative levels of the terminal voltages of the enhancement-type NMOS transistor for different regions of operation.
SM 24 EECE 488 – Set 2: Background
SM 12 Regions of Operation - 4
• PMOS Regions of Operation:
© Microelectronic Circuits, 2004 Oxford University Press
• The relative levels of the terminal voltages of the enhancement-type PMOS transistor for different regions of operation.
SM 25 EECE 488 – Set 2: Background
Regions of Operation - 5
Example:
For the following circuit assume that VTH =0.7V. • Whenis the device on?
• What is the region of operation if the device is on?
• Sketch the on-resistance of transistor M1 as a function of VG.
SM 26 EECE 488 – Set 2: Background
SM 13 Transconductance - 1
• The drain current of the MOSFET in saturation region is ideally a function of gate-overdrive voltage (effective voltage). In reality, it is also
a function of VDS .
• It makes sense to define a figure of merit that indicates how well the device converts the voltage to current.
• Which current are we talking about?
• What voltage is in the designer’s control?
• What is this figure of merit?
∂I g = D m ∂ = VGS VDS Const .
SM 27 EECE 488 – Set 2: Background
Transconductance - 2
Example:
Plot the transconductance of the following circuit as a function of VDS (assume Vb is a constant voltage).
• Transconductance in triode: ∂ W 1 g = µ ⋅C ⋅ ⋅[()V −V ⋅V − ⋅V 2 ] m ∂ n ox GS TH DS DS = VGS L 2 VDS Const . W = µ ⋅ C ⋅ ⋅V n ox L DS • Transconductance in saturation: ∂ 1 W g = ⋅ µ ⋅C ⋅ ⋅(V −V ) 2 m ∂ n ox GS TH = VGS 2 L VDS Const . W = µ ⋅C ⋅ ⋅ (V −V ) n ox L GS TH • Moral: Transconductance drops if the device enters the triode region.
SM 28 EECE 488 – Set 2: Background
SM 14 Transconductance - 3
• Transconductance,gm, in saturation: W W 2 ⋅ I g = µ ⋅C ⋅ ⋅ (V −V ) = 2µ ⋅C ⋅ ⋅ I = D m n ox GS TH n ox D − L L VGS VTH
• If the aspectratio is constant:gm depends linearly on (V GS -VTH ).
Also, gm depends on square root of ID.
• If ID is constant: gm is inversely proportional to (V GS -VTH ).
Also, gm depends on square root of the aspect ratio.
• If the overdrive voltage is constant: gm depends linearly on ID.
Also, gm depends linearly on the aspect ratio.
SM 29 EECE 488 – Set 2: Background
Second-Order Effects (Body Effect)
Substrate Voltage: • So far, we assumed that the bulk and source of the transistor are at the same voltage (V B=V S). • If VB >V s, then the bulk-source PN junction will be forward biased, and the device will not operate properly.
• If VB – the depletion region widens, and Qdep increases. –VTH will be increased (Body effect or Backgate effect). • It can be shown that (what is the unit for γ ?) : ⋅ ⋅ε ⋅ 2 q si Nsub VTH = VTH 0 + γ ⋅ 2⋅ΦF +VSB − 2 ⋅ΦF where γ = Cox SM 30 EECE 488 – Set 2: Background SM 15 Body Effect - 2 Example: Consider the circuit below (assume the transistor is in the active region): • If body-effect is ignored, VTH will be constant, and I1 will only depend on VGS1=V in -Vout . Since I1 is constant, Vin -Vout remains constant. − − = = → − = + = = Vin Vout VTH C Const . Vin Vout VTH C D Conts . • In general, I1 depends on VGS1-VTH =V in -Vout -VTH (and with body effect VTH is not constant). Since I1 is constant, Vin -Vout -VTH remains constant: − − = = → − = + Vin Vout VTH C Const . Vin Vout VTH C • As Vout increases, VSB1 increases, and as a result VTH increases. Therefore, Vin -Vout Increases. No Body Effect With Body Effect SM 31 EECE 488 – Set 2: Background Body Effect - 3 Example: For the following Circuit sketch the drain current of transistor M1 when VX γ 1/2 Φ varies from -∞ to 0. Assume VTH0=0.6V, =0.4V , and 2 F=0.7V. SM 32 EECE 488 – Set 2: Background SM 16 Channel Length Modulation - 1 • When a transistor is in the saturation region (V DS > VGS –VTH ), the channel is pinched off. L = 1 µ W − 2 = ∆ • The drain current is ID nCox (VGS VTH ) where L' L- L 2 L' 1 1 1 1 1 = = ⋅ ≈ ⋅ (1+ ∆L ) L' L − ∆L L 1− ∆L L L L 1 1 ∆ 1 • Assuming∆L = λ ⋅V weget: ≈ ⋅ (1+ L )= ⋅ ()1+ λ ⋅V L DS L' L L L DS 1 W 1 W • The drain current is I = µ C (V −V )2 ≈ µ C ()()V −V 2 ⋅ 1+ λ ⋅V D 2 n ox L' GS TH 2 n ox L GS TH DS • As ID actually depends on both VGS and VDS , MOS transistors are not ideal current sources (why?). SM 33 EECE 488 – Set 2: Background Channel Length Modulation - 2 • λ represents the relative variation in effective length of the channel for a given . increment in VDS • For longer channels λ is smaller, i.e., λ ∝ 1/L ∂I • Transconductance: g = D m ∂ = VGS VDS Const . In Triode: W g = µ ⋅C ⋅ ⋅V m n ox L DS In Saturation (ignoring channel length modulation): W W 2 ⋅ I g = µ ⋅C ⋅ ⋅(V −V ) = 2µ ⋅C ⋅ ⋅ I = D m n ox GS TH n ox D − L L VGS VTH In saturation with channel length modulation: W W 2 ⋅ I g = µ ⋅C ⋅ ⋅(V −V ) ⋅ ()1+ λ ⋅V = 2µ ⋅C ⋅ ⋅ I ⋅ ()1+ λ ⋅V = D m n ox GS TH DS n ox D DS − L L VGS VTH . • The dependence of ID on VDS is much weaker than its dependence on VGS SM 34 EECE 488 – Set 2: Background SM 17 Channel Length Modulation - 3 Example: Given all other parameters constant, plot ID-VDS characteristic of an NMOS for L=L 1 and L=2L1 ≈ µ ⋅ ⋅ W ⋅ − ⋅ − 1 ⋅ 2 • InTriode Region: ID n Cox []()VGS VTH VDS VDS L 2 ∂I W Therefore : D ∝ ∂ VDS L ≈ 1 µ W ()()− 2 ⋅ + λ ⋅ • In Saturation Region: ID nCox VGS VTH 1 VDS 2 L ∂I 1 W So we get : D = µ C ()V −V 2 ⋅λ ∂ n ox GS TH VDS 2 L ∂I W ⋅λ W Therefore : D ∝ ∝ ∂ 2 VDS L L • Changing the length of the device from L1 to 2L1 will flatten the ID-VDS curves (slope will be divided by two in triode and by four in saturation). • Increasing L will make a transistor a better current source, while degrading its current capability. • Increasing W will improve the current capability. SM 35 EECE 488 – Set 2: Background Sub-threshold Conduction • If VGS < VTH , the drain current is not zero. • The MOS transistors behave similar to BJTs. VBE = ⋅ VT • In BJT: I C I S e VGS ζ ⋅ = ⋅ VT • In MOS: I D I 0 e • As shown in the figure, in MOS transistors, the drain current drops by one decade for approximately each 80mV of drop in VGS . • In BJT devices the current drops faster (one decade for approximately each 60mv of drop in VGS ). • This current is known as sub-threshold or weak-inversion conduction. SM 36 EECE 488 – Set 2: Background SM 18 CMOS Processing Technology • Top and side views of a typical CMOS process SM EECE 588 – Set 1: Introduction and Background 37 CMOS Processing Technology • Different layers comprising CMOS transistors SM EECE 588 – Set 1: Introduction and Background 38 SM 19 Photolithography (Lithography) • Used to transfer circuit layout information to the wafer SM EECE 588 – Set 1: Introduction and Background 39 Typical Fabrication Sequence SM 40 SM 20 Self-Aligned Process • Why source and drain junctions are formed after the gate oxide and polysilicon layers are deposited? SM EECE 588 – Set 1: Introduction and Background 41 Back-End Processing • Oxide spacers and silicide SM EECE 588 – Set 1: Introduction and Background 42 SM 21 Back-End Processing • Contact and metal layers fabrication SM EECE 588 – Set 1: Introduction and Background 43 Back-End Processing • Large contact areas should be avoided to minimize the possibility of spiking SM EECE 588 – Set 1: Introduction and Background 44 SM 22 MOS Layout - 1 • It is beneficialto have some insight into the layout of the MOS devices. • When laying out a design, there are many important parameters we need to pay attention to such as: drain and source areas, interconnects, and their connections to the silicon through contact windows. • Design rules determine the criteria that a circuit layout must meet for a given technology. Things like, minimum length of transistors, minimum area of contact windows, … SM 45 EECE 488 – Set 2: Background MOS Layout - 2 Example: Figures below show a circuit with a suggested layout. • The same circuit can be laid out in different ways, producing different electrical parameters (such as different terminal capacitances). SM 46 EECE 488 – Set 2: Background SM 23 Device Capacitances - 1 • The quadratic model determines the DC behavior of a MOS transistor. • The capacitances associated with the devices are important when studying the AC behavior of a device. • There is a capacitance between any two terminals of a MOS transistor. So there are 6 Capacitances in total. • The Capacitance between Drain and Source is negligible (C DS =0). • These capacitances will depend on the region of operation (Bias values). SM 47 EECE 488 – Set 2: Background Device Capacitances - 2 • The following will be used to calculate the capacitances between terminals: ε = ⋅ ⋅ C = ox 1. Oxide Capacitance: C 1 W L C ox , ox tox q ⋅ε ⋅ N C = C = W ⋅ L ⋅ si sub 2. Depletion Capacitance: 2 dep ⋅Φ 4 F = = = ⋅ ⋅ + 3. Overlap Capacitance: C3 C4 Cov W LD Cox C fringe 4. Junction Capacitance: Sidewall Capacitance: C jsw C = j0 C jun m V 1+ R Bottom-plate Capacitance: C j Φ B = = + C5 C6 C j C jsw SM 48 EECE 488 – Set 2: Background SM 24 Device Capacitances - 3 In Cut-off: C = C = C 1. CGS : is equal to the overlap capacitance. GS ov 3 = = CGD Cov C4 2. CGD : is equal to the overlap capacitance. 3. CGB : is equal to Cgate-channel = C1 in series with Cchannel-bulk = C2. 4. CSB : is equal to the junction capacitance between source and bulk. 5. CDB : is equal to the junction capacitance between source and bulk. = CSB C5 = CDB C6 SM 49 EECE 488 – Set 2: Background Device Capacitances - 4 In Triode: • The channel isolates the gate from the substrate. This means that if VG changes, the charge of the inversion layer are supplied by the drain and source as long as VDS is close to zero. So, C1 is divided between gate and drain terminals, and gate and source terminals, and C2 is divided between bulk and drain terminals, and bulk and source terminals. C = + 1 1. C : CGS Cov GS 2 C 2. CGD : C = C + 1 GD ov 2 = 3. CGB : the channel isolates the gate from the substrate. CGB 0 C = + 2 4. C : CSB C5 SB 2 C2 5. CDB : C = C + DB 6 2 SM 50 EECE 488 – Set 2: Background SM 25 Device Capacitances - 5 In Saturation: • The channel isolates the gate from the substrate. The voltage across the channel varies which can be accounted for by adding two equivalent capacitances to the source. One is between source and gate, and is equal to two thirds of C1. The other is between source and bulk, and is equal to two thirds of C2. 2 C = C + C 1. CGS : GS ov 3 1 = 2. CGD : CGD Cov C = 0 3. CGB : the channel isolates the gate from the substrate. GB 2 4. CSB : C = C + C SB 5 3 2 = 5. CDB : CDB C6 SM 51 EECE 488 – Set 2: Background Device Capacitances - 6 • Insummary: Cut-off Triode Saturation 2 C1 + C Cov C + Cov C1 GS ov 2 3 C C + 1 C CGD ov Cov ov 2 C ⋅C C 1 2 〈C 〈C GB + GB 1 0 0 C1 C2 C + 2 2 C5 + CSB C5 C C 2 5 3 2 C + 2 C C C C6 6 DB 6 2 SM 52 EECE 488 – Set 2: Background SM 26 Importance of Layout Example (Folded Structure): Calculate the gate resistance of the circuits shown below. Folded structure: • Decreases the drain capacitance • Decreases the gate resistance • Keeps the aspect ratio the same SM EECE 588 – Set 1: Introduction and Background 53 Passive Devices SM EECE 588 – Set 1: Introduction and Background 54 SM 27 Passive Devices • Capacitors: SM EECE 588 – Set 1: Introduction and Background 55 Passive Devices • Capacitors SM EECE 588 – Set 1: Introduction and Background 56 SM 28 Passive Devices SM EECE 588 – Set 1: Introduction and Background 57 Latch-Up • Due to parasitic bipolar transistors in a CMOS process SM EECE 588 – Set 1: Introduction and Background 58 SM 29 Small Signal Models - 1 • Small signal model is an approximation of the large-signal model around the operation point. • In analog circuits most MOS transistors are biased in saturation region. • Ingeneral,ID is a function of VGS ,VDS , and VBS . We can use this Taylor series approximation: ∂I ∂I ∂I Taylor Expansion : I = I + D ⋅ ∆V + D ⋅ ∆V + D ⋅ ∆V + second order term s D D0 ∂ GS ∂ DS ∂ BS VGS VDS VBS ∂I ∂I ∂I ∆V ∆I ≈ D ⋅ ∆V + D ⋅ ∆V + D ⋅ ∆V = g ⋅ ∆V + DS + g ⋅ ∆V D ∂ GS ∂ DS ∂ BS m GS mb BS VGS VDS VBS ro SM 59 EECE 488 – Set 2: Background Small Signal Models - 2 1 W 1 W • Currentin Saturation: I = µ C (V −V ) 2 ≈ µ C ()()V −V 2 ⋅ 1+ λ ⋅V D 2 n ox L' GS TH 2 n ox L GS TH DS ∂I ∂I ∂I ∆I ≈ D ⋅ ∆V + D ⋅ ∆V + D ⋅ ∆V • Taylor approximation: D ∂ GS ∂ DS ∂ BS VGS VDS VBS • PartialDerivatives: ∂I W D = µ ⋅C ⋅ ⋅ (V −V ) ⋅ ()1+ λ ⋅V = g ∂ n ox GS TH DS m VGS L ∂I 1 W 1 D = ⋅ µ ⋅C ⋅ ⋅ (V −V )2 ⋅ λ ≈ I ⋅ λ = ∂ n ox GS TH D VDS 2 L ro ∂I ∂I ∂V W γ D = D ⋅ TH = − µ ⋅ ⋅ ⋅ − ⋅ ()+ λ ⋅ ⋅ − n Cox (VGS VTH ) 1 VDS ∂V ∂V ∂V L ⋅Φ + BS TH BS 2 2 F VSB γ = −g ⋅ − = g ⋅η = g m ⋅Φ + m mb 2 2 F VSB SM 60 EECE 488 – Set 2: Background SM 30 Small Signal Models - 3 • Small-SignalModel: v = ⋅ + DS + ⋅ iD g m vGS g mb vBS ro • Terms, gmvGS and gmb vBS , can be modeled by dependent sources. These terms have the same polarity: increasing vG, has the same effect as increasing vB. • The term, vDS /r o can be modeled using a resistor as shown below. SM 61 EECE 488 – Set 2: Background Small Signal Models - 4 • Complete Small-Signal Model with Capacitances: • Small signal model including all the capacitance makes the intuitive (qualitative) analysis of even a few-transistor circuit difficult! • Typically, CAD tools are used for accurate circuit analysis • For intuitive analysis we try to find a simplest model that can represent the role of each transistor with reasonable accuracy. SM 62 EECE 488 – Set 2: Background SM 31 Circuit Impedance - 1 • It is often useful to determine the impedance of a circuit seen from a specific pair of terminals. • The following is the recipeto do so: 1. Connect a voltage source, VX, to the port. 2. Suppress all independent sources. 3. Measure or calculateIX. V = X RX I X SM 63 EECE 488 – Set 2: Background Circuit Impedance - 2 Example: • Find the small-signal impedance of the following current sources. • We draw the small-signal model, which is the same for both circuits, and connect a voltage source as shown below: v v = X + ⋅ = X iX gm vGS ro ro v = X = RX ro iX SM 64 EECE 488 – Set 2: Background SM 32 Circuit Impedance - 3 Example: • Find the small-signal impedance of the following circuits. • We draw the small-signal model, which is the same for both circuits, and connect a voltage source as shown below: v v = X − ⋅ − ⋅ = X + ⋅ + ⋅ iX gm vGS gmb vBS gm vX gmb vX ro ro v 1 1 1 R = X = = r X 1 o iX + + g m gmb gm gmb ro SM 65 EECE 488 – Set 2: Background Circuit Impedance - 4 Example: • Find the small-signal impedance of the following circuit. This circuit is known as the diode-connected load, and is used frequently in analog circuits. • We draw the small-signal model and connect the voltage source as shown below: v v 1 i = X + g ⋅ v = X + g ⋅ v = v ⋅ + g X m GS m X X m ro ro ro v 1 1 R = X = = r X 1 o iX + gm gm ro • If channel length modulation is ignored (r o=∞) we get: = 1 = ∞ 1 = 1 RX ro g m gm g m SM 66 EECE 488 – Set 2: Background SM 33 Circuit Impedance - 5 Example: • Find the small-signal impedance of the following circuit. This circuit is a diode-connected load with body effect. v v = X − ⋅ − ⋅ = X + ⋅ + ⋅ iX g m vGS gmb vBS g m vX gmb vX ro ro 1 = v ⋅ + g + g X m mb ro v 1 1 1 1 R = X = = r = r X 1 o + o iX + + gm gmb gm gmb gm gmb ro • If channel length modulation is ignored (r o=∞) we get: 1 1 1 1 1 R = r = ∞ = = X o + + + gm gmb gm gmb g m g mb gm g mb SM 67 EECE 488 – Set 2: Background Equivalent Transconductance - 1 • Recall that the transconductance of a transistor was a a figure of merit that indicates how well the device converts a voltage to current. ∂I g = D m ∂ = VGS VDS Const . • It is sometimes useful to define the equivalent transconductance of a circuit as follows: ∂I G = OUT m ∂ = VIN VOUT Const . • The following is a small-signal block diagram of an arbitrary circuit with a Norton equivalent at the output port. We notice that: VOUT =Constant so vOUT =0 in the small signal model. i G = OUT m = vIN vOUT 0 SM 68 EECE 488 – Set 2: Background SM 34 Equivalent Transconductance - 2 Example: • Find the equivalent transconductance of an NMOS transistor in saturation from its small-signal model. = ⋅ = ⋅ iOUT gm vGS gm vIN i = OUT = Gm gm vIN SM 69 EECE 488 – Set 2: Background Equivalent Transconductance - 3 Example: • Find the equivalent transconductance of the following circuit when the NMOS transistor in saturation. = + = + ⋅ vIN vGS vS vGS iOUT RS v i ⋅ R = ⋅ + ⋅ − S = ⋅ − ⋅ + ⋅ ()− ⋅ − OUT S iOUT gm vGS gmb vBS gm (vIN iOUT RS ) gmb iOUT RS rO rO R i ⋅1+ g ⋅ R + g ⋅ R + S = g ⋅ v OUT m S mb S m IN rO i g g ⋅ r G = OUT = m = m O m R + ⋅()⋅ + ⋅ + vIN + ⋅ + ⋅ + S rO rO g m RS gmb RS RS 1 gm RS g mb RS rO SM 70 EECE 488 – Set 2: Background SM 35 Short-Channel Effects • Threshold Reduction – Drain-induced barrier lowering (DIBL) • Mobility degradation • Velocity saturation • Hot carrier effects – Substrate current – Gate current • Output impedance variation SM 71 EECE 488 – Set 2: Background Threshold Voltage Variation in Short Channel Devices • The Threshold of transistors fabricated on the same chip decreases as the channel length decreases. • Intuitively, the extent of depletion regions associated with drain and source in the channel area, reduces the immobile charge that must be imaged by the charge on the gate. SM 72 EECE 488 – Set 2: Background SM 36 Drain-Induced Barrier Lowering (DIBL) When the channel is short, the drain voltage increases the channel surface potential, lowering the barrier to flow charge from source (think of increased electric field) and therefore, decreasing the threshold. SM 73 EECE 488 – Set 2: Background Effects of Velocity Saturation • Due to drop in mobility at high electric fields • (a) Premature drain current saturation and (b) reduction in gm SM 74 EECE 488 – Set 2: Background SM 37 Hot Carrier Effects • Short channel devices may experience high lateral drain-source electric field • Some carriers that make it to drain have high velocity (called “hot” carriers) • “Hot” carriers may “hit” silicon atoms at high speed and cause impact ionization • The resulting electron and holes are absorbed by the drain and substrate causing extra drain-substrate current • Really “hot” carriers may be injected into gate oxide and flow out of gate causing gate current! SM 75 EECE 488 – Set 2: Background Output Impedance Variation Recall the definition of λ . SM 76 EECE 488 – Set 2: Background SM 38 Output Impedance Variation in Short-Channel Devices SM 77 EECE 488 – Set 2: Background SM 39