High Performance 22/20nm FinFET CMOS Devices with Advanced High-K/Metal Gate Scheme

C.C. Wu, D.W. Lin, A. Keshavarzi, C.H. Huang, C.T. Chan, C.H. Tseng, C.L. Chen, C.Y. Hsieh, K.Y. Wong, M.L. Cheng, T.H. Li, Y.C. Lin, L.Y. Yang, C.P. Lin, C.S. Hou, H.C. Lin, J.L. Yang, K.F. Yu, M.J. Chen, T.H. Hsieh, Y.C. Peng, C.H. Chou, C.J. Lee, C.W. Huang, C.Y. Lu, F.K. Yang, H.K. Chen, L.W. Weng, P.C. Yen, S.H. Wang, S.W. Chang, S.W. Chuang, T.C. Gan, T.L. Wu, T.Y. Lee, W.S. Huang, Y.J. Huang, Y. W. Tseng, C.M. Wu, Eric Ou-Yang, K.Y. Hsu, L.T. Lin, S.B. Wang, T.M. Kwok, C.C. Su, C.H. Tsai, M.J. Huang, H.M. Lin, A.S. Chang, S.H. Liao, L.S. Chen, J.H. Chen, P.S. Lim, X.F. YU, S.Y. Ku, Y.B. Lee, P.C. Hsieh, P.W. Wang, Y.H. Chiu, S.S. Lin, H.J. Tao, M. Cao, Y.J. Mii

Research & Development, Taiwan Semiconductor Manufacturing Company No. 8, Li-Hsin Rd. 6, Hsinchu Science Park, Hsinchu, Taiwan, R.O.C., Tel: +886-3-5636688, Email: [email protected]

Abstract gate approach, it is difficult to achieve low long-channel A high performance 22/20nm CMOS bulk FinFET device Vth for both NFET and PFET simultaneously. achieves the best in-class N/P Ion values of 1200/1100 Therefore, the capability of separately modulating the μA/μm for Ioff=100nA/μm at 1V. Excellent device metal gate WF of NFET and PFET by the dual-WF electrostatic control is demonstrated for gate length (Lgate) approach is critical in achieving variation-tolerant Vth down to 20nm. Dual-Epitaxy and multiple stressors are roll-off characteristics. However, this important subject essential to boost the device performance. Dual has rarely been discussed for FinFET with Lgate down to workfunction (WF) with an advanced High-K/Metal gate 20nm. In this work, we introduce a dual-WF HK/MG (HK/MG) stack is deployed in an integration-friendly stack in an integrated CMOS process and have compared CMOS process flow. This dual-WF approach provides it with the single-WF approach. Furthermore, we have excellent Vth roll-off immunity in the short-channel evaluated and compared the BTI reliability of this regime that allows properly positioning the long-channel advanced dual-WF HK/MG stack to a planar 32nm device Vth. Enhanced 193nm immersion lithography has HK/MG technology [7] enabled the stringent requirements of the 22/20nm ground The major objectives of this work are (1) to demonstrate rules. Reliability of our advanced HK/MG stack is the highly competitive CMOS integrated process for promising. Excellent SRAM static noise margin at 0.45V FinFETs on the 22/20nm ground rules, and (2) to provide is reported. competitive and comparable NFET/PFET driving currents by carefully deploying process modules and the Introduction techniques for effective strain engineering, parasitic As the requirement of channel length scaling enters source/drain series-resistance (Rsd) reduction, and the sub-30nm regime, the improved electrostatic control of dual-WF approach. In this paper, we show comparable multi-gate device architectures make them attractive for NFET/PFET strengths (n/p ratio ~1) that allows continued transistor channel length scaling in advanced flexibility in FinFET circuit design architecture and technology nodes. Among the multi-gate architectures, competitive circuit layout with equal device widths. FinFET is the most promising one for its self-aligned multi-gate structure and its relatively better compatibility Process to the conventional planar CMOS process [1]. However, This paper reports a high performance bulk FinFET integrating FinFETs into CMOS process flow in the tight architecture using 22/20nm ground rules on wafers with pitch technologies with constrained design rules is (100) substrate. Advanced 193nm immersion lithography demanding. Managing parasitic resistance while and optimized etching processes were utilized for fin maintaining performance is critical for FinFET [2-6]. formation, gate patterning and trench contact formation in Proper insertion of multiple stressors on a varying the front-end integration. The TEM cross-section in Fig. 1 topography is extremely challenging to deploy on the indicates a vertical fin sidewall in the area of device 22/20nm ground rules and beyond. interest and the definition of effective device width (Weff The influence of long-channel device Vth setting on the = 2 x Fin Height + Fin Width) in this work. A vertical short-channel device Vth roll-off characteristics is well gate profile from fin-top to fin-bottom at 90nm gate-pitch known in device physics particularly when a definite was achieved (Fig. 2). Good patterning capability is 2 short-channel device Vth is required. For a desired shown in Fig. 3 for a high performance 0.1μm SRAM bit short-channel device Vth target, a lower long-channel cell. device Vth achieves a smaller Vth roll-off slope in the Proper insertion of stressor films and reduction of short-channel regime and in turn improves process parasitic Rsd are critical for high performance FinFET. window by suppressing the device performance variation Epitaxial silicon and in-situ boron-doped epitaxial resulting from Lgate variation. By using a single-WF metal silicon-germanium (e-SiGe) were utilized to enlarge the

978-1-4244-7419-6/10/$26.00 ©2010 IEEE 27.1.1 IEDM10-600 current conduction cross-section outside the channel depicted in Fig. 15. This reduced FinFET gated-diode Iboff region for NFET and PFET while e-SiGe additionally could be partly attributed to a significantly reduced imposed compressive strain on the PFET channel region channel doping concentration that is required to sustain for the purpose of improving hole carrier mobility. the short-channel device Vth. As a result, FinFET is Conventional Stress-Memorization-Technique (SMT) [8] especially suitable for the low-standby-power and was implemented on NFET for electron mobility low-leakage operation. enhancement. Combining SMT with an optimized N+ S/D ion-implantation, NFET Ion was enhanced by 8% at a Reliability constant Ioff as depicted in Fig. 4. Both mobility Fig. 16 (a) & (b) exhibit the FinFET PBTI and NBTI enhancement (reduced slope) and Rsd reduction (reduced performance of our HK/MG stack compared to a planar intercept value on the R_total axis) are shown by 32nm HK/MG technology [7]. Our FinFET structure with analyzing R_total vs. Lgate curves in Fig. 5. After the top and sidewall planes shows similar PBTI/NBTI conventional nickel-silicide formation, an optimized performance compared to the 32nm planar technology contact-etch-stop-layer (CESL) was used to provide implying that excellent sidewall interface and HK quality ~10% improvement in PFET Ion-Ioff performance as is achieved in our optimized FinFET process. Therefore, shown in Fig. 6. our FinFET platform maintains good reliability margin as Our advanced HK/MG process properly adjusted the well as high device performance while reducing the PFET’s WF in order to achieve a low long-channel device process complexity and cost. Vth and excellent Vth roll-off slope in the short channel regime that will be discussed more in the next section. SRAM More than 25% PFET Ion-Ioff improvement is achieved by FinFET width quantization requires extra efforts for the combined implementation of the optimized CESL and the SRAM design to be optimized for the read and write gate-last HK/MG stack [9]-[10] as shown in Fig.7. Fig. 8 performance by carefully adjusting Vth of SRAM shows the TEM cross-section of the final gate stack. transistors. Butterfly curves of the high performance SRAM cell are shown in Fig. 17 at 0.85V, 0.65V and Device 0.45V respectively. FinFET’s improved Vth variation and Long-channel device Vth setting is critical to the Vth short-channel electrostatic control allow for low operation roll-off characteristics in the short-channel regime. Fig. 9 voltage. Excellent SRAM static noise margin of 90mV is explains that a higher long-channel device Vth (using observed even down to 0.45V Vdd. PFET in the single-WF gate stack as an example) leads to steeper Vth roll-off in the short-channel regime and in turn Conclusions degrades the process window when the goal is to achieve We have successfully demonstrated a high performance a low short-channel device Vth. Our dual-WF approach and low-leakage FinFET technology on 22/20 nm ground has successfully lowered the Vth of the long-channel rules. Good electrostatic control down to 20nm Lgate was devices to <0.3V for both NFET and PFET (Fig. 10). This exhibited. By integrating the advanced dual-WF HK/MG feature enables improved variation-tolerant Vth roll-off stack in FinFET structure, low long-channel device V characteristics allowing stable short-channel device th and excellent Vth roll-off slope in the short-channel operation with Lgate down to 20nm for high performance regime are achieved for both NFET and PFET. The device requirements. advantage of dual-WF scheme over single WF scheme is Figs. 11-12 show our Id-Vg and Id-Vd characteristics. therefore evident. Strain engineering and parasitic Rsd NFET and PFET DIBL of 100mV/V and 120mV/V are reduction endeavors produced highly competitive and reported for devices with 25nm Lgate. Sub-threshold swing balanced N/PFET Ion-Ioff performance. measures 80mV/decade. Fig. 13 demonstrates N/PFET Ion-Ioff curves achieving Ion values of 1200/1100 μA/μm at 100nA/μm I for V =1V. All currents are normalized to Reference off dd [1] N. Lindert, et al.,” IEEE EDL., vol. 22, p.487, 2001. W as described earlier in Fig. 1. Key contribution of eff [2] D. Hisamoto, et al., IEDM, p.1032, 1998. this work is demonstrating state-of-the-art N/PFET [3] Y.-K. Choi, et al, IEDM, p.421, 2001 devices that meet or exceed the best reported FinFET [4] J. Kavalieros, et al., VLSI Tech. Symp., p.50, 2006. devices in the industry under stringent design rules. Fig. [5] C. Y. Chang, et al., IEDM, p.293, 2009 14 compares and shows the fact that this work provides [6] C. E. Smith, et al., IEDM, p.309, 2009 the up-to-date overall best NFET and PFET Ion-Lgate [7] C. H. Diaz, et al., IEDM, p.629, 2008 performance. [8] C. H. Chen, et al., VLSI Tech. Symp., p. 56, 2004. In contrast with the planar device sharing the same [9] C. Auth, et al., VLSI Tech. Symp., p.128, 2008 process platform, FinFET shows excellent capability of [10] S. Yamakawa, et al., Proc. SISPAD, p.109, 2008. [11] V. S. Basker, et al., VLSI Tech. Symp., p.19, 2010. suppressing the off-state drain-to-bulk junction leakage current (Iboff) at a given sub-threshold leakage current as

IEDM10-601 27.1.2 Fin_W

Fin_H Fin top 100 nm

Fin bottom

Weff = 2 x Fin_H + Fin_W Figure 1. TEM Cross-section showing Figure 2. Cross-sectional TEM showing a Figure 3. Top view image of the high vertical fin sidewall in the area of interest. vertical gate profile from fin-top to performance 0.1μm2 SRAM bit cell fin-bottom. showing good pattern fidelity.

1000

100 300 w/o SMT w/o SMT -um)

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SMT + ( R_total optimized S/D-IMP 180 optimized S/D-IMP 0.1 0.7 0.8 0.9 1.0 1.1 1.2 1.3 0 102030405060 Normalized Idsat Gate Length (nm)

Figure 4. Stress-memorization-technique + optimized Figure 5. SMT stress + optimized N+ S/D ion-implantation + N S/D ion-implantation provides 8% Ion-Ioff gain for the demonstrates mobility enhancement (lower slope) and Rsd NFET. reduction (lower intercept) for the NFET.

1000 1000

100 Control 100 Control 10% >25% 10 10

Metal gate Optimized CESL

Ioff (nA/um) Ioff 1 Ioff (nA/um) Ioff 1 Optimized CESL + High-K advanced HK/MG

0.1 0.1 0.7 0.8 0.9 1.0 1.1 1.2 1.3 0.6 0.8 1.0 1.2 1.4 1.6 Si substrate Normalized Ion (a.u.) Normalized Ion (a.u.)

Figure 6. Optimized CESL leads to 10% Figure 7. Optimized CESL + Advanced Figure 8. Cross-sectional TEM of the better PFET Ion-Ioff over the control HK/MG improves PFET Ion-Ioff by > 25%. advanced HK/MG scheme. sample. Our Advanced HK/MG provides not only correct WF setting, but also improved strain efficiency.

27.1.3 IEDM10-602

-0.5 0.4 single WF V 0.3 th_lin NFET -0.4 0.2 Vth_sat -0.3 0.1

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th (V) th -0.2 V -0.1 V dual WF -0.2 -0.1 empty : Vth_ lin @ Vd=-0.05V -0.3 PFET solid : V @ Vd=-1V 0.0 th_s at -0.4 20 30 40 50 60 70 80 90 100 20 100 Gate Length (nm) Gate Length (nm)

Figure 9. Higher long-channel Vth leads to steeper Vth Figure 10. Vth vs. Lgate characteristics for both NFET and roll-off slope in the short-channel regime. By PFET using the advanced HK/MG scheme in this work. independently optimizing WF for PFET in the dual WF Long-channel Vth achieves <0.3V. case, improved Vth roll-off slope is achieved.

10-2 1200 -3 PFET NFET Vd = 1V 10 Vg=1.0V m) m) 1000 μ -4 μ 10 Vg=0.9V A/

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PFET NFET Drain Current ( 10-9 0 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 -1.0 -0.5 0.0 0.5 1.0 Gate Voltage (V) Drain Voltage (V)

Figure 11. Id-Vg curves for 25nm Lgate NFET and PFET. Figure 12. Id-Vd curves for 25nm Lgate NFET and PFET

103 1300 1200 100 m)

μ NFET PFET PFET NFET 1250 1100 Planar device 2 This work (A.U.) 10 -1 1200 1000 boff 10 m) μ

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Ion ( 10 1000 600 -1 0 1 2 -1400-1200-1000 -800 -600 600 800 1000 1200 1400 25 30 35 40 25 30 35 40 Junction Leakage,I 10 10 10 10 Gate Length (nm) Gate Length (nm) Subthreshold Leakage, I (A.U.) Ion (μA/μm) soff

Figure 13. Ion-Ioff curves show Ion = 1200 Figure 14. Performance benchmark of Figure 15. N-FinFETs junction leakage μA/μm for NFET and 1100 μA/μm for Ion-Lgate at Ioff = 100nA/μm for the previous decreases by 100 times at the same Isoff PFET at Ioff = 100nA/μm at Vdd=1V. FinFET works. leakage compared to the planar NFETs

using similar process conditions. 0.9 0.85V 100 100 a 1stplanar generation 28nm32nm HK/MG HK/MG technology [7] 0.8 HK/MG HK/MG in thisin thiswork work 0.7 0.65V 0.6 0.5 0.45V 10 10 (V)

N2 0.4 V

Shift (mV) Shift 0.3 th

V 0.2 (a) PBTI (b) NBTI 0.1 1 1 6789101112131467891011121314 0.0 Equivalent E-field (MV/cm) Equivalent E-field (MV/cm) 0.00.10.20.30.40.50.60.70.80.9 VN1 (V) Figure 16. Advanced HK/MG scheme used in this work Figure 17. SRAM butterfly curves measured at Vdd=0.85V, shows similar PBTI and NBTI performance to a planar 0.65V and 0.45V. Excellent static noise margin of 90mV is 32nm HK/MG technology [7]. observed at Vdd=0.45V.

IEDM10-603 27.1.4