5Oth SISC ‐ “RUMP Session”
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Room Temperature Ultrahigh Electron Mobility and Giant Magnetoresistance in an Electron-Hole-Compensated Semimetal Luptbi
High Electron Mobility and Large Magnetoresistance in the Half-Heusler Semimetal LuPtBi Zhipeng Hou1,2, Wenhong Wang1,*, Guizhou Xu1, Xiaoming Zhang1, Zhiyang Wei1, Shipeng Shen1, Enke Liu1, Yuan Yao1, Yisheng Chai1, Young Sun1, Xuekui Xi1, Wenquan Wang2, Zhongyuan Liu3, Guangheng Wu1 and Xi-xiang Zhang4 1State Key Laboratory for Magnetism, Beijing National Laboratory for Condensed Matter Physics, Institute of Physics, Chinese Academy of Sciences, Beijing 100190, China 2College of Physics, Jilin University, Changchun 130023, China 3State Key Laboratory of Metastable Material Sciences and Technology, Yanshan University, Qinhuangdao 066004, China 4Physical Science and Engineering, King Abdullah University of Science and Technology (KAUST), Thuwal 23955-6900, Saudi Arabia. Abstract Materials with high carrier mobility showing large magnetoresistance (MR) have recently received much attention because of potential applications in future high-performance magneto-electric devices. Here, we report on the discovery of an electron-hole-compensated half-Heusler semimetal LuPtBi that exhibits an extremely high electron mobility of up to 79000 cm2/Vs with a non-saturating positive MR as large as 3200% at 2 K. Remarkably, the mobility at 300 K is found to exceed 10500 cm2/Vs, which is among the highest values reported in three-dimensional bulk materials thus far. The clean Shubnikov-de Haas quantum oscillation observed at low temperatures and the first-principles calculations together indicate that the high electron mobility is due to a rather small effective carrier mass caused by the distinctive band structure of the crystal. Our finding provide a new approach for finding large, high-mobility MR materials by designing an appropriate Fermi surface topology starting from simple electron-hole-compensated semimetals. -
Imperial College London Department of Physics Graphene Field Effect
Imperial College London Department of Physics Graphene Field Effect Transistors arXiv:2010.10382v2 [cond-mat.mes-hall] 20 Jul 2021 By Mohamed Warda and Khodr Badih 20 July 2021 Abstract The past decade has seen rapid growth in the research area of graphene and its application to novel electronics. With Moore's law beginning to plateau, the need for post-silicon technology in industry is becoming more apparent. Moreover, exist- ing technologies are insufficient for implementing terahertz detectors and receivers, which are required for a number of applications including medical imaging and secu- rity scanning. Graphene is considered to be a key potential candidate for replacing silicon in existing CMOS technology as well as realizing field effect transistors for terahertz detection, due to its remarkable electronic properties, with observed elec- tronic mobilities reaching up to 2 × 105 cm2 V−1 s−1 in suspended graphene sam- ples. This report reviews the physics and electronic properties of graphene in the context of graphene transistor implementations. Common techniques used to syn- thesize graphene, such as mechanical exfoliation, chemical vapor deposition, and epitaxial growth are reviewed and compared. One of the challenges associated with realizing graphene transistors is that graphene is semimetallic, with a zero bandgap, which is troublesome in the context of digital electronics applications. Thus, the report also reviews different ways of opening a bandgap in graphene by using bi- layer graphene and graphene nanoribbons. The basic operation of a conventional field effect transistor is explained and key figures of merit used in the literature are extracted. Finally, a review of some examples of state-of-the-art graphene field effect transistors is presented, with particular focus on monolayer graphene, bilayer graphene, and graphene nanoribbons. -
Evaluation of Passivation Process for Stainless Steel Hypotubes Used in Coronary Angioplasty Technique
coatings Article Evaluation of Passivation Process for Stainless Steel Hypotubes Used in Coronary Angioplasty Technique Lucien Reclaru 1,2 and Lavinia Cosmina Ardelean 2,3,* 1 Scientific Independent Consultant Biomaterials and Medical Devices, 103 Paul-Vouga, 2074 Marin-Neuchâtel, Switzerland; [email protected] 2 Multidisciplinary Center for Research, Evaluation, Diagnosis and Therapies in Oral Medicine, “Victor Babes” University of Medicine and Pharmacy Timisoara, 2 Eftimie Murgu sq, 300041 Timisoara, Romania 3 Department of Technology of Materials and Devices in Dental Medicine, “Victor Babes” University of Medicine and Pharmacy Timisoara, 2 Eftimie Murgu sq, 300041 Timisoara, Romania * Correspondence: [email protected] Abstract: In the manufacturing of hypotubes for coronary applications, austenitic steels of types 304, 304, or 316 L are being used. The manufacturing process involves bending steel strips into tubes and the continuous longitudinal welding of the tubes. Manufacturing also includes heat treatments and stretching operations to achieve an external/internal diameter of 0.35/0.23 mm, with a tolerance of +/− 0.01 mm. Austenitic steels are sensitive to localized corrosion (pitting, crevice, and intergranular) that results from the welding process and various heat treatments. An extremely important step is the cleaning and the internal and external passivation of the hypotube surface. During patient interventions, there is a high risk of metal cations being released in contact with human blood. The aim of this study was to evaluate the state of passivation and corrosion resistance by using electrochemical methods and specific intergranular corrosion tests (the Strauss test). There were difficulties in passivating the hypotubes and assessing the corrosion phenomena in the interior of the tubes. -
Si Passivation and Chemical Vapor Deposition of Silicon Nitride: Final Technical Report, March 18, 2007
A national laboratory of the U.S. Department of Energy Office of Energy Efficiency & Renewable Energy National Renewable Energy Laboratory Innovation for Our Energy Future Si Passivation and Chemical Subcontract Report NREL/SR-520-42325 Vapor Deposition of Silicon Nitride November 2007 Final Technical Report March 18, 2007 H.A. Atwater California Institute of Technology Pasadena, California NREL is operated by Midwest Research Institute ● Battelle Contract No. DE-AC36-99-GO10337 Si Passivation and Chemical Subcontract Report NREL/SR-520-42325 Vapor Deposition of Silicon Nitride November 2007 Final Technical Report March 18, 2007 H.A. Atwater California Institute of Technology Pasadena, California NREL Technical Monitor: R. Matson/F. Posey-Eddy Prepared under Subcontract No. AAT-2-31605-01 National Renewable Energy Laboratory 1617 Cole Boulevard, Golden, Colorado 80401-3393 303-275-3000 • www.nrel.gov Operated for the U.S. Department of Energy Office of Energy Efficiency and Renewable Energy by Midwest Research Institute • Battelle Contract No. DE-AC36-99-GO10337 This publication was reproduced from the best available copy Submitted by the subcontractor and received no editorial review at NREL NOTICE This report was prepared as an account of work sponsored by an agency of the United States government. Neither the United States government nor any agency thereof, nor any of their employees, makes any warranty, express or implied, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any information, apparatus, product, or process disclosed, or represents that its use would not infringe privately owned rights. Reference herein to any specific commercial product, process, or service by trade name, trademark, manufacturer, or otherwise does not necessarily constitute or imply its endorsement, recommendation, or favoring by the United States government or any agency thereof. -
Graphene Field-Effect Transistor Array with Integrated Electrolytic Gates Scaled to 200 Mm
Graphene field-effect transistor array with integrated electrolytic gates scaled to 200 mm N C S Vieira1,3, J Borme1, G Machado Jr.1, F Cerqueira2, P P Freitas1, V Zucolotto3, N M R Peres2 and P Alpuim1,2 1INL - International Iberian Nanotechnology Laboratory, 4715-330, Braga, Portugal. 2CFUM - Center of Physics of the University of Minho, 4710-057, Braga, Portugal. 3IFSC - São Carlos Institute of Physics, University of São Paulo, 13560-970, São Carlos-SP, Brazil E-mail: [email protected] Abstract Ten years have passed since the beginning of graphene research. In this period we have witnessed breakthroughs both in fundamental and applied research. However, the development of graphene devices for mass production has not yet reached the same level of progress. The architecture of graphene field-effect transistors (FET) has not significantly changed, and the integration of devices at the wafer scale has generally not been sought. Currently, whenever an electrolyte-gated FET (EGFET) is used, an external, cumbersome, out-of-plane gate electrode is required. Here, an alternative architecture for graphene EGFET is presented. In this architecture, source, drain, and gate are in the same plane, eliminating the need for an external gate electrode and the use of an additional reservoir to confine the electrolyte inside the transistor active zone. This planar structure with an integrated gate allows for wafer-scale fabrication of high-performance graphene EGFETs, with carrier mobility up to 1800 cm2 V-1 s-1. As a proof-of principle, a chemical sensor was achieved. It is shown that the sensor can discriminate between saline solutions of different concentrations. -
3 Carbon Nanotubes – the Dispersion
DEPARTMENT OF PHYSICS UNIVERSITY OF JYVÄSKYLÄ RESEARCH REPORT No. 11/2018 DEVELOPMENT OF MICROFLUIDICS FOR SORTING OF CARBON NANOTUBES BY JÁN BOROVSKÝ Academic Dissertation for the Degree of Doctor of Philosophy To be presented, by permission of the Faculty of Mathematics and Science of the University of Jyväskylä, for public examination in Auditorium FYS1 of the University of Jyväskylä on December 13th, 2018 at 12 o’clock noon Jyväskylä, Finland December 2018 Preface The work reviewed in this thesis has been carried out during the years 2012 & 2014-2018 at the Department of Physics and Nanoscience Center in the University of Jyväskylä. First and foremost, I would like to thank my supervisor Doc. Andreas Jo- hansson for his guidance during my Erasmus internship and consequent Ph.D. studies. I am very grateful for his willingness to share both the professional com- petence and personal wisdom. Equal gratitude belongs to Prof. Mika Pettersson, without whom this project would never exist. His ability to see the big picture, his interesting insights, and genuine joy from the beauty of the microworld were a true motivation for me. It has been a great experience to work in the Nanoscience Center for all these years. I would like to express my gratitude to the whole staff for being supportive, sharing good ideas, or just having fun meaningful conversations. A special thanks goes to Prof. Janne Ihalainen for providing me access to the facilities of the Department of Biology. I humbly acknowledge the irreplaceable help of our technical staff, namely Dr. Kimmo Kinnunen, Mr. Tarmo Suppula, Dr. -
Analysis of the Silicon Dioxide Passivation and Forming Gas
&RQIHUHQFH3URFHHGLQJV 6RODU:RUOG&RQJUHVV Daegu, Korea, 08 – 12 November 2015 Analysis of the Silicon Dioxide Passivation and Forming Gas Annealing in Silicon Solar Cells Izete Zanesco and Adriano Moehlecke Solar Energy Technology Nucleus (NT-Solar), Faculty of Physics, Pontifical Catholic University of Rio Grande do Sul (PUCRS), Porto Alegre (Brazil) Abstract The passivation of silicon solar cells by the deposition of SiNx anti-reflection coating is usual in the industry. However, materials such as SiO2, TiO2 and Al2O3 may be a cost-effective alternative and its analysis is mainly reported in silicon wafers. The goal of this paper is to present the development and analysis of silicon solar cells passivated with a thin layer of SiO2 as well as the evaluation of the effectiveness of the annealing step in forming gas. The dry oxidation was performed before the TiO2 anti-reflection coating deposition and the annealing in forming gas was performed in the same furnace. The temperature and time of the oxidation and the annealing step were experimentally optimized. The efficiency of 15.9 %was achieved. The highest average efficiency was found in the oxidation temperature range from 750 ºC to 800 ºC, during 7 minutes, caused by the increasing of open circuit voltage and fill factor. At short wavelengths, the internal quantum efficiency decreases slightly with the increasing of the oxidation temperature. The minority carrier diffusion length (LD) of the solar cells processed with the oxidation temperature of 800 °C was around 1890 Pm. The open circuit voltage shows a slight trend of increasing with the oxidation time. The annealing step in forming gas did not improve the average efficiency of the solar cells. -
Design and Analysis of Double Gate MOSFET Devices Using High-K Dielectric
International Journal of Electrical Engineering. ISSN 0974-2158 Volume 7, Number 1 (2014), pp. 53-60 © International Research Publication House http://www.irphouse.com Design and Analysis of Double Gate MOSFET Devices using High-k Dielectric Asha Balhara* and Divya Punia Department of E.C.E., B.P.S. Women University, khanpur kalan, Sonepat, India. *E-mail id: [email protected] Abstract Double gate MOSFET is one of the most promising and leading contender for Nano regime devices. In this paper an n-channel symmetric Double-Gate MOSFET using high-k (TiO2) dielectric with 80nm gate length is designed and simulated to study its electrical characteristics. ATHENA and ATLAS simulation tools from SILVACO are used in simulating electrical performance and analyzing the effectiveness of double gate MOSFET. High-k gate technology is emerging as a strong alternative for replacing the conventional SiO2 dielectrics gates in scaled MOSFETs for both high performance and low power applications. High-k oxides offer a solution to leakage problems that occur as gate oxide thickness’ are scaled down. Non-ideal effect of a MOSFET design such as short channel effects are investigated. The most common effect that generally occurs in the short channel MOSFETs are channel modulation, drain induced barrier lowering (DIBL). It is observed in the results that the device engineering would play an important role in optimizing the device parameters. Keywords- MOSFET-metal oxide semiconductor field effect transistor; DG- MOSFET-double-gate MOSFET; SG-MOSFET-single -
H2O2 Hydrogen Peroxide Passivation Procedure
Solvaytechnical Chemicals PUBLICATION H2O2 Passivation Procedure Introduction Hydrogen peroxide is a strong chemical oxidant which decomposes into water and oxygen in the presence of a catalytic quantity of any transition metal (e.g., iron, copper, nickel, etc.). The primary concern with decomposition is the buildup of pressure which can lead to pressure Prepare for passivation by roping off the work area bursts. To prevent this from occurring, any metal surface that comes in and posting warning signs. All open lights and tools contact with hydrogen peroxide must be degreased, pickled and which may spark must be removed from the passivated, even if only used once. The degreasing and pickling steps passivation area. Smoking is prohibited within the chemically clean the metal surfaces. The passivating step oxidizes the passivation area. Prior to preparation of the chemical metal surface. The thin oxide coating, which forms on the metal surface solutions, determine how to dispose of the spent during passivation, renders the surface nonreactive to hydrogen peroxide chemicals. These chemicals must be disposed of in and prevents the metal from decomposing the peroxide. a safe and environmentally sound manner that is consistent with all applicable federal, state, and The passivation procedure consists of: local regulations. 1. Grinding to remove weld spatter and smooth out scratches. 2. Degreasing to remove oil and grease films. Application methods 3. Pickling to chemically clean the surface. The chemical solutions may be applied to the metal surfaces by the four different methods listed below. 4. Passivating with nitric acid to form an oxide film. • The metal surfaces may be sprayed with the 5. -
Advanced MOSFET Structures and Processes for Sub-7 Nm CMOS Technologies
Advanced MOSFET Structures and Processes for Sub-7 nm CMOS Technologies By Peng Zheng A dissertation submitted in partial satisfaction of the requirements for the degree of Doctor of Philosophy in Engineering - Electrical Engineering and Computer Sciences in the Graduate Division of the University of California, Berkeley Committee in charge: Professor Tsu-Jae King Liu, Chair Professor Laura Waller Professor Costas J. Spanos Professor Junqiao Wu Spring 2016 © Copyright 2016 Peng Zheng All rights reserved Abstract Advanced MOSFET Structures and Processes for Sub-7 nm CMOS Technologies by Peng Zheng Doctor of Philosophy in Engineering - Electrical Engineering and Computer Sciences University of California, Berkeley Professor Tsu-Jae King Liu, Chair The remarkable proliferation of information and communication technology (ICT) – which has had dramatic economic and social impact in our society – has been enabled by the steady advancement of integrated circuit (IC) technology following Moore’s Law, which states that the number of components (transistors) on an IC “chip” doubles every two years. Increasing the number of transistors on a chip provides for lower manufacturing cost per component and improved system performance. The virtuous cycle of IC technology advancement (higher transistor density lower cost / better performance semiconductor market growth technology advancement higher transistor density etc.) has been sustained for 50 years. Semiconductor industry experts predict that the pace of increasing transistor density will slow down dramatically in the sub-20 nm (minimum half-pitch) regime. Innovations in transistor design and fabrication processes are needed to address this issue. The FinFET structure has been widely adopted at the 14/16 nm generation of CMOS technology. -
Effect of the Electrochemical Passivation on the Corrosion Behaviour of Austenitic Stainless Steel
Effect of the electrochemical passivation on the corrosion behaviour of austenitic stainless steel A. Barbucci, M.Delucchi, M. Panizza, G, Farné, G. Cerisola DICheP, University of Genova, P.le Kennedy 1, 16129 Genova, Italy tel: +390103536030, e-mail: [email protected] Abstract: Cold rolled SS is also fruitfully used in deep drawing however the presence of scales or oxides on the surface reduces the life of the tools and emphasises creep phenomena of the material. Then a cleaning of the SS surface from these impurities is necessary. Oxides can be formed during the hot rolling preceding the cold one, or during the annealing performed between the several steps of thickness reduction. The annealing helps to decrease the work hardening occurring during the process. Normally this heat treatment is performed in reducing atmosphere of pure hydrogen (bright annealing), but even in this conditions oxides are formed on the SS surface. To avoid this uncontrolled oxide growth one method recently applied is an electrochemical cleaning performed in an electrolytic solution containing chrome, generally called electrochemical passivation. The electrochemical passivation allows the dissolution of the contaminating hard particles on the strips. Few scientific contributions are available in literature, which explain in detail the process mechanism. The aim of this work is to investigate if the electrochemical passivated surface acts in a different way with regard to corrosion phenomena with respect to conventional SS. Electrochemical measurements like polarisations, chronoamperometries and surface analysis were used to investigate the corrosion behaviour of electrochemically passivated AISI 304L and AISI 305. The effect of some process parameters were considered, too. -
Outline MOS Gate Dielectrics Incorporation of N Or F at the Si/Sio
MOS Gate Dielectrics Outline •Scaling issues •Technology •Reliability of SiO2 •Nitrided SiO2 •High k dielectrics araswat tanford University 42 EE311 / Gate Dielectric Incorporation of N or F at the Si/SiO2 Interface Incorporating nitrogen or fluorine instead of hydrogen strengthens the Si/SiO2 interface and increases the gate dielectric lifetime because Si-F and Si-N bonds are stronger than Si-H bonds. Nitroxides – Nitridation of SiO2 by NH3 , N2O, NO Poly-Si Gate – Growth in N2O – Improvement in reliability – Barrier to dopant penetration from poly-Si gate Oxide N or F – Marginal increase in K – Used extensively Si substrate Fluorination – Fluorination of SiO2 by F ion implantation – Improvement in reliability – Increases B penetration from P+ poly-Si gate – Reduces K – Not used intentionally – Can occur during processing (WF6 , BF2) araswat tanford University 43 EE311 / Gate Dielectric 1 Nitridation of SiO2 in NH3 H • Oxidation in O2 to grow SiO2. • RTP anneal in NH3 maximize N at the interface and minimize bulk incorporation. • Reoxidation in O2 remove excess nitrogen from the outer surface • Anneal in Ar remove excess hydrogen from the bulk • Process too complex araswat tanford University 44 EE311 / Gate Dielectric Nitridation in N2O or NO Profile of N in SiO2 Stress-time dependence of gm degradation of a NMOS SiO2 Ref. Bhat et.al IEEE IEDM 1994 (Ref: Ahn, et.al., IEEE Electron Dev. Lett. Feb. 1992) •The problem of H can be circumvented by replacing NH3 by N2O or NO araswat tanford University 45 EE311 / Gate Dielectric 2 Oxidation of Si in N2O N2O → N2 + O N2O + O → 2NO Ref: Okada, et.al., Appl.