Novel Technologies for Next Generation Memory
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Novel Technologies for Next Generation Memory WookHyun Kwon Tsu-Jae King Liu, Ed. Vivek Subramanian, Ed. Electrical Engineering and Computer Sciences University of California at Berkeley Technical Report No. UCB/EECS-2013-136 http://www.eecs.berkeley.edu/Pubs/TechRpts/2013/EECS-2013-136.html July 25, 2013 Copyright © 2013, by the author(s). All rights reserved. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission. Acknowledgement I would like express my sincere gratitude to my advisor, Professor Tsu-Jae King Liu. Prof. King Liu truly inspire me to do better, and I am always looking forward your advices because she always give great feedback. I am deeply grateful to Professor Vivek Subramanian for his enthusiastic class, especially EE231. He has a superior teaching techniques that lead students to have intuitions on the device. I hope he keeps teaching, during whole life. Novel Technologies for Next Generation Memory By Wookhyun Kwon A dissertation submitted in partial satisfaction of the requirements for the degree of Doctor of Philosophy in Engineering - Electrical Engineering and Computer Sciences in the Graduate Division of the University of California, Berkeley Committee in charge: Professor Tsu-Jae King Liu, Chair Professor Vivek Subramanian Professor Junqiao Wu Fall 2013 Novel Technologies for Next Generation Memory Copyright © 2013 by Wookhyun Kwon Abstract Novel Technologies for Next Generation Memory by Wookhyun Kwon Doctor of Philosophy in Engineering – Electrical Engineering and Computer Sciences University of California, Berkeley Professor Tsu-Jae King Liu, Chair Historically, our society requires computational memory media to support the development of our civilization. It is likely that our society will keep demanding larger capacity memory. However, conventional memory technologies are facing many challenges such as difficulties of miniaturization and guarantee of good reliability. For this reason, alternate memory device designs are proposed to overcome the conventional memory device technologies. For DRAM technology, a double-gate array having vertical channel structure (DGVC) with 4F2 cell size is proposed, which can be fabricated on a bulk silicon wafer using the conventional memory process flow for stand-alone DRAM application. The operation and scalability of the DGVC cell are demonstrated via TCAD device simulations. For Flash Memory technology, a new backside charge storage non-volatile memory (BCS-NVM) cell design is proposed. A NAND flash array of the BCS-NVM cells can be fabricated on a modified SOI substrate. TCAD device simulation show that this design allows for a relatively high cell read current and steep sub-threshold slope to enable lower voltage operation in comparison with conventional NAND flash memory devices. As a new concept of non-volatile memory technology, a nano-electro-mechanical (NEM) diode non-volatile memory cell design is proposed. This design eliminates the need of a selector device to form a cross-point array, by leveraging the gap closing actuator. The electro-mechanical diode cell design can be scaled to 20 nm minimum lateral dimension by following an appropriate scaling methodology in consideration of various practical and fundamental limits. Low-voltage (< 2 V) and high-speed (sub-nanosecond) operation are projected using a calibrated analytical model as well as 3-D FEM simulation. These findings indicate that electro-mechanical diode technology is promising for high density storage beyond the limits of conventional flash memory technology. 1 To my wife for her devoted love and support, to my daughters for their sincere smile, and to my parents for their unbounded love. i Contents Table of Contents ii List of Figures vi List of Tables x Acknowledgements xi Table of Contents Chapter 1: Introduction ………………………......………..……………1 1.1 Overview of Computer Memory Technologies …..……….………………………...1 1.2 Dynamic Random Access Memory (DRAM) ..………………...……………….…2 1.2.1 Conventional DRAM and Limitations .…………………………….2 1.2.2 Capacitor-less DRAM Technology …………..………….………….4 1.2.3 Doubly-Gated Capacitor-less DRAM Technology .....….……..…...6 1.3 Flash Memory .…………………………………………………………………..8 1.3.1 History of Flash Memory Technology ………………..…………..8 1.3.2 Limitations of conventional Flash memory technology ……..…..11 ii 1.4 Emerging Memory Technology ……………….……………………………..…13 1.4.1 Cross-point Memory ………………………..………..…………..13 1.4.2 Mechanical Switch Memory …………………………..……..…..14 1.5 Research Objectives and Thesis Overview ……….……………………………..…17 1.6 References …………………………………………………….………………...18 Chapter 2: Highly Scalable Capacitor-less DRAM Cell having a Doubly Gated Vertical Channel ……………….....19 2.1 Introduction ………………………………..……………………………………19 2.2 Device Architecture and Proposed Fabrication …..……………………………......20 2.3 Cell Operation ………………………………...……………………………......23 2.4 Disturbances in the Cell Array ……………………………………....................26 2.5 Scalability of DGVC …………………………………………………....................27 2.6 Summary ………………………………………………..……………....................29 2.7 References ……………………………………………………………....................29 iii Chapter 3: A New NAND Flash Memory Cell Design Utilizing a Back Gate Structure …………………..……...31 3.1 Introduction ………………………………..……………………………………31 3.2 Device Structure .………………….……………………………………………......33 3.3 Proposed Fabrication Process .….…………………….………………................34 3.3.1 Silicon-On-ONO-Substrate (SOONOS) Formation .………………………...34 3.3.2 Memory Device Fabrication …………….……………………………….36 3.4 Device Simulation of the BCS-NVM Cell …………….........................................37 3.4.1 Basic Cell Operation ...............................................………………………...38 3.4.2 Disturbance Immunities...........................................………………………...40 3.5 Summary ..….……………………………………………...................................41 3.6 References ….……………………………………………...................................42 Chapter 4: Electro-Mechanical Diode Non-Volatile Memory Cell …….…………………...……………..……...43 4.1 Introduction ………………………………..……………………………………43 4.2 Device Structure ……………………………………………...….……………...44 4.3 Fabrication Process for Proto-type Cell ……………………..………………….....48 4.4 Electrical Measurement of the Proto-type Cell …...………………………………..51 iv 4.5 Suppression of Sneak Leakage Currents in the Cell Array .……………………..55 4.6 Reliability …….………………………………………………………………....56 4.7 Modeling and Analysis of Electrical Behavior …………………………………..58 4.7.1 Set Operation ............................................……............…………………...58 4.7.2 Reset Operation ……...........................................………………………...60 4.8 Scaling Theory of Electro-Mechanical Diode Cell ..................................................62 4.9 Exemplary Design for 20nm Electro-Mechanical Diode Cell .................................65 4.11 3-Dimensional Integration .....................................................................................66 4.12 Summary ...............................................................................................................67 4.13 References ..............................................................................................................67 Chapter 5: Conclusion ……………………………………….…………69 5.1 Summary …………………..………………………………..…………………….69 5.2 Contribution of This Work …………………………………………………………70 5.3 Suggested Future Work …………………………………………..……………….71 v List of Figures 1.1 Technology trend of conventional DRAM 2 1.2a Comparison between a conventional 8F2 and new 6F2 layout design 3 1.2b Example of 6F2 layout schematic 3 1.3 Recessed-Channel-Access-Transistor (RCAT) structures in DRAM technology 4 1.10a Common-Source NOR-type array architecture 9 1.4 Schematic cross-sectional view of a capacitor-less DRAM 5 1.5 TEM image of a fabricated capacitor-less DRAM cell 5 1.6 Schematic cross-sectional view of a capacitor-less DRAM on SOI 6 1.7 Schematic cross-sectional view and TEM image of a typical independently-Controlled- Double-Gate Floating-Body-Cell device 7 1.8 Channel length vs. Allowable body thickness in a doubly gate capacitor-less DRAM cell design 7 1.9 Schematic cross-section of the conventional flash memory cell 8 1.10a Common-Source NOR-type array architecture 9 1.10b NAND-type array architecture 9 1.11 Photo-lithographic resolution trends 10 1.12 NAND Flash memory revenue trend of the past 15 years 10 1.13 Cross-sectional TEM image of 25nm NAND Flash memory cell 11 1.14 The number of electrons stored in the NAND Flash cell’s floating gate 12 1.15 Example of mechanical switch memory in daily life 14 1.16 Illustration of micro-electro-mechanical non-volatile memory cell 14 1.17a TEM image of Nano-mechanical NVM cell using CMOS back-end process 15 1.17b Illustration of the operaion of Nano-mechanical NVM cell 15 1.18a Schematic cross-section of NEMory cell 16 1.18b Fundamental theory of NEMory operation 16 2.1a Schematic cross-sectional view of DGVC cells 21 2.1b Schematic plan view of DGVC array 21 2.2 Circuit schematic of a DGVC cell array 21 2.3 Key process steps for DGVC array 22 2.4 Simulated retention characteristics of a DGVC cell 25 2.5 Simulated non-destructive readout characteristic of a DGVC cell 25 2.6a Write “0” disturbance on the unselected