Recent Advances of Field-Effect Transistor Technology for Infectious Diseases
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Ion-Sensitive Field Effect Transistor (ISFET) for MEMS Multisensory Chips at RIT Murat Baylav
Rochester Institute of Technology RIT Scholar Works Theses Thesis/Dissertation Collections 2010 Ion-sensitive field effect transistor (ISFET) for MEMS multisensory chips at RIT Murat Baylav Follow this and additional works at: http://scholarworks.rit.edu/theses Recommended Citation Baylav, Murat, "Ion-sensitive field effect transistor (ISFET) for MEMS multisensory chips at RIT" (2010). Thesis. Rochester Institute of Technology. Accessed from This Thesis is brought to you for free and open access by the Thesis/Dissertation Collections at RIT Scholar Works. It has been accepted for inclusion in Theses by an authorized administrator of RIT Scholar Works. For more information, please contact [email protected]. Title Page Ion-Sensitive Field Effect Transistor (ISFET) for MEMS Multisensory Chips at RIT By Murat Baylav A Thesis Submitted In Partial Fulfillment of the Requirements of the Degree of Master of Science in Microelectronic Engineering Approved by: Professor ___________________________________ Date: __________________ Dr. Lynn F. Fuller (Thesis Advisor) Professor ___________________________________ Date: __________________ Dr. Karl D. Hirschman (Thesis Committee Member) Professor ___________________________________ Date: __________________ Dr. Santosh K. Kurinec (Thesis Committee Member) Professor ___________________________________ Date: __________________ Dr. Robert Pearson (Director, Microelectronic Engineering Program) Professor ___________________________________ Date: __________________ Dr. Sohail Dianat (Chair, Electrical -
Discrete Cosine Transform Based Image Fusion Techniques VPS Naidu MSDF Lab, FMCD, National Aerospace Laboratories, Bangalore, INDIA E.Mail: [email protected]
View metadata, citation and similar papers at core.ac.uk brought to you by CORE provided by NAL-IR Journal of Communication, Navigation and Signal Processing (January 2012) Vol. 1, No. 1, pp. 35-45 Discrete Cosine Transform based Image Fusion Techniques VPS Naidu MSDF Lab, FMCD, National Aerospace Laboratories, Bangalore, INDIA E.mail: [email protected] Abstract: Six different types of image fusion algorithms based on 1 discrete cosine transform (DCT) were developed and their , k 1 0 performance was evaluated. Fusion performance is not good while N Where (k ) 1 and using the algorithms with block size less than 8x8 and also the block 1 2 size equivalent to the image size itself. DCTe and DCTmx based , 1 k 1 N 1 1 image fusion algorithms performed well. These algorithms are very N 1 simple and might be suitable for real time applications. 1 , k 0 Keywords: DCT, Contrast measure, Image fusion 2 N 2 (k 1 ) I. INTRODUCTION 2 , 1 k 2 N 2 1 Off late, different image fusion algorithms have been developed N 2 to merge the multiple images into a single image that contain all useful information. Pixel averaging of the source images k 1 & k 2 discrete frequency variables (n1 , n 2 ) pixel index (the images to be fused) is the simplest image fusion technique and it often produces undesirable side effects in the fused image Similarly, the 2D inverse discrete cosine transform is defined including reduced contrast. To overcome this side effects many as: researchers have developed multi resolution [1-3], multi scale [4,5] and statistical signal processing [6,7] based image fusion x(n1 , n 2 ) (k 1 ) (k 2 ) N 1 N 1 techniques. -
Temperature Compensation Circuit for ISFET Sensor
Journal of Low Power Electronics and Applications Article Temperature Compensation Circuit for ISFET Sensor Ahmed Gaddour 1,2,* , Wael Dghais 2,3, Belgacem Hamdi 2,3 and Mounir Ben Ali 3,4 1 National Engineering School of Monastir (ENIM), University of Monastir, Monastir 5000, Tunisia 2 Electronics and Microelectronics Laboratory, LR99ES30, Faculty of Sciences of Monastir, University of Monastir, Monastir 5000, Tunisia; [email protected] (W.D.); [email protected] (B.H.) 3 Higher Institute of Applied Sciences and Technology of Sousse (ISSATSo), University of Sousse, Sousse 4003, Tunisia; [email protected] 4 Nanomaterials, Microsystems for Health, Environment and Energy Laboratory, LR16CRMN01, Centre for Research on Microelectronics and Nanotechnology, Sousse 4034, Tunisia * Correspondence: [email protected]; Tel.: +216-50998008 Received: 3 November 2019; Accepted: 21 December 2019; Published: 4 January 2020 Abstract: PH measurements are widely used in agriculture, biomedical engineering, the food industry, environmental studies, etc. Several healthcare and biomedical research studies have reported that all aqueous samples have their pH tested at some point in their lifecycle for evaluation of the diagnosis of diseases or susceptibility, wound healing, cellular internalization, etc. The ion-sensitive field effect transistor (ISFET) is capable of pH measurements. Such use of the ISFET has become popular, as it allows sensing, preprocessing, and computational circuitry to be encapsulated on a single chip, enabling miniaturization and portability. However, the extracted data from the sensor have been affected by the variation of the temperature. This paper presents a new integrated circuit that can enhance the immunity of ion-sensitive field effect transistors (ISFET) against the temperature. -
Graphene Field-Effect Transistor Array with Integrated Electrolytic Gates Scaled to 200 Mm
Graphene field-effect transistor array with integrated electrolytic gates scaled to 200 mm N C S Vieira1,3, J Borme1, G Machado Jr.1, F Cerqueira2, P P Freitas1, V Zucolotto3, N M R Peres2 and P Alpuim1,2 1INL - International Iberian Nanotechnology Laboratory, 4715-330, Braga, Portugal. 2CFUM - Center of Physics of the University of Minho, 4710-057, Braga, Portugal. 3IFSC - São Carlos Institute of Physics, University of São Paulo, 13560-970, São Carlos-SP, Brazil E-mail: [email protected] Abstract Ten years have passed since the beginning of graphene research. In this period we have witnessed breakthroughs both in fundamental and applied research. However, the development of graphene devices for mass production has not yet reached the same level of progress. The architecture of graphene field-effect transistors (FET) has not significantly changed, and the integration of devices at the wafer scale has generally not been sought. Currently, whenever an electrolyte-gated FET (EGFET) is used, an external, cumbersome, out-of-plane gate electrode is required. Here, an alternative architecture for graphene EGFET is presented. In this architecture, source, drain, and gate are in the same plane, eliminating the need for an external gate electrode and the use of an additional reservoir to confine the electrolyte inside the transistor active zone. This planar structure with an integrated gate allows for wafer-scale fabrication of high-performance graphene EGFETs, with carrier mobility up to 1800 cm2 V-1 s-1. As a proof-of principle, a chemical sensor was achieved. It is shown that the sensor can discriminate between saline solutions of different concentrations. -
An Extended CMOS ISFET Model Incorporating the Physical Design
View metadata, citation and similar papers at core.ac.uk brought to you by CORE provided by Spiral - Imperial College Digital Repository IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. XXX, NO. XXX, XXX XXX 1 An Extended CMOS ISFET Model Incorporating the Physical Design Geometry and the Effects on Performance and Offset Variation Yan Liu, Student Member, IEEE, Pantelis Georgiou, Member, IEEE, Themistoklis Prodromakis, Member, IEEE, Timothy G. Constandinou, Senior Member, and Christofer Toumazou, Fellow, IEEE Abstract—This paper presents an extended model for the as large-scale, highly-integrated chemical sensor arrays [4], CMOS-based Ion-Sensitive-Field-Effect-Transistor (ISFET), in- [6]. corporating design parameters associated with the physical In this paper we present an extended model for CMOS- geometry of the device. This can, for the first time, provide a good match between calculated and measured characteristics by based ISFETs to include both the first order effects, (i.e. taking into account the effects of non-idealities such as threshold intrinsic dimension-related characteristics) and second order voltage variation and sensor noise. The model is evaluated effects, (i.e. non-linear characteristics). By focusing on the through a number of devices with varying design parameters effect of varying the design parameters (i.e physical dimen- (chemical sensing area and MOSFET dimensions) fabricated in sions) a capacitance-based model is derived which includes all a commercially-available 0.35µm CMOS technology. Threshold voltage, subthreshold slope, chemical sensitivity, drift and noise capacitive structures, the values of which are directly related were measured and compared to the simulated results. The to physical dimensions. -
An Integrated Semiconductor Device Enabling Non-Optical Genome Sequencing
ARTICLE doi:10.1038/nature10242 An integrated semiconductor device enabling non-optical genome sequencing Jonathan M. Rothberg1, Wolfgang Hinz1, Todd M. Rearick1, Jonathan Schultz1, William Mileski1, Mel Davey1, John H. Leamon1, Kim Johnson1, Mark J. Milgrew1, Matthew Edwards1, Jeremy Hoon1, Jan F. Simons1, David Marran1, Jason W. Myers1, John F. Davidson1, Annika Branting1, John R. Nobile1, Bernard P. Puc1, David Light1, Travis A. Clark1, Martin Huber1, Jeffrey T. Branciforte1, Isaac B. Stoner1, Simon E. Cawley1, Michael Lyons1, Yutao Fu1, Nils Homer1, Marina Sedova1, Xin Miao1, Brian Reed1, Jeffrey Sabina1, Erika Feierstein1, Michelle Schorn1, Mohammad Alanjary1, Eileen Dimalanta1, Devin Dressman1, Rachel Kasinskas1, Tanya Sokolsky1, Jacqueline A. Fidanza1, Eugeni Namsaraev1, Kevin J. McKernan1, Alan Williams1, G. Thomas Roth1 & James Bustillo1 The seminal importance of DNA sequencing to the life sciences, biotechnology and medicine has driven the search for more scalable and lower-cost solutions. Here we describe a DNA sequencing technology in which scalable, low-cost semiconductor manufacturing techniques are used to make an integrated circuit able to directly perform non-optical DNA sequencing of genomes. Sequence data are obtained by directly sensing the ions produced by template-directed DNA polymerase synthesis using all-natural nucleotides on this massively parallel semiconductor-sensing device or ion chip. The ion chip contains ion-sensitive, field-effect transistor-based sensors in perfect register with 1.2 million wells, which provide confinement and allow parallel, simultaneous detection of independent sequencing reactions. Use of the most widely used technology for constructing integrated circuits, the complementary metal-oxide semiconductor (CMOS) process, allows for low-cost, large-scale production and scaling of the device to higher densities and larger array sizes. -
The Design, Fabrication, and Testing of Corrugated Silicon Nitride Diaphragms
36 JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 3, NO. I, MARCH 1994 The Design, Fabrication, and Testing of Corrugated Silicon Nitride Diaphragms Patrick R. Scheeper, Wouter Olthuis, and Piet Bergveld Abstract-Silicon nitride corrugated diaphragms of 2 mm x 2 mm x lpm have been fabricated with 8 circular corrugations, having depths of 410, or 14 pm. The diaphragms with 4-pm-deep corrugations show a measured mechanical sensitivity (increase in the deflection over the increase in the applied pressure) which is 25 times larger than the mechanical sensitivity of flat diaphragms I of equal size and thickness. Since this gain in sensitivity is due to Fig. I. Schematic cross-sectional view of a circular corrugated diaphragm reduction of the initial stress, the sensitivity can only increase in and characteristic parameters. the case of diaphragms with initial stress. A simple analytical model has been proposed that takes the influence of initial tensile stress into account. The model predicts to-run reproducibility is determined by the reproducibility of that the presence of corrugations increases the sensitivity of the the initial conditions of the reactor (affected by contamination, diaphragms, because the initial diaphragm stress is reduced. The adsorbed water, previously deposited layers) and the accuracy model also predicts that for corrugations with a larger depth the sensitivity decreases, because the bending stiffness of the of the instruments which control the reactor temperature, the corrugations then becomes dominant. These predictions have pressure and the mass flow of the process gases. Variations of been confirmed by experiments. a factor 2 of the initial stress have been measured. -
Design and Analysis of Cmos Current Conveyor
JOURNAL OF INFORMATION, KNOWLEDGE AND RESEARCH IN ELECTRONICS AND COMMUNICATION ENGINEERING DESIGN AND ANALYSIS OF CMOS CURRENT CONVEYOR AMRUTA BHATT M.E [Signal processing and VLSI] Student, Department Of Electronics And Communication, Vishwakarma Government Engineering College, Chandkheda, Ahmedabad, Gujarat [email protected] ABSTRACT : Current conveyor is a high performance analog building block. It exhibits high linearity, wide bandwidth, lower power consumption, simpler circuitry and better high frequency performance. It has unity gain current and voltage. Current conveyor is a combination of voltage and current follower. In this report different second generation current conveyors are simulated for low voltage, low power and high bandwidth applications. The main feature of this current conveyor is their wide voltage and current transfer bandwidth which make them suitable for high frequency applications. The current conveyors are simulated using 130nm CMOS technology model parameters on NGSPICE using1.2Vsupply voltage. Keywords-Current conveyor, Current mode circuit, Voltage mode circuit 1. INTRODUCTION Current conveyors can be used in variety of Since the beginning of electronics the need of new applications ranging from multifunction and active device has been very important. It has driven universal filters, oscillators etc. Current conveyors the birth of transistor. It used in many applications, can give larger band-width and are suitable for low in particular voltage operational amplifier has voltage applications. Operational amplifier do not rapidly become the main analog block and has perform well where a current output signal is dominated the market. But there is a limitation of needed and consequently there is an application its constant gain band-with product and trend of field for current conveyor circuits. -
Advanced MOSFET Structures and Processes for Sub-7 Nm CMOS Technologies
Advanced MOSFET Structures and Processes for Sub-7 nm CMOS Technologies By Peng Zheng A dissertation submitted in partial satisfaction of the requirements for the degree of Doctor of Philosophy in Engineering - Electrical Engineering and Computer Sciences in the Graduate Division of the University of California, Berkeley Committee in charge: Professor Tsu-Jae King Liu, Chair Professor Laura Waller Professor Costas J. Spanos Professor Junqiao Wu Spring 2016 © Copyright 2016 Peng Zheng All rights reserved Abstract Advanced MOSFET Structures and Processes for Sub-7 nm CMOS Technologies by Peng Zheng Doctor of Philosophy in Engineering - Electrical Engineering and Computer Sciences University of California, Berkeley Professor Tsu-Jae King Liu, Chair The remarkable proliferation of information and communication technology (ICT) – which has had dramatic economic and social impact in our society – has been enabled by the steady advancement of integrated circuit (IC) technology following Moore’s Law, which states that the number of components (transistors) on an IC “chip” doubles every two years. Increasing the number of transistors on a chip provides for lower manufacturing cost per component and improved system performance. The virtuous cycle of IC technology advancement (higher transistor density lower cost / better performance semiconductor market growth technology advancement higher transistor density etc.) has been sustained for 50 years. Semiconductor industry experts predict that the pace of increasing transistor density will slow down dramatically in the sub-20 nm (minimum half-pitch) regime. Innovations in transistor design and fabrication processes are needed to address this issue. The FinFET structure has been widely adopted at the 14/16 nm generation of CMOS technology. -
A Novel MEMS Pressure Sensor with MOSFET on Chip
A Novel MEMS Pressure Sensor with MOSFET on Chip Zhao-Hua Zhang *, Yan-Hong Zhang, Li-Tian Liu, Tian-Ling Ren Tsinghua National Laboratory for Information Science and Technology Institute of Microelectronics, Tsinghua University Beijing 100084, China [email protected] Abstract—A novel MOSFET pressure sensor was proposed Figure 1. Two PMOSFET’s and two piezoresistors are based on the MOSFET stress sensitive phenomenon, in which connected to form a Wheatstone bridge. To obtain the the source-drain current changes with the stress in channel maximum sensitivity, these components are placed near the region. Two MOSFET’s and two piezoresistors were employed four sides of the silicon diaphragm, which are the high stress to form a Wheatstone bridge served as sensitive unit in the regions. The MOSFET’s has the same structure parameter novel sensor. Compared with the traditional piezoresistive W/L, same threshold voltage VT and gate-source voltage VGS pressure sensor, this MOSFET sensor’s sensitivity is improved (equal to VG-Vdd). They are designed to work in the significantly, meanwhile the power consumption can be saturation region. The piezoresistors also have the same decreased. The fabrication of the novel pressure sensor is low- resistance R . cost and compatible with standard IC process. It shows the 0 great promising application of MOSFET-bridge-circuit structure for the high performance pressure sensor. This kind of MEMS pressure sensor with signal process circuit on the same chip can be used in positive or negative Tire Pressure Monitoring System (TPMS) which is very hot in automotive electron research field. I. -
Fundamentals of MOSFET and IGBT Gate Driver Circuits
Application Report SLUA618A–March 2017–Revised October 2018 Fundamentals of MOSFET and IGBT Gate Driver Circuits Laszlo Balogh ABSTRACT The main purpose of this application report is to demonstrate a systematic approach to design high performance gate drive circuits for high speed switching applications. It is an informative collection of topics offering a “one-stop-shopping” to solve the most common design challenges. Therefore, it should be of interest to power electronics engineers at all levels of experience. The most popular circuit solutions and their performance are analyzed, including the effect of parasitic components, transient and extreme operating conditions. The discussion builds from simple to more complex problems starting with an overview of MOSFET technology and switching operation. Design procedure for ground referenced and high side gate drive circuits, AC coupled and transformer isolated solutions are described in great details. A special section deals with the gate drive requirements of the MOSFETs in synchronous rectifier applications. For more information, see the Overview for MOSFET and IGBT Gate Drivers product page. Several, step-by-step numerical design examples complement the application report. This document is also available in Chinese: MOSFET 和 IGBT 栅极驱动器电路的基本原理 Contents 1 Introduction ................................................................................................................... 2 2 MOSFET Technology ...................................................................................................... -
CMOS Operational Floating Current Conveyor Circuit for Instrumentation Amplifier Application
International Journal of Electrical and Electronic Engineering & Telecommunications Vol. 9, No. 5, September 2020 CMOS Operational Floating Current Conveyor Circuit for Instrumentation Amplifier Application Fahmi Elsayed, Mostafa Rashdan, and Mohammad Salman College of Engineering and Technology, American University of the Middle East, Kuwait Email: {fahmi.el-sayed; mostafa.rashdan; mohammad.salman}@aum.edu.kw Abstract—This paper presents a fully integrated CMOS output voltage terminal of the current feedback amplifier, Operational Floating Current Conveyor (OFCC) circuit. and has low output impedance. Both Z+ and Z- are high The proposed circuit is designed for instrumentation impedance output current terminals. The Z+ terminal has amplifier circuits. The CMOS OFCC circuit is designed and an output current equal in phase and magnitude to the W simulated using Cadence in TSMC 90 m technology kit. The terminal. For the Z- terminal, it has an output current circuit aims at two different design goals. The first goal is to design a low power consumption circuit (LBW design) while which has the same magnitude as the W terminal’s the second is to design a high bandwidth circuit (HBW current but is 180˚ out of phase. design). The total power consumption of the LBW design is 1.26 mW with 30 MHz bandwidth while the power consumption of the HBW design is 3 mW with 104.6 MHz bandwidth. Index Terms—Analog signal processing, CMOS, low power, low voltage, operational floating current conveyor, VLSI Fig. 1. OFCC block diagram. I. INTRODUCTION The following matrix equation explains the operation Current conveyors are commonly used in different of the exact OFCC circuits: applications such as instrumentation amplifier circuits [1], i y 00000 v y Operational Transconductance Amplifiers (OTA), analog filter designs and current multipliers [2], [3].