Static CMOS Circuits

• Conventional (ratio-less) static CMOS – Covered so far • Ratio-ed logic (depletion load, pseudo nMOS) • Pass transistor logic

ECE 261 James Morizio 1 Example 1 module mux(input s, d0, d1, output y);

assign y = s ? d1 : d0; endmodule

1) Sketch a design using AND, OR, and NOT gates.

ECE 261 James Morizio 2 Example 1 module mux(input s, d0, d1, output y);

assign y = s ? d1 : d0; endmodule

1) Sketch a design using AND, OR, and NOT gates. D0 S Y D1 S

ECE 261 James Morizio 3 Example 2

2) Sketch a design using NAND, NOR, and NOT gates. Assume ~S is available.

ECE 261 James Morizio 4 Example 2

2) Sketch a design using NAND, NOR, and NOT gates. Assume ~S is available.

D0 S Y D1 S

ECE 261 James Morizio 5 Bubble Pushing • Start with network of AND / OR gates • Convert to NAND / NOR + inverters • Push bubbles around to simplify logic – Remember DeMorgan’s Law

Y Y

(a) (b)

Y Y

D (c) (d)

ECE 261 James Morizio 6 Example 3

3) Sketch a design using one compound gate and one NOT gate. Assume ~S is available.

ECE 261 James Morizio 7 Example 3

3) Sketch a design using one compound gate and one NOT gate. Assume ~S is available.

D0 S Y D1 S

ECE 261 James Morizio 8 Compound Gates • Logical Effort of compound gates unit inverter AOI21 AOI22 Complex AOI Y = A Y = AB + C Y = AB + CD Y = A(B + C)+ DE D A A E Y B B A A Y Y Y C C B D C

A 4 B 4 A 4 B 4 B 6 2 C 4 C 4 D 4 C 6 A 3 A Y Y Y 1 A 2 A 2 C 2 D 6 E 6 C 1 Y B 2 B 2 D 2 E 2 A 2 D 2 B 2 C 2

gA = 3/3 gA = 6/3 gA = 6/3 gA = 5/3

p = 3/3 gB = 6/3 gB = 6/3 gB = 8/3

gC = 5/3 gC = 6/3 gC = 8/3

p = 7/3 gD = 6/3 gD = 8/3

p = 12/3 gE = 8/3 p = 16/3

ECE 261 James Morizio 9 Example 4 • The multiplexer has a maximum input capacitance of 16 units on each input. It must drive a load of 160 units. Estimate the delay of the NAND and compound gate designs. D0 D0 S S Y Y D1 D1 S S

H = 160 / 16 = 10 B = 1 N = 2

ECE 261 James Morizio 10 NAND Solution

D0 S Y D1 S

ECE 261 James Morizio 11 NAND Solution

P = 2 + 2 = 4 D0 S G = (4 / 3)(4 / 3) = 16 / 9 Y D1 F = GBH = 160 / 9 S fˆ = N F = 4.2 D = Nfˆ + P = 12.4τ

ECE 261 James Morizio 12 Compound Solution

D0 S Y D1 S

ECE 261 James Morizio 13 Compound Solution

P = 4 +1 = 5 D0 S Y G = (6/ 3)(1) = 2 D1 F = GBH = 20 S fˆ = N F = 4.5 D = Nfˆ + P = 14τ

ECE 261 James Morizio 14 Example 5 • Annotate your designs with transistor sizes that achieve this delay.

Y Y

Homework exercise!

ECE 261 James Morizio 15 Input Order

• Our parasitic delay model was too simple – Calculate parasitic delay for Y falling • If A arrives latest? • If B arrives latest?

2 2 Y A 2 6C x B 2 2C

ECE 261 James Morizio 16 Input Order

• Our parasitic delay model was too simple – Calculate parasitic delay for Y falling • If A arrives latest? 2τ • If B arrives latest? 2.33τ

2 2 Y A 2 6C x B 2 2C

ECE 261 James Morizio 17 Inner & Outer Inputs

2 2 • Outer input is closest to rail (B) Y A 2 • Inner input is closest to output (A) B 2

• If input arrival time is known – Connect latest input to inner terminal

ECE 261 James Morizio 18 Asymmetric Gates

• Asymmetric gates favor one input over another • Ex: suppose input A of a NAND gate is most critical

– Use smaller transistor on A (less capacitance) A Y – Boost size of noncritical input reset – So total resistance is same 2 2 • gA = 10/9 Y A 4/3 • gB = 2 reset 4 • gtotal = gA + gB = 28/9 • Asymmetric gate approaches g = 1 on critical input • But total logical effort goes up

ECE 261 James Morizio 19 Symmetric Gates

• Inputs can be made perfectly symmetric 2 2 Y A 1 1 B 1 1

ECE 261 James Morizio 20 Skewed Gates • Skewed gates favor one edge over another • Ex: suppose rising output of inverter is most critical – Downsize noncritical nMOS transistor HI-skew unskewed inverter unskewed inverter inverter (equal rise resistance) (equal fall resistance)

2 2 1 A Y A Y A Y 1/2 1 1/2

• Calculate logical effort by comparing to unskewed inverter with same effective resistance on that edge.

– gu =

– gd =

ECE 261 James Morizio 21 Skewed Gates • Skewed gates favor one edge over another • Ex: suppose rising output of inverter is most critical – Downsize noncritical nMOS transistor HI-skew unskewed inverter unskewed inverter inverter (equal rise resistance) (equal fall resistance)

2 2 1 A Y A Y A Y 1/2 1 1/2 • Calculate logical effort by comparing to unskewed inverter with same effective resistance on that edge.

– gu = 2.5 / 3 = 5/6

– gd = 2.5 / 1.5 = 5/3

ECE 261 James Morizio 22 HI- and LO-Skew

• Def: Logical effort of a skewed gate for a particular transition is the ratio of the input capacitance of that gate to the input capacitance of an unskewed inverter delivering the same output current for the same transition.

• Skewed gates reduce size of noncritical transistors – HI-skew gates favor rising output (small nMOS) – LO-skew gates favor falling output (small pMOS) • Logical effort is smaller for favored direction • But larger for the other direction

ECE 261 James Morizio 23 Catalog of Skewed Gates

Inverter NAND2 NOR2

2 2 B 4 Y A 4 2 A 2 unskewed A Y Y 1 B 2 1 1 gu = 1 gu = 4/3 gu = 5/3 gd = 1 gd = 4/3 gd = 5/3 gavg = 1 gavg = 4/3 gavg = 5/3 B Y A 2 A HI-skew A Y Y 1/2 B gu = 5/6 gu = gu = gd = 5/3 gd = gd = gavg = 5/4 gavg = gavg = B Y A 1 A LO-skew A Y Y 1 B gu = 4/3 gu = gu = gd = 2/3 gd = gd = gavg = 1 gavg = gavg =

ECE 261 James Morizio 24 Catalog of Skewed Gates

Inverter NAND2 NOR2

2 2 B 4 Y A 4 2 A 2 unskewed A Y Y 1 B 2 1 1 gu = 1 gu = 4/3 gu = 5/3 gd = 1 gd = 4/3 gd = 5/3 gavg = 1 gavg = 4/3 gavg = 5/3 2 2 B 4 Y A 4 2 A 1 HI-skew A Y Y 1/2 B 1 1/2 1/2 gu = 5/6 gu = gu = gd = 5/3 gd = gd = gavg = 5/4 gavg = gavg = 1 1 B 2 Y A 2 1 A 2 LO-skew A Y Y 1 B 2 1 1 gu = 4/3 gu = gu = gd = 2/3 gd = gd = gavg = 1 gavg = gavg =

ECE 261 James Morizio 25 Catalog of Skewed Gates

Inverter NAND2 NOR2

2 2 B 4 Y A 4 2 A 2 unskewed A Y Y 1 B 2 1 1 gu = 1 gu = 4/3 gu = 5/3 gd = 1 gd = 4/3 gd = 5/3 gavg = 1 gavg = 4/3 gavg = 5/3 2 2 B 4 Y A 4 2 A 1 HI-skew A Y Y 1/2 B 1 1/2 1/2 gu = 5/6 gu = 1 gu = 3/2 gd = 5/3 gd = 2 gd = 3 gavg = 5/4 gavg = 3/2 gavg = 9/4 1 1 B 2 Y A 2 1 A 2 LO-skew A Y Y 1 B 2 1 1 gu = 4/3 gu = 2 gu = 2 gd = 2/3 gd = 1 gd = 1 gavg = 1 gavg = 3/2 gavg = 3/2

ECE 261 James Morizio 26 Asymmetric Skew

• Combine asymmetric and skewed gates – Downsize noncritical transistor on unimportant input – Reduces parasitic delay for critical input

A Y reset

1 2 Y A 4/3 reset 4

ECE 261 James Morizio 27 Best P/N Ratio

• We have selected P/N ratio for unit rise and fall resistance (µ = 2-3 for an inverter). • Alternative: choose ratio for least average delay • Ex: inverter P A – Delay driving identical inverter 1

– tpdf =

– tpdr =

– tpd =

– Differentiate tpd w.r.t. P – Least delay for P =

ECE 261 James Morizio 28 Best P/N Ratio

– tpdf = (P+1)

– tpdr = (P+1)(µ/P)

– tpd = (P+1)(1+µ/P)/2 = (P + 1 + µ + µ/P)/2

– Differentiate tpd w.r.t. P – Least delay for P = µ

ECE 261 James Morizio 29 P/N Ratios

• In general, best P/N ratio is sqrt of that giving equal delay. – Only improves average delay slightly for inverters – But significantly decreases area and power Inverter NAND2 NOR2

2 2 B 2 Y A 2 fastest 1.414 A 2 A Y Y P/N ratio 1 B 2 1 1 gu = 1.15 gu = 4/3 gu = 2 gd = 0.81 gd = 4/3 gd = 1 gavg = 0.98 gavg = 4/3 gavg = 3/2

ECE 261 James Morizio 30 Observations

• For speed: – NAND vs. NOR – Many simple stages vs. fewer high fan-in stages – Latest-arriving input • For area and power: – Many simple stages vs. fewer high fan-in stages

ECE 261 James Morizio 31 Combinational vs. Sequential Logic

Out Logic In Logic In Out Circuit Circuit

State

(a) Combinational (b) Sequential

Output = f(In) Output = f(In, Previous In)

ECE 261 James Morizio 32 Static CMOS Circuit (Review)

At every point in time (except during the switching transients) each gate output is connected to either VDD or Vss via a low-resistive path. The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes.

ECE 261 James Morizio 33 Static CMOS (Review) VDD

In1 In2 PUN PMOS Only In3

F = G

In1 In2 PDN NMOS Only In3

VSS

PUN and PDN are Dual Networks

ECE 261 James Morizio 34 Properties of Complementary CMOS Gates (Review)

High noise margins:

VOH and VOL are at VDD and GND, respectively. No static power consumption:

There never exists a direct path between VDD and VSS (GND) in steady-state mode. Comparable rise and fall times: (under the appropriate scaling conditions)

ECE 261 James Morizio 35 Influence of Fan-In and Fan-Out on Delay

VDD

A B C D Fan-Out: Number of Gates Connected Every fanout (output) adds two gate capacitances (pMOS and nMOS) A B FanIn: Quadratic Term due to: C 1. Resistance Increasing D 2. Capacitance Increasing

a 2 + tp = a1FI + 2FI a3FO

ECE 261 James Morizio 36 Fast Complex Gate-Design Techniques • Trans is tor Sizing: As long as Fan-out Capacitance dominates • Progres s ive Sizing:

Out

InN MN CL M1 > M2 > M3 > MN

C3 In3 M3

C In2 M2 2

In1 M1 C1

ECE 261 James Morizio 37 Fast Complex Gate - Design Techniques • Trans is tor Ordering

critical path critical path

CL CL In3 M3 In1 M1

C2 C2 In2 M2 In2 M2

C1 C In1 M1 In3 M3 3

(a) (b)

ECE 261 James Morizio 38 Fast Complex Gate - Design Techniques

• Improved Logic Des ign

ECE 261 James Morizio 39 Ratioed Logic

VDD VDD VDD

Resistive Depletion PMOS Load RL Load VT < 0 Load VSS F F F In1 In1 In1 In2 PDN In2 PDN In2 PDN In3 In3 In3

VSS VSS VSS (a) resistive load (b) depletion load NMOS (c) pseudo-NMOS

Goal: to reduce the number of devices over complementary CMOS Careful design needed!

ECE 261 James Morizio 40 Ratioed Logic

VDD • VOH = VDD

RPDN VDD Resistive VOL = RL + RPDN Load RL

Desired: RL >> RPDN (to keep noise margin low) F

t = 0.69R C In1 PLH L L

In2 PDN RPDN In3 Problems: 1) Static power dissipation

2) Difficult to implement a large VSS resistor, eg 40kΩ resistor (typical value) needs 3200 µ2 of n-diff, i.e. 1,000 transistors!

ECE 261 James Morizio 41 Active Loads VDD VDD

Depletion PMOS Load VT < 0 Load

VSS F F

In1 In1 In2 PDN In2 PDN In3 In3

VSS VSS depletion load NMOS pseudo-NMOS • Depletion-mode transistor has negative threshold

• On if VGS = 0 • Body effect may be a problem!

ECE 261 James Morizio 42 Pseudo-nMOS VDD

F C A B C D L

• No problems due to body effect • N-input gate requires only N+1 transistors • Each input connects to only a single transistor, presenting smaller load to preceding gate • Static power dissipation (when output is zero) • Asymmetric rise and fall times Example: Suppose minimal-sized gate consumes 1 mW of static power. 100, 000 gate-circuit: 50 W of static power (plus dynamic power)! (half the gates are in low-output state) • Effective only for small subcircuits where speed is important, eg address decoders in memories

ECE 261 James Morizio 43 Pseudo-NMOS NAND Gate

VDD

GND

ECE 261 James Morizio 44 Pass-Transistor Logic

Out A Switch Out Inputs Network B B

Is this transmission gates necessary? AND gate Need a low impedance path to ground when B = 0

• No s tatic cons umption

ECE 261 James Morizio 45 Pass-Transistor Based Multiplexer

S S

F = AS + BS VDD

V S DD

A M2 Out F

S F

M1 B

S GND

In1 S S In2

ECE 261 James Morizio 46 Transmission Gate XOR

B 6 transistors only! Case 1: B M2 B = 1, M3/M4 turned off, F = AB

A A Case 2: F B = 0, M3/M4 turned on, F = AB M1 M3/M4 B

F always has a path to VDD or Gnd, hence low impedance node If not, node would be dynamic, requiring refresh due to charge leakage

ECE 261 James Morizio 47 Delay in Transmission Gate Networks

5 5 5 5 V1 V Vi V Vn-1 V In i-1 i+1 n

C C C 0 0 C 0 C 0

(a)

Req Req Req Req V1 Vi V Vn-1 V In i+1 n

C C C C C

(b) m

Req Req Req Req Req Req In C C C C C C C C

ECE 261 James Morizio 48 Delay in Transmission Gate Networks

Consider Kirchoff’s Law at node Vi Vi+1-Vi + Vi-1-Vi C dVi = dt Req Req

Therefore, dV V + V - 2V =i i+1 i-1 i dt ReqC

Propagation delay can be determined using Elmore delay analysis

ECE 261 James Morizio 49 Delay Optimization

Delay can be reduced by adding buffers after m stages

(tbuf = delay of a buffer)

ECE 261 James Morizio 50 Transmission Gate Full Adder

P VDD V C DD A i P S Sum Generation A A P Ci

A P V B B DD V A DD P P Co Carry Generation

Ci Ci Ci A Setup P

ECE 261 James Morizio 51 NMOS Only Logic: Level Restoring Transistor

VDD Level Restorer VDD Mr B M2 X A Mn Out

• Advantage: Full Swing • Disadvantage: More Complex, Larger Capacitance • Other approaches: reduced threshold NMOS

ECE 261 James Morizio 52 Single Transistor Pass Gate with VT=0

VDD

VDD 0V 5V

Out VDD 0V

WATCH OUT FOR LEAKAGE CURRENTS

ECE 261 James Morizio 53 Complimentary Pass Transistor Logic

A Pass-Transistor A B Network F B (a)

A Inverse A Pass-Transistor F B B Network

B B B B B B

A A A

B F=AB B F=A+B A F=A⊕Β (b) A A A

B F=AB B F=A+B A F=A⊕Β

AND/NAND OR/NOR EXOR/NEXOR

ECE 261 James Morizio 54 4 Input NAND in CPL

ECE 261 James Morizio 55