Representations of Bits and and OR Gates Using Switches

Representations of bits

Table 3-1 Physical states representing bits in different computer logic and memory technologies.

State Representing Bit

Technology 0 1

Pneumatic logic Fluid at low pressure Fluid at high pressure Relay logic Circuit open Circuit closed Complementary metal-oxide 0–1.5 V 3.5–5.0 V semiconductor (CMOS) logic Transistor-transistor logic (TTL) 0–0.8 V 2.0–5.0 V Fiber optics Light off Light on Dynamic memory Capacitor discharged Capacitor charged Nonvolatile, erasable memory Electrons trapped Electrons released Bipolar read-only memory Fuse blown Fuse intact Bubble memory No magnetic bubble Bubble present Magnetic tape or disk Flux direction “north” Flux direction “south” Polymer memory Molecule in state A Molecule in state B Read-only compact disc No pit Pit Rewriteable compact disc Dye in crystalline state Dye in noncrystalline state

Not all logic representations are suitable for logic gates. Logic device must outputs that are of the same type as its inputs.

October 3, 2002 EE 121: Digital Design Laboratory Lecture 3 – 1

AND and OR gates using switches

Single-pole single-throw (SPST) switches are either normally open (n.o.) or normally closed (n.c.). Normally-open switches can be used to build AND and OR gates.

AND gate: serial connection: OR gate: parallel connection:

+ + V− LED V− LED

AB AB

October 3, 2002 EE 121: Digital Design Laboratory Lecture 3 – 2 MOS transistors

Logic levels for CMOS circuits have wide range, from > 12 Vdownto∼1V. Often 5 V is used for compatibility with older logic families (TTL). 5.0 V Logic 1 (HIGH) 3.5 V undefined logic level 1.5 V Logic 0 (LOW) 0.0 V

VIN

Voltage-controlled resistance: − drain increase V ==> decrease R Voltage-controlled resistance: gate gs ds Vgs decrease Vgs ==> decrease Rds + + source source ≥ gate V Note: normally, Vgs 0 drain gs ≤ − Note: normally, Vgs 0 Copyright © 2000 by Prentice Hall, Inc. Copyright © 2000 by Prentice Hall, Inc. October 3, 2002Digital Design Principles and Practices, EE3/e 121: Digital Design LaboratoryDigital Design Principles and Practices, 3/e Lecture 3 – 3

CMOS inverter Schematic, function table, and logic symbol:

VDD = +5.0 V

Q2 on when (b) VIN Q1 Q2 V OUT (p-channel) Q2 VIN is low (p-channel) 0.0 (L) off on 5.0 (H) VOUT 5.0 (H) on off 0.0 (L) Q1 VOUT on when VIN (n-channel) Q1 VIN is high VIN (n-channel)

Switch view of CMOS inverter:

VDD = +5.0 V VDD = +5.0 V (a) (b)

VIN = L VOUT = H VIN = H VOUT = L

Copyright © 2000 by Prentice Hall, Inc. Digital Design Principles and Practices, 3/e October 3, 2002 EE 121: Digital Design Laboratory Lecture 3 – 4 CMOS NAND Schematic, function table, and logic symbol:

(b) A B Q1 Q2 Q3 Q4 Z Q2 Q4 L L off on off on H L H off on on off H Z H L on off off on H H H on off on off L A Q1

A B Q3 (c) Z B

Switch models for CMOS NAND gate:

V V V (a) DD (b) DD (c) DD

Z = H Z = H Z = L

A = L A = H A = H

B = L B = L B = H

CMOS NOR

V (a) DD

A Q2 (b) A B Q1 Q2 Q3 Q4 Z L L off on off on H L H off on on off L B Q4 H L on off off on L H H on off on off L Z

A Q1 Q3 (c) Z B

NAND and NOR are dual Boolean functions (to be discussed later). Their logic circuits are dual circuits. Performance of NAND or NOR is not the same because pMOS and nMOS transistors have diﬀerent characteristics. CMOS NAND gates are faster than NOR gates because of series connnection of n-channel transistors has higher conductance than series connection of p-channel transistors.

October 3, 2002 EE 121: Digital Design Laboratory Lecture 3 – 6 n-input NAND and NOR

V (a)DD (b)

A B C Q1 Q2 Q3 Q4 Q5 Q6 Z

Q2 Q4 Q6 L L L off on off on off on H L L H off on off on on off H L H L off on on off off on H L H H off on on off on off H Z H L L on off off on off on H H L H on off off on on off H H H L on off on off off on H A Q1 H H H on off on off on off L

B Q3 (c) A B Z C Q5 C

This implementation of n-input NAND or NOR uses n pairs of transistors. Unfortunately, delay increases with the number of inputs:

delay ≈ a + bn2

October 3, 2002 EE 121: Digital Design Laboratory Lecture 3 – 7

Large fan-in gates

For a large number of inputs, it is faster to use multiple gates. Example: 8-input NAND might be faster using three small gate delays.

I1 I1 I2 I2 I3 I3 I4 I4 OUT OUT I5 I5 I6 I6 I7 I7 I8 I8

Copyright © 2000 by Prentice Hall, Inc. Digital Design Principles and Practices, 3/e Note the tradeoﬀ between speed and cost: 22 transistors vs. 16 transistors. Cost is proportional to the number of transistors or area in integrated circuit.

October 3, 2002 EE 121: Digital Design Laboratory Lecture 3 – 8 CMOS AND-OR-INVERT

The circuit below uses two AND gates (2 · 6=12T) and one NOR gate (4T).

B Z C

(a) (b) A B C D Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Z

A Q2 Q4 L L L L off on off on off on off on H L L L H off on off on off on on off H B L L H L off on off on on off off on H L L H H off on off on on off on off L L H L L off on on off off on off on H Q6 Q8 L H L H off on on off off on on off H L H H L off on on off on off off on H Z L H H H off on on off on off on off L H L L L on off off on off on off on H H L L H on off off on off on on off H C Q5 Q3 H L H L on off off on on off off on H H L H H on off off on on off on off L H H L L on off on off off on off on L H H L H on off on off off on on off L D Q7 Q1 H H H L on off on off on off off on L H H H H on off on off on off on off L

October 3, 2002 EE 121: Digital Design Laboratory Lecture 3 – 9

CMOS steady-state electrical behavior

(b) VIN Q1 Q2 V OUT Q2 (p-channel) 0.0 (L) off on 5.0 (H) 5.0 (H) on off 0.0 (L) VOUT Q1 VIN (n-channel)

VOUT

5.0 HIGH V 3.5 CC VOHmin HIGH High-state undefined DC noise margin 0.7 VCC VIHmin

1.5 ABNORMAL V LOW 0.3 VCC ILmax LOW Low-state 0 V IN V DC noise margin 0 1.5 3.5 5.0 0 OLmax LOWundefined HIGH Copyright © 2000 by Prentice Hall, Inc. Copyright © 2000 by Prentice Hall, Inc. Digital Design Principles and Practices, 3/e Digital Design Principles and Practices, 3/e

October 3, 2002 EE 121: Digital Design Laboratory Lecture 3 – 10 Resistive loads, nonideal inputs

(a) VCC (b) VCC "sourcing current" CMOS CMOS inverter inverter Rp Rp resistive > 1 MΩ load VOLmax VOHmin VIN VIN I I R OLmax resistive R OHmax n load n > 1 MΩ

"sinking current" Copyright © 2000 by Prentice Hall, Inc. Digital Design Principles and Practices, 3/e Output voltage will diﬀer from ideal high or low if too much output current. The voltage shift may not matter for analog applications (LEDs). But the output should not also be connected to inputs of CMOS gates. Intermediate input voltages (e.g., 2.5 V) cause both transistors to turn on partially and steady state current to ﬂow. Unused inputs should be connected to some signal or voltage level.

+5 V (a) (b) (c) X Z 1 kΩ logic 1 logic 0 X Z 1 k Ω Z X Copyright © 2000 by Prentice Hall, Inc. Digital Design Principles and Practices, 3/e October 3, 2002 EE 121: Digital Design Laboratory Lecture 3 – 11

Timing diagrams

(a)

(b)

tr tf

TEST CIRCUIT FOR ALL OUTPUTS LOADING

VCC ParameterRL CL S1 S2 VCC tpZH 50 pF Open Closed ten 1 KΩ or S1 tpZL 150 pF Closed Open V VIN Device OUT R Pulse L tpHZ Open Closed Under tdis 1 KΩ Generator Test tpLZ Closed Open

S2 50 pF C t — or Open Open R L pd T 150 pF

DEFINITIONS: CL = Load capacitance, includes jig and probe capacitance. SETUP, HOLD, AND RELEASE TIMES RT = Termination resistance, should equal ZOUT of the Pulse Generator. V Data CC Input 50% 0.0 V tSU tH PULSE WIDTH V Clock CC Input 50% VOH 0.0 V LOW-HIGH-LOW t Pulse 50% REM V V OL Asynchronous Control CC tW Input (PR, CLR, etc.) 50% VOH HIGH-LOW-HIGH 0.0 V 50% Pulse V V OL Synchronous Control CC Input (CLKEN, etc.) 50% 0.0 V tSU tH

PROPAGATION DELAY THREE-STATE ENABLE AND DISABLE TIMES Enable Disable V V Same-Phase CC Control CC Input Transition 50% Input 50% 0.0 V 0.0 V tPLH tPHL tPZL tPLZ VOH VCC Output Output 50% Transition 50% Normally LOW 10% VOL VOL t t t t PLH PHL PZH PHZ V VCC OH Opposite-Phase Output 90% Input Transition 50% Normally HIGH 50% 0.0 V 0.0 V

V = +5.0 V DD VCC = +5.0 V Equivalent load for transition-time analysis CMOS inverter R Q2 on when p (p-channel) VIN is low R V L V OUT OUT VIN Q1 on when + VIN (n-channel) Rn VIN is high CL VL −

200 Ω > 1 MΩ AC load AC load

VOUT = 5.0 V VOUT VIN VIN I = 0 OUT I > 1 MΩ 100 Ω OUT 100 pF 100 pF

October 3, 2002 EE 121: Digital Design Laboratory Lecture 3 – 13

CMOS dynamic electrical behavior (2)

200 Ω > 1 MΩ AC load AC load

VOUT = 5.0 V VOUT VIN VIN I = 0 OUT I > 1 MΩ 100 Ω OUT 100 pF 100 pF

Fall time for high-to-low transition of CMOS output

> 1 MΩ 100 Ω

5 V

3.5 V VOUT

1.5 V

0 V 0 time

October 3, 2002 EE 121: Digital Design Laboratory Lecture 3 – 14 CMOS dynamic electrical behavior (3)

> 1 MΩ 200 Ω AC load AC load

VOUT = 0 V VOUT VIN VIN I = 0 OUT I 100 Ω > 1 MΩ OUT 100 pF 100 pF

Fall time for low-to-high transition of CMOS output

Rp Rn 200 Ω > 1 MΩ

> 1 MΩ 100 Ω

5 V

3.5 V VOUT

1.5 V

0 V 0 time

Propagation delays

(a) VIN

VOUT

tpHL tpLH

(b) VIN

VOUT

tpHL tpLH

October 3, 2002 EE 121: Digital Design Laboratory Lecture 3 – 16 Power consumption

Current ﬂows from power to ground through transistors, but may pause on capacitors (input gates of other CMOS devices).

> 1 MΩ 200 Ω AC load AC load

VOUT = 0 V VOUT VIN VIN I = 0 OUT I 100 Ω > 1 MΩ OUT 100 pF 100 pF

October 3, 2002 EE 121: Digital Design Laboratory Lecture 3 – 17

Power consumption (2)

200 Ω > 1 MΩ AC load AC load

VOUT = 5.0 V VOUT VIN VIN I = 0 OUT I > 1 MΩ 100 Ω OUT 100 pF 100 pF

2 Power consumption formula: P = CPD · VDD · f CPD eﬀective capacitance VDD power-supply voltage f number of output transitions per second

October 3, 2002 EE 121: Digital Design Laboratory Lecture 3 – 18 Transmission gates

EN_L

normally AB complementary

Multiplexers can be built using T-gates:

VCC

October 3, 2002 EE 121: Digital Design Laboratory Lecture 3 – 19

Transmission gates (2)

This circuit uses only 6T compared to 14T for the NAND-NAND circuit:

1 Z (a) (b) 0 1 X XZP ZP ZP 0 Z F 1 YZ 0 YZ 1 Y XZP 0

Warning: delays through transmission gates can add up.

October 3, 2002 EE 121: Digital Design Laboratory Lecture 3 – 20