Representations of bits Table 3-1 Physical states representing bits in different computer logic and memory technologies. State Representing Bit Technology 0 1 Pneumatic logic Fluid at low pressure Fluid at high pressure Relay logic Circuit open Circuit closed Complementary metal-oxide 0–1.5 V 3.5–5.0 V semiconductor (CMOS) logic Transistor-transistor logic (TTL) 0–0.8 V 2.0–5.0 V Fiber optics Light off Light on Dynamic memory Capacitor discharged Capacitor charged Nonvolatile, erasable memory Electrons trapped Electrons released Bipolar read-only memory Fuse blown Fuse intact Bubble memory No magnetic bubble Bubble present Magnetic tape or disk Flux direction “north” Flux direction “south” Polymer memory Molecule in state A Molecule in state B Read-only compact disc No pit Pit Rewriteable compact disc Dye in crystalline state Dye in noncrystalline state Not all logic representations are suitable for logic gates. Logic device must outputs that are of the same type as its inputs. October 3, 2002 EE 121: Digital Design Laboratory Lecture 3 { 1 AND and OR gates using switches Single-pole single-throw (SPST) switches are either normally open (n.o.) or normally closed (n.c.). Normally-open switches can be used to build AND and OR gates. AND gate: serial connection: OR gate: parallel connection: + + V− LED V− LED AB AB October 3, 2002 EE 121: Digital Design Laboratory Lecture 3 { 2 MOS transistors Logic levels for CMOS circuits have wide range, from > 12 Vdownto»1V. Often 5 V is used for compatibility with older logic families (TTL). 5.0 V Logic 1 (HIGH) 3.5 V undefined logic level 1.5 V Logic 0 (LOW) 0.0 V Copyright © 2000 by Prentice Hall, Inc. Digital Design Principles and Practices, 3/e MOS transistors are voltage-controlled resistances that we use as switches. VIN Copyright © 2000 by Prentice Hall, Inc. Digital Design Principles and Practices, 3/e n-type transistors are normally open; p-type transistors are normally closed. Voltage-controlled resistance: − drain increase V ==> decrease R Voltage-controlled resistance: gate gs ds Vgs decrease Vgs ==> decrease Rds + + source source ≥ gate V Note: normally, Vgs 0 drain gs ≤ − Note: normally, Vgs 0 Copyright © 2000 by Prentice Hall, Inc. Copyright © 2000 by Prentice Hall, Inc. October 3, 2002Digital Design Principles and Practices, EE3/e 121: Digital Design LaboratoryDigital Design Principles and Practices, 3/e Lecture 3 { 3 CMOS inverter Schematic, function table, and logic symbol: VDD = +5.0 V VDD = +5.0 V Copyright © 2000 by Prentice Hall, Inc. (a) Digital Design Principles and Practices, 3/e Q2 on when (b) VIN Q1 Q2 V OUT (p-channel) Q2 VIN is low (p-channel) 0.0 (L) off on 5.0 (H) VOUT 5.0 (H) on off 0.0 (L) Q1 VOUT on when VIN (n-channel) Q1 VIN is high VIN (n-channel) (c) IN OUT Copyright © 2000 by Prentice Hall, Inc. Digital Design Principles and Practices, 3/e Switch view of CMOS inverter: VDD = +5.0 V VDD = +5.0 V (a) (b) VIN = L VOUT = H VIN = H VOUT = L Copyright © 2000 by Prentice Hall, Inc. Digital Design Principles and Practices, 3/e October 3, 2002 EE 121: Digital Design Laboratory Lecture 3 { 4 CMOS NAND Schematic, function table, and logic symbol: VDD Copyright © 2000 by Prentice Hall, Inc. (a) Digital Design Principles and Practices, 3/e (b) A B Q1 Q2 Q3 Q4 Z Q2 Q4 L L off on off on H L H off on on off H Z H L on off off on H H H on off on off L A Q1 A B Q3 (c) Z B Switch models for CMOS NAND gate: V V V (a) DD (b) DD (c) DD Z = H Z = H Z = L A = L A = H A = H B = L B = L B = H Copyright © 2000 by Prentice Hall, Inc. Digital Design Principles and Practices, 3/e October 3, 2002 EE 121: Digital Design Laboratory Lecture 3 { 5 CMOS NOR V (a) DD A Q2 (b) A B Q1 Q2 Q3 Q4 Z L L off on off on H L H off on on off L B Q4 H L on off off on L H H on off on off L Z A Q1 Q3 (c) Z B Copyright © 2000 by Prentice Hall, Inc. Digital Design Principles and Practices, 3/e NAND and NOR are dual Boolean functions (to be discussed later). Their logic circuits are dual circuits. Performance of NAND or NOR is not the same because pMOS and nMOS transistors have di®erent characteristics. CMOS NAND gates are faster than NOR gates because of series connnection of n-channel transistors has higher conductance than series connection of p-channel transistors. October 3, 2002 EE 121: Digital Design Laboratory Lecture 3 { 6 n-input NAND and NOR V (a)DD (b) A B C Q1 Q2 Q3 Q4 Q5 Q6 Z Q2 Q4 Q6 L L L off on off on off on H L L H off on off on on off H L H L off on on off off on H L H H off on on off on off H Z H L L on off off on off on H H L H on off off on on off H H H L on off on off off on H A Q1 H H H on off on off on off L B Q3 (c) A B Z C Q5 C Copyright © 2000 by Prentice Hall, Inc. Digital Design Principles and Practices, 3/e This implementation of n-input NAND or NOR uses n pairs of transistors. Unfortunately, delay increases with the number of inputs: delay ¼ a + bn2 October 3, 2002 EE 121: Digital Design Laboratory Lecture 3 { 7 Large fan-in gates For a large number of inputs, it is faster to use multiple gates. Example: 8-input NAND might be faster using three small gate delays. I1 I1 I2 I2 I3 I3 I4 I4 OUT OUT I5 I5 I6 I6 I7 I7 I8 I8 Copyright © 2000 by Prentice Hall, Inc. Digital Design Principles and Practices, 3/e Note the tradeo® between speed and cost: 22 transistors vs. 16 transistors. Cost is proportional to the number of transistors or area in integrated circuit. October 3, 2002 EE 121: Digital Design Laboratory Lecture 3 { 8 CMOS AND-OR-INVERT The circuit below uses two AND gates (2 ¢ 6=12T) and one NOR gate (4T). A B Z C D Copyright © 2000 by Prentice Hall, Inc. Digital Design Principles and Practices, 3/e This logic function can be implemented directly using 8 transistors. V Copyright © 2000 by Prentice Hall, Inc. DD Digital Design Principles and Practices, 3/e (a) (b) A B C D Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Z A Q2 Q4 L L L L off on off on off on off on H L L L H off on off on off on on off H B L L H L off on off on on off off on H L L H H off on off on on off on off L L H L L off on on off off on off on H Q6 Q8 L H L H off on on off off on on off H L H H L off on on off on off off on H Z L H H H off on on off on off on off L H L L L on off off on off on off on H H L L H on off off on off on on off H C Q5 Q3 H L H L on off off on on off off on H H L H H on off off on on off on off L H H L L on off on off off on off on L H H L H on off on off off on on off L D Q7 Q1 H H H L on off on off on off off on L H H H H on off on off on off on off L October 3, 2002 EE 121: Digital Design Laboratory Lecture 3 { 9 CMOS steady-state electrical behavior VDD = +5.0 V Copyright © 2000 by Prentice Hall, Inc. (a) Digital Design Principles and Practices, 3/e (b) VIN Q1 Q2 V OUT Q2 (p-channel) 0.0 (L) off on 5.0 (H) 5.0 (H) on off 0.0 (L) VOUT Q1 VIN (n-channel) (c) IN OUT VOUT 5.0 HIGH V 3.5 CC VOHmin HIGH High-state undefined DC noise margin 0.7 VCC VIHmin 1.5 ABNORMAL V LOW 0.3 VCC ILmax LOW Low-state 0 V IN V DC noise margin 0 1.5 3.5 5.0 0 OLmax LOWundefined HIGH Copyright © 2000 by Prentice Hall, Inc. Copyright © 2000 by Prentice Hall, Inc. Digital Design Principles and Practices, 3/e Digital Design Principles and Practices, 3/e October 3, 2002 EE 121: Digital Design Laboratory Lecture 3 { 10 Resistive loads, nonideal inputs (a) VCC (b) VCC "sourcing current" CMOS CMOS inverter inverter Rp Rp resistive > 1 MΩ load VOLmax VOHmin VIN VIN I I R OLmax resistive R OHmax n load n > 1 MΩ "sinking current" Copyright © 2000 by Prentice Hall, Inc. Digital Design Principles and Practices, 3/e Output voltage will di®er from ideal high or low if too much output current. The voltage shift may not matter for analog applications (LEDs). But the output should not also be connected to inputs of CMOS gates.