DOCSLIB.ORG

SEMICONDUCTORS: LOGIC CMOS 4000 SERIES Jameco Part# Manufacturer Manufacturer Part # Description Package Type Price 1

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
SEMICONDUCTORS: LOGIC CMOS 4000 SERIES Jameco Part# Manufacturer Manufacturer Part # Description Package Type Price 1 Click Here to Request a Large Quantity Quote SEMICONDUCTORS: LOGIC CMOS 4000 SERIES Jameco Part# Manufacturer Manufacturer Part # Description Package Type Price 1 12562 Major Brands CD4001B IC CD4001 QUAD 2-INPUT NOR GATE DIP 14 $ 0.49 675964 Major Brands CD4002B IC CD4002B DUAL 4-INPUT NOR GATE DIP 14 $ 0.49 2228711 Major Brands CD4006B IC CD4006B CMOS 18-Stage Static Shift Register DIP 14 $ 4.95 12597 Major Brands CD4007UBE IC CD4007 DUAL COMPLEMENTARY PAIR PLUS INVERTER DIP 14 $ 0.49 54623 Major Brands CD40098B IC CD40098B Hex Inverting 3-State Buffer DIP 16 $ 2.95 676481 Major Brands CD40103B IC CD40103B Counter IC Binary Counter 1 Element 8 Bit Positive Edge DIP 16 $ 1.29 2178996 Major Brands CD40104B IC CD40104B 4-Bit Bidirectional Universal Shift Register DIP 16 $ 1.95 893179 Major Brands CD40106BE IC CD40106BE CMOS Hex Schmitt Trigger DIP 14 $ 0.49 676502 Major Brands CD40110B IC CD40110 DECADE UP/DOWN COUNTER DIP 16 $ 1.49 12634 Major Brands CD4011B IC CD4011 QUAD 2-INPUT NAND GATE DIP 14 $ 0.49 675972 Major Brands CD4012B IC CD4012B Dual 4-Input NAND Gate DIP 14 $ 0.49 12677 Major Brands CD4013BE IC CD4013 DUAL D-TYPE FLIP-FLOp DIP 14 $ 0.49 2288823 Major Brands CD4014B IC CD4014B CMOS 8-Stage Static Shift Register(HD14014BP) DIP 16 $ 0.55 12706 Major Brands CD4015B IC CD4015 4-STAGE STATIC SHIFT REGISTER DIP 16 $ 0.55 2178988 Major Brands CD40163B IC CD40163B CMOS Synchronous Programmable 4-Bit Counter DIP 16 $ 0.39 12722 Major Brands CD4016B IC CD4016 DUAL QUAD BILATERAL SWITCH DIP 14 $ 0.49 12749 Major Brands CD4017B IC CD4017 CMOS Decade Counter 10 Decoded Outputs DIP 16 $ 0.49 12773 Major Brands CD4018B IC CD4018 PRESETTABLE DIVIDE-BY-N COUNTER DIP 16 $ 0.55 676537 Major Brands CD40193B IC CD40193B CMOS Presettable Up/Down Counter Binary Type DIP 16 $ 0.55 675999 Major Brands CD4019B IC CD4019B CMOS Quad AND/OR Select Gate DIP 16 $ 0.49 12802 Major Brands CD4020 IC CD4020 14-STAGE RIPPLE CARRY BINARY COUNTER DIP 16 $ 0.49 12829 Major Brands CD4021B IC CD4021 8-Stage Static Shift Register DIP 16 $ 0.49 54666 Major Brands CD4022 IC CD4022 CMOS Octal Counter with 8 Decoded Outputs DIP 16 $ 0.49 12845 Major Brands CD4023B IC CD4023 Triple 3-Input NAND Gates DIP 14 $ 0.49 12853 Major Brands CD4024 IC CD4024 7-STAGE RIPPLE CARRY BINARY COUNTER DIP 14 $ 0.49 676001 Major Brands CD4025B IC CD4025B Triple Input NOR Gate 3 Volt to 15 Volt DIP 14 $ 0.49 353560 Major Brands CD4026B IC CD4026 DECADE COUNTER/DIVIDER DIP 16 $ 0.49 12888 Major Brands CD4027B IC CD4027 DUAL J-K MASTER/SLAVE FLIP-FLOP DIP 16 $ 0.49 12909 Major Brands CD4028B IC CD4028 BCD to Decimal Decoder DIP 16 $ 0.49 12925 Major Brands CD4029B IC CD4029 UP/DOWN BINARY COUNTER DIP 16 $ 0.49 2288831 Major Brands CD4031B IC CD4031B CMOS 64-Stage Static Shift Register DIP 16 $ 1.29 2288839 Major Brands CD4033B IC CD4033B CMOS Decade Counter/Divider with Ripple Blanking DIP 16 $ 1.19 2288135 Major Brands CD4034BE IC CD4043B CMOS 8-Stage Static Bidirectional Parallel/Serial Input/Output Bus Register DIP 24 $ 3.95 12950 Major Brands CD4040B IC CD4040 12 Stage Binary Ripple Counter DIP 16 $ 0.49 676027 Major Brands CD4041UBE IC CD4041UB CMOS Quad True/Complement Buffer DIP 14 $ 1.09 Click Here to Request a Large Quantity Quote SEMICONDUCTORS: LOGIC CMOS 4000 SERIES Jameco Part# Manufacturer Manufacturer Part # Description Package Type Price 1 12992 Major Brands CD4043 IC CD4043 Quad Tri-State NOR R/S Latch DIP 16 $ 0.49 13004 Major Brands CD4044B IC CD4044 Quad NAND R-S Latch DIP 16 $ 0.49 13012 Major Brands CD4046B IC CD4046 MICROPOWER PHASE LOCK LOOP DIP 16 $ 0.49 13039 Major Brands CD4047B IC CD4047 MONOSTABLE MULTIVIBRATOR DIP 14 $ 0.55 13055 Major Brands CD4049 IC CD4049 HEX INVERTING BUFFER/CONVERTER DIP 16 $ 0.49 13071 Major Brands CD4050B IC CD4050B HEX NON-INVERTING BUFFER/CONVERTER DIP 16 $ 0.49 13098 Major Brands CD4051B IC CD4051 SINGLE 8-CH ANALOG MULTIPLEXER DIP 16 $ 0.55 894391 MAJOR Brands CD4051BE IC CD4051BE 8-Channel Multiplexer DIP 16 $ 0.59 13119 Major Brands CD4052B IC CD4052 DUAL 4-CHANNEL ANALOG MULTIPLEXER DIP 16 $ 0.49 13127 Major Brands CD4053B IC CD4053 Triple 2-Channel Analog Multiplexer DIP 16 $ 0.49 13151 Major Brands CD4060B IC CD4060 14-STAGE RIPPLE-CARRY BINARY COUNTER/DIVIDER DIP 16 $ 0.49 13186 Major Brands CD4066B IC CD4066 QUAD BILATERAL SWITCH DIP 14 $ 0.45 13215 Major Brands CD4067B IC CD4067 SINGLE 16-CHANNEL ANALOG MULTIPLEXER DIP 24 $ 4.95 676060 Major Brands CD4068B IC CD4068B CMOS 8-Input NAND and AND Gate DIP 14 $ 0.49 13231 Major Brands CD4069 IC CD4069 HEX INVERTER DIP 14 $ 0.59 894761 National Semiconductor CD4069UBE IC CD4069UBE CMOS HEX INVERTER,UNBUFFERED DIP 16 $ 0.49 13258 Major Brands CD4070B IC CD4070 QUAD 2-INPUT EXCLUSIVE OR GATE DIP 14 $ 0.49 13274 Major Brands CD4071B IC CD4071 QUAD 2-INPUT OR GATE DIP 14 $ 0.49 676078 Major Brands CD4072B IC CD4072 DUAL 4-INPUT OR GATE DIP 14 $ 0.49 676086 Major Brands CD4073B IC CD4073 Triple 3-Input AND Gate DIP 14 $ 0.49 676094 Major Brands CD4075B IC CD4075 Triple 3-Input OR Gate DIP 14 $ 0.49 676107 Major Brands CD4077B IC CD4077 QUAD EXCLUSIVE-NOR GATE CMOS DIP 14 $ 0.49 676115 Major Brands CD4078B IC CD4078B CMOS 8-Input NOR/OR Gate DIP 14 $ 0.49 13354 Major Brands CD4081B IC CD4081 QUAD 2-INPUT AND GATE DIP 14 $ 0.49 676123 Major Brands CD4082B IC CD4082 DUAL 4-INPUT AND GATE DIP 14 $ 0.49 13397 Major Brands CD4086B IC CD4086B 2-Input AND-OR-Invert Gate 20 Volt DIP 14 $ 1.49 13400 Major Brands CD4093B IC CD4093 QUAD 2-INPUT NAND SCHMITT-TRIG DIP 14 $ 0.49 13426 Major Brands CD4094B IC CD4094 8-Bit Shift Register Latch DIP 16 $ 0.49 13442 Major Brands CD4099B IC CD4099B 8-Bit Addressable D-Type Latch Low Level DIP 16 $ 0.49 13469 Major Brands CD4503B IC CD4503 CMOS Hex Non-Inverting Buffer with 3-State Outputs DIP 16 $ 0.49 2287287 Motorola CD4508B IC CD4508B Dual 4-Bit CMOS Latch DIP 24 $ 3.95 13485 Major Brands CD4510B IC CD4510 BCD Presettable Up Down Counter DIP 16 $ 0.49 13493 Major Brands CD4511B IC CD4511 BCD-to-7-Segment Latch Decoder Driver DIP 16 $ 0.49 13522 Major Brands CD4514B IC CD4514B 4-Bit Latch Line Decoder DIP 24 $ 6.95 2290471 Major Brands CD4515B IC CD4515B 4-Bit Transparent Latch and 4-to-16 Line Decoder DIP 24 $ 1.95 13549 Major Brands CD4516B IC CD4516 BINARY UP/DOWN COUNTER DIP 16 $ 0.55 Click Here to Request a Large Quantity Quote SEMICONDUCTORS: LOGIC CMOS 4000 SERIES Jameco Part# Manufacturer Manufacturer Part # Description Package Type Price 1 13565 Major Brands CD4518B IC CD4518 DUAL BCD UP COUNTER DIP 16 $ 0.55 2179008 Major Brands CD4519B IC CD4519B Logic MUX 2-INOUT DIP 16 $ 1.95 13581 Major Brands CD4520B IC CD4520 DUAL BINARY UP COUNTER DIP 16 $ 0.55 676422 Major Brands CD4527B IC CD4527B CMOS BCD Rate Multiplier DIP 16 $ 0.69 13611 Major Brands CD4528B IC CD4528 DUAL MONOSTABLE MULTIVIBRATOR DIP 16 $ 1.95 2288847 Major Brands CD4529B IC CD4529B 8-Channel Analog Data Selector DIP 16 $ 3.95 676431 Major Brands CD4532BP IC CD4532B CMOS 8-Bit Priority Encoder DIP 16 $ 0.55 13653 Major Brands CD4538B IC CD14538B DUAL MONOSTABLE MULTIVIBRATOR(MC14538CP) DIP 16 $ 2.25 13696 Major Brands CD4543B IC CD4543 BCD-to-7-Segment Decoder Driver DIP 16 $ 0.49 2288855 Motorola CD4549B IC CD4549B Successive Approximation Registers DIP 16 $ 6.95 354618 Major Brands CD4556BP IC CD4556B Dual 1 to 4 Decoder/Demultiplexer DIP 16 $ 0.55 13768 Major Brands CD4584B IC CD4584 HEX SCHMITT TRIGGER DIP 14 $ 1.49 2290487 Major Brands CD4724BE IC CD4724B CMOS 8-Bit Addressable Latch DIP 16 $ 1.25 2178970 Major Brands MC14174BCP IC CD14174B HEX D-type Flip-Flop 3-18VDC 10mA DIP 16 $ 0.79 2288191 National Semiconductor MM80C97N IC MM80C97N 3-State Hex Buffer Non-Inverting DIP 16 $ 1.95 .
Load more

Recommended publications
  • Engineering Transcriptional Control and Synthetic Gene Circuits in Cell Free Systems
    University of Tennessee, Knoxville TRACE: Tennessee Research and Creative Exchange Doctoral Dissertations Graduate School 12-2012 Engineering Transcriptional Control and Synthetic Gene Circuits in Cell Free systems Sukanya Iyer University of Tennessee, [email protected] Follow this and additional works at: https://trace.tennessee.edu/utk_graddiss Part of the Biotechnology Commons Recommended Citation Iyer, Sukanya, "Engineering Transcriptional Control and Synthetic Gene Circuits in Cell Free systems. " PhD diss., University of Tennessee, 2012. https://trace.tennessee.edu/utk_graddiss/1586 This Dissertation is brought to you for free and open access by the Graduate School at TRACE: Tennessee Research and Creative Exchange. It has been accepted for inclusion in Doctoral Dissertations by an authorized administrator of TRACE: Tennessee Research and Creative Exchange. For more information, please contact [email protected]. To the Graduate Council: I am submitting herewith a dissertation written by Sukanya Iyer entitled "Engineering Transcriptional Control and Synthetic Gene Circuits in Cell Free systems." I have examined the final electronic copy of this dissertation for form and content and recommend that it be accepted in partial fulfillment of the equirr ements for the degree of Doctor of Philosophy, with a major in Life Sciences. Mitchel J. Doktycz, Major Professor We have read this dissertation and recommend its acceptance: Michael L. Simpson, Albrecht G. von Arnim, Barry D. Bruce, Jennifer L. Morrell-Falvey Accepted for the Council: Carolyn R. Hodges Vice Provost and Dean of the Graduate School (Original signatures are on file with official studentecor r ds.) Engineering Transcriptional Control and Synthetic Gene Circuits in Cell Free systems A Dissertation Presented for the Doctor of Philosophy Degree The University of Tennessee, Knoxville Sukanya Iyer December 2012 Copyright © 2012 by Sukanya Iyer.
    [Show full text]
  • CSE Yet, Please Do Well! Logical Connectives
    administrivia Course web: http://www.cs.washington.edu/311 Office hours: 12 office hours each week Me/James: MW 10:30-11:30/2:30-3:30pm or by appointment TA Section: Start next week Call me: Shayan Don’t: Actually call me. Homework #1: Will be posted today, due next Friday by midnight (Oct 9th) Gradescope! (stay tuned) Extra credit: Not required to get a 4.0. Counts separately. In total, may raise grade by ~0.1 Don’t be shy (raise your hand in the back)! Do space out your participation. If you are not CSE yet, please do well! logical connectives p q p q p p T T T T F T F F F T F T F NOT F F F AND p q p q p q p q T T T T T F T F T T F T F T T F T T F F F F F F OR XOR 푝 → 푞 • “If p, then q” is a promise: p q p q F F T • Whenever p is true, then q is true F T T • Ask “has the promise been broken” T F F T T T If it’s raining, then I have my umbrella. related implications • Implication: p q • Converse: q p • Contrapositive: q p • Inverse: p q How do these relate to each other? How to see this? 푝 ↔ 푞 • p iff q • p is equivalent to q • p implies q and q implies p p q p q Let’s think about fruits A fruit is an apple only if it is either red or green and a fruit is not red and green.
    [Show full text]
  • Transistors and Logic Gates
    Introduction to Computer Engineering CS/ECE 252, Spring 2013 Prof. Mark D. Hill Computer Sciences Department University of Wisconsin – Madison Chapter 3 Digital Logic Structures Slides based on set prepared by Gregory T. Byrd, North Carolina State University Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Transistor: Building Block of Computers Microprocessors contain millions of transistors • Intel Pentium II: 7 million • Compaq Alpha 21264: 15 million • Intel Pentium III: 28 million Logically, each transistor acts as a switch Combined to implement logic functions • AND, OR, NOT Combined to build higher-level structures • Adder, multiplexer, decoder, register, … Combined to build processor • LC-3 3-3 Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Simple Switch Circuit Switch open: • No current through circuit • Light is off • Vout is +2.9V Switch closed: • Short circuit across switch • Current flows • Light is on • Vout is 0V Switch-based circuits can easily represent two states: on/off, open/closed, voltage/no voltage. 3-4 Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. N-type MOS Transistor MOS = Metal Oxide Semiconductor • two types: N-type and P-type N-type • when Gate has positive voltage, short circuit between #1 and #2 (switch closed) • when Gate has zero voltage, open circuit between #1 and #2 Gate = 1 (switch open) Gate = 0 Terminal #2 must be connected to GND (0V). 3-5 Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. P-type MOS Transistor P-type is complementary to N-type • when Gate has positive voltage, open circuit between #1 and #2 (switch open) • when Gate has zero voltage, short circuit between #1 and #2 (switch closed) Gate = 1 Gate = 0 Terminal #1 must be connected to +2.9V.
    [Show full text]
  • Efficient Design of 2'S Complement Adder/Subtractor Using QCA
    International Journal of Engineering Research & Technology (IJERT) ISSN: 2278-0181 Vol. 2 Issue 11, November - 2013 Efficient Design of 2'S complement Adder/Subtractor Using QCA. D.Ajitha 1 Dr.K.Venkata Ramanaiah 3 , Assistant Professor, Dept of ECE, Associate Professor, ECE Dept , S.I.T.A.M..S., Chittoor, Y S R Engineering college of Yogi Vemana A.P. India. University, Proddatur. 2 4 P.Yugesh Kumar, Dr.V.Sumalatha , SITAMS,Chittoor, Associate Professor, Dept of ECE, J.N.T.U.C.E.A Ananthapur, A.P. Abstract: The alternate digital design of In this paper efficient 1-bit full adder [10] has CMOS Technology fulfilled with the Quantum taken to implement the above circuit by comparing with previous 1-bit full adder designs [7-9]. A full adder with Dot Cellular Automata. In this paper, the 2’s reduced one inverter is used and implemented with less complement adder design with overflow was number of cells. Latency and power consumption is also implemented as first time in QCA & have the reduced with the help of optimization process [5]. smallest area with the least number of cells, Therefore efficient two‟s complement adder is also reduced latency and low cost achieved with designed using the efficient 1-bit full adder [10] and reduced all the parameters like area delay and cost one inverter reduced full adder using majority compared with CMOS [14]. logic. The circuit was simulated with QCADesigner and results were included in The paper is organized as follows: In Section 2, this paper. QCA basics and design methods to implement gates functionalities is presented.
    [Show full text]
  • Negation-Limited Complexity of Parity and Inverters
    数理解析研究所講究録 第 1554 巻 2007 年 131-138 131 Negation-Limited Complexity of Parity and Inverters 森住大樹 1 垂井淳 2 岩間一雄 1 1 京都大学大学院情報学研究科, {morizumi, iwama}@kuis.kyoto-u.ac.jp 2 電気通信大学情報通信工学科, [email protected] Abstract 1 Introduction and Summary In negation-limited complexity, one considers circuits Although exponential lower bounds are known for the with a limited number of NOT gates, being mo- monotone circuit size [4], [6], at present we cannot tivated by the gap in our understanding of mono- prove a superlinear lower bound for the size of circuits tone versus general circuit complexity, and hop- computing an explicit Boolean function: the largest ing to better understand the power of NOT gates. known lower bound is $5n-o(n)[\eta, |10],$ $[8]$ . It is We give improved lower bounds for the size (the natural to ask: What happens if we allow a limited number of $AND/OR/NOT$) of negation-limited cir- number of NOT gatae? The hope is that by the study cuits computing Parity and for the size of negation- of negation-limited complexity of Boolean functions limited inverters. An inverter is a circuit with inputs under various scenarios [3], [17], [15]. [2], $|1$ ], $[13]$ , we $x_{1},$ $\ldots,x_{\mathfrak{n}}$ $\neg x_{1},$ $po\mathfrak{n}^{r}er$ and outputs $\ldots,$ $\neg x_{n}$ . We show that understand the of NOT gates better. (a) For $n=2^{f}-1$ , circuits computing Parity with $r-1$ We consider circuits consisting of $AND/OR/NOT$ NOT gates have size at least $6n-\log_{2}(n+1)-O(1)$, gates.
    [Show full text]
  • Universal Gate - NAND Digital Electronics 2.2 Intro to NAND & NOR Logic
    Universal Gate - NAND Digital Electronics 2.2 Intro to NAND & NOR Logic Universal Gate – NAND This presentation will demonstrate • The basic function of the NAND gate. • How a NAND gate can be used to replace an AND gate, an OR gate, or an INVERTER gate. • How a logic circuit implemented with AOI logic gates can Universal Gate – NAND be re-implemented using only NAND gates. • That using a single gate type, in this case NAND, will reduce the number of integrated circuits (IC) required to implement a logic circuit. Digital Electronics AOI Logic NAND Logic 2 More ICs = More $$ Less ICs = Less $$ NAND Gate NAND Gate as an Inverter Gate X X X (Before Bubble) X Z X Y X Y X Z X Y X Y Z X Z 0 0 1 0 1 Equivalent to Inverter 0 1 1 1 0 1 0 1 1 1 0 3 4 Project Lead The Way, Inc Copyright 2009 1 Universal Gate - NAND Digital Electronics 2.2 Intro to NAND & NOR Logic NAND Gate as an AND Gate NAND Gate as an OR Gate X X Y Y X X Z X Y X Y Y Z X Y X Y X Y Y NAND Gate Inverter Inverters NAND Gate X Y Z X Y Z 0 0 0 0 0 0 0 1 0 0 1 1 Equivalent to AND Gate Equivalent to OR Gate 1 0 0 1 0 1 1 1 1 1 1 1 5 6 NAND Gate Equivalent to AOI Gates Process for NAND Implementation 1.
    [Show full text]
  • EE 434 Lecture 2
    EE 330 Lecture 6 • PU and PD Networks • Complex Logic Gates • Pass Transistor Logic • Improved Switch-Level Model • Propagation Delay Review from Last Time MOS Transistor Qualitative Discussion of n-channel Operation Source Gate Drain Drain Bulk Gate n-channel MOSFET Source Equivalent Circuit for n-channel MOSFET D D • Source assumed connected to (or close to) ground • VGS=0 denoted as Boolean gate voltage G=0 G = 0 G = 1 • VGS=VDD denoted as Boolean gate voltage G=1 • Boolean G is relative to ground potential S S This is the first model we have for the n-channel MOSFET ! Ideal switch-level model Review from Last Time MOS Transistor Qualitative Discussion of p-channel Operation Source Gate Drain Drain Bulk Gate Source p-channel MOSFET Equivalent Circuit for p-channel MOSFET D D • Source assumed connected to (or close to) positive G = 0 G = 1 VDD • VGS=0 denoted as Boolean gate voltage G=1 • VGS= -VDD denoted as Boolean gate voltage G=0 S S • Boolean G is relative to ground potential This is the first model we have for the p-channel MOSFET ! Review from Last Time Logic Circuits VDD Truth Table A B A B 0 1 1 0 Inverter Review from Last Time Logic Circuits VDD Truth Table A B C 0 0 1 0 1 0 A C 1 0 0 B 1 1 0 NOR Gate Review from Last Time Logic Circuits VDD Truth Table A B C A C 0 0 1 B 0 1 1 1 0 1 1 1 0 NAND Gate Logic Circuits Approach can be extended to arbitrary number of inputs n-input NOR n-input NAND gate gate VDD VDD A1 A1 A2 An A2 F A1 An F A2 A1 A2 An An A1 A 1 A2 F A2 F An An Complete Logic Family Family of n-input NOR gates forms
    [Show full text]
  • Digital IC Listing
    BELS Digital IC Report Package BELS Unit PartName Type Location ID # Price Type CMOS 74HC00, Quad 2-Input NAND Gate DIP-14 3 - A 500 0.24 74HCT00, Quad 2-Input NAND Gate DIP-14 3 - A 501 0.36 74HC02, Quad 2 Input NOR DIP-14 3 - A 417 0.24 74HC04, Hex Inverter, buffered DIP-14 3 - A 418 0.24 74HC04, Hex Inverter (buffered) DIP-14 3 - A 511 0.24 74HCT04, Hex Inverter (Open Collector) DIP-14 3 - A 512 0.36 74HC08, Quad 2 Input AND Gate DIP-14 3 - A 408 0.24 74HC10, Triple 3-Input NAND DIP-14 3 - A 419 0.31 74HC32, Quad OR DIP-14 3 - B 409 0.24 74HC32, Quad 2-Input OR Gates DIP-14 3 - B 543 0.24 74HC138, 3-line to 8-line decoder / demultiplexer DIP-16 3 - C 603 1.05 74HCT139, Dual 2-line to 4-line decoders / demultiplexers DIP-16 3 - C 605 0.86 74HC154, 4-16 line decoder/demulitplexer, 0.3 wide DIP - Small none 445 1.49 74HC154W, 4-16 line decoder/demultiplexer, 0.6wide DIP none 446 1.86 74HC190, Synchronous 4-Bit Up/Down Decade and Binary Counters DIP-16 3 - D 637 74HCT240, Octal Buffers and Line Drivers w/ 3-State outputs DIP-20 3 - D 643 1.04 74HC244, Octal Buffers And Line Drivers w/ 3-State outputs DIP-20 3 - D 647 1.43 74HCT245, Octal Bus Transceivers w/ 3-State outputs DIP-20 3 - D 649 1.13 74HCT273, Octal D-Type Flip-Flops w/ Clear DIP-20 3 - D 658 1.35 74HCT373, Octal Transparent D-Type Latches w/ 3-State outputs DIP-20 3 - E 666 1.35 74HCT377, Octal D-Type Flip-Flops w/ Clock Enable DIP-20 3 - E 669 1.50 74HCT573, Octal Transparent D-Type Latches w/ 3-State outputs DIP-20 3 - E 674 0.88 Type CMOS CD4000 Series CD4001, Quad 2-input
    [Show full text]
  • The Equation for the 3-Input XOR Gate Is Derived As Follows
    The equation for the 3-input XOR gate is derived as follows The last four product terms in the above derivation are the four 1-minterms in the 3-input XOR truth table. For 3 or more inputs, the XOR gate has a value of 1when there is an odd number of 1’s in the inputs, otherwise, it is a 0. Notice also that the truth tables for the 3-input XOR and XNOR gates are identical. It turns out that for an even number of inputs, XOR is the inverse of XNOR, but for an odd number of inputs, XOR is equal to XNOR. All these gates can be interconnected together to form large complex circuits which we call networks. These networks can be described graphically using circuit diagrams, with Boolean expressions or with truth tables. 3.2 Describing Logic Circuits Algebraically Any logic circuit, no matter how complex, may be completely described using the Boolean operations previously defined, because of the OR gate, AND gate, and NOT circuit are the basic building blocks of digital systems. For example consider the circuit shown in Figure 1.3(c). The circuit has three inputs, A, B, and C, and a single output, x. Utilizing the Boolean expression for each gate, we can easily determine the expression for the output. The expression for the AND gate output is written A B. This AND output is connected as an input to the OR gate along with C, another input. The OR gate operates on its inputs such that its output is the OR sum of the inputs.
    [Show full text]
  • Additional Gates and Circuits, Other Gate Types, Exclusive-OR Operator and Gates, High-Impedance Outputs 5
    Introduction to Digital Logic Course Outline 1. Digital Computers, Number Systems, Arithmetic Operations, Decimal, Alphanumeric, and Gray Codes 2. Binary Logic, Gates, Boolean Algebra, Standard Forms 3. Circuit Optimization, Two-Level Optimization, Map Manipulation, Multi-Level Prof. Nizamettin AYDIN Circuit Optimization 4. Additional Gates and Circuits, Other Gate Types, Exclusive-OR Operator and Gates, High-Impedance Outputs 5. Implementation Technology and Logic Design, Design Concepts and Automation, The Design Space, Design Procedure, The major design steps [email protected] 6. Programmable Implementation Technologies: Read-Only Memories, Programmable Logic Arrays, Programmable Array Logic,Technology mapping to programmable [email protected] logic devices 7. Combinational Functions and Circuits 8. Arithmetic Functions and Circuits 9. Sequential Circuits Storage Elements and Sequential Circuit Analysis 10. Sequential Circuits, Sequential Circuit Design State Diagrams, State Tables 11. Counters, register cells, buses, & serial operations 12. Sequencing and Control, Datapath and Control, Algorithmic State Machines (ASM) 13. Memory Basics 1 2 Introduction to Digital Logic Other Gate Types • Why? – Implementation feasibility and low cost – Power in implementing Boolean functions Lecture 4 – Convenient conceptual representation Additional Gates and Circuits • Gate classifications – Primitive gate - a gate that can be described using a single – Other Gate Types primitive operation type (AND or OR) plus an optional – Exclusive -OR Operator and Gates inversion(s). – High -Impedance Outputs – Complex gate - a gate that requires more than one primitive operation type for its description • Primitive gates will be covered first 3 4 Buffer NAND Gate • A buffer is a gate with the function F = X: • The basic NAND gate has the following symbol, illustrated for three inputs: XF – AND-Invert (NAND) • In terms of Boolean function, a buffer is the X Y (F X, ,Y Z) === X ⋅⋅⋅ Y ⋅⋅⋅ Z same as a connection! Z • So why use it? • NAND represents NOT AND , i.
    [Show full text]
  • Static CMOS Circuits
    Static CMOS Circuits • Conventional (ratio-less) static CMOS – Covered so far • Ratio-ed logic (depletion load, pseudo nMOS) • Pass transistor logic ECE 261 Krish Chakrabarty 1 Example 1 module mux(input s, d0, d1, output y); assign y = s ? d1 : d0; endmodule 1) Sketch a design using AND, OR, and NOT gates. ECE 261 Krish Chakrabarty 2 1 Example 1 module mux(input s, d0, d1, output y); assign y = s ? d1 : d0; endmodule 1) Sketch a design using AND, OR, and NOT gates. ECE 261 Krish Chakrabarty 3 Example 2 2) Sketch a design using NAND, NOR, and NOT gates. Assume ~S is available. ECE 261 Krish Chakrabarty 4 2 Example 2 2) Sketch a design using NAND, NOR, and NOT gates. Assume ~S is available. ECE 261 Krish Chakrabarty 5 Bubble Pushing • Start with network of AND / OR gates • Convert to NAND / NOR + inverters • Push bubbles around to simplify logic – Remember DeMorgan’s Law ECE 261 Krish Chakrabarty 6 3 Example 3 3) Sketch a design using one compound gate and one NOT gate. Assume ~S is available. ECE 261 Krish Chakrabarty 7 Example 3 3) Sketch a design using one compound gate and one NOT gate. Assume ~S is available. ECE 261 Krish Chakrabarty 8 4 Compound Gates • Logical Effort of compound gates ECE 261 Krish Chakrabarty 9 Example 4 • The multiplexer has a maximum input capacitance of 16 units on each input. It must drive a load of 160 units. Estimate the delay of the NAND and compound gate designs. H = 160 / 16 = 10 B = 1 N = 2 ECE 261 Krish Chakrabarty 10 5 NAND Solution ECE 261 Krish Chakrabarty 11 NAND Solution ECE 261 Krish Chakrabarty 12 6 Compound Solution ECE 261 Krish Chakrabarty 13 Compound Solution ECE 261 Krish Chakrabarty 14 7 Example 5 • Annotate your designs with transistor sizes that achieve this delay.
    [Show full text]
  • Design a 3-Input CMOS NAND Gate (PUN/PDN) with Fan-Out of 3. Total Output Load of the NAND Gate Is Equal to 15Ff and Μn/Μp = 2.5
    Tutorial on Transistor Sizing Problem #1 (Static CMOS logic): Design a 3-input CMOS NAND gate (PUN/PDN) with fan-out of 3. Total output load of the NAND gate is equal to 15fF and µn/µp = 2.5. For 0.35µm process technology tox = -9 -12 7.6*10 m, εox = 35*10 F/m. Compare the above design with that of a 3-input NOR (PUN/PDN) gate. State any benefits of one implementation over the other. For the sake of simplicity assume all capacitance is lumped and gate capacitance neglecting diffusion and wiring capacitance. Solution: Cox = εoxWL/ tox = 15fF. So W = 9.2µm. Leff = 0.35µm. Assuming output load is all gate capacitance. This is a simplifying assumption made for this problem. A more realistic approach would be to calculate the diffusion and wiring capacitances as well. Equivalent inverter for fan-out of 3 and µn/µp = 2.5 would result in: A B C 2.23 2.23 2.23 Wp = 2.5*Wn for equal rise and fall times. Also, Wp + Wn = 9.2/3 = 3.16µm for fan-out of 3. A 2.67 B Solving the above equations we have, 2.67 C 2.67 Wp = 2.23µm and Wn = 0.89µm. NAND implementation: NAND implementation Therefore, for the 3-ip NAND gate implementation, each PDN n-MOS transistor will be: 3*0.89µm = 2.67µm A and each p-MOS transistor in the PUN network will be: 2.23µm 6.69 B NOR implementation: 6.69 For a 3-ip NOR gate implementation, each PDN n-MOS transistor C will be: 0.89µm 6.69 A BC Each PUN p-MOS transistor will be 3*2.23µm = 6.69µm 0.89 0.89 0.89 Area comparison: NOR implementation Total gate area of NAND gate is: 3*(2.67+2.23)µm = 14.7µm Total gate area of NOR gate is: 3*(6.69+0.89) µm = 22.7µm Thus we infer that the NAND gate has less area and power compared to the NOR gate for identical loading and fan-out conditions and is the preferred implementation.
    [Show full text]