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Chapter 4 Calculating the Logical Effort of Gates Chapter 4 Calculating the Logical Effort of Gates The simplicity of the theory of logical effort follows from assigning to each kind of logic gate a number—its logical effort—that describes its drive capability relative to that of a reference inverter. The logical effort is independent of the actual size of the logic gate, allowing one to postpone detailed calculations of transistor sizes until after the logical effort analysis is complete. Each logic gate is characterized by two quantities: its logical effort and its parasitic delay. These parameters may be determined in three ways: Using a few process parameters, one can estimate logical effort and parasitic delay as described in this chapter. The results are sufficiently accurate for most design work. Using test circuit simulations, the logical effort and parasitic delay can be simulated for various logic gates. This technique is explained in Chapter 5. Using fabricated test structures, logical effort and parasitic delay can be physically measured. Before turning to methods of calculating logical effort, we present a discussion of different definitions and interpretations of logical effort. While these are all equivalent, in some sense, each offers a different perspective to the design task and each leads to different intuitions. 0 Copyright c 1998, Morgan Kaufmann Publishers, Inc. This material may not be copied or distributed without permission of the publisher. 59 60 CHAPTER 4. CALCULATING THE LOGICAL EFFORT OF GATES 4.1 Definitions of logical effort Logical effort captures enough information about a logic gate’s topology—the network of transistors that connect the gate’s output to the power supply and to ground—to determine the delay of the logic gate. In this section, we give three equivalent concrete definitions of logical effort. Definition 4.1 The logical effort of a logic gate is defined as the number of times worse it is at delivering output current than would be an inverter with identical input capacitance. Any topology required to perform logic makes a logic gate less able to deliver output current than an inverter with identical input capacitance. For one thing, a logic gate must have more transistors than an inverter, and so to maintain equal input capacitance, its transistors must be narrower on average and thus less able to conduct current than those of an inverter with identical input capacitance. If its topology requires transistors in parallel, a conservative estimate of its performance will assume that not all of them conduct at once, and therefore that they will not deliver as much current as could an inverter with identical input capacitance. If its topology requires transistors in series, it cannot possibly deliver as much current as could an inverter with identical input capacitance. Whatever the topology of a simple logic gate, its ability to deliver output current must be worse than an inverter with identical input capacitance. Logical effort is a measure of how much worse. Definition 4.2 The logical effort of a logic gate is defined as the ratio of its input capacitance to that of an inverter that delivers equal output current. This alternative definition is useful for computing the logical effort of a par- ticular topology. To compute the logical effort of a logic gate, pick transistor sizes for it that make it as good at delivering output current as a standard inverter, and then tally up the input capacitance of each input signal. The ratio of this input capacitance to that of the standard inverter is the logical effort of that input to the logic gate. The logical effort of a logic gate will depend slightly on the mobilitiy ratio in the fabrication process used to build it. These calculations are shown in detail later in this chapter. Definition 4.3 The logical effort of a logic gate is defined as the slope of the gate’s delay vs. fanout curve divided by the slope of an inverter’s delay vs. fanout curve. 4.2. GROUPING INPUT SIGNALS 61 This alternative definition suggests an easy way to measure the logical effort of any particular logic gate by experiements with real or simulated circuits of various fanouts. 4.2 Grouping input signals Because logical effort relates the input capacitance to the output drive current available, a natural question arises: for a logic gate with multiple inputs, how many of the input signals should we consider when computing logical effort? It is useful to define several kinds of logical effort, depending on how input signals are grouped. In each case, we define an input group to contain the input signals that are relevant to the computation of logical effort: Logical effort per input, in which logical effort measures the effectiveness of a single input in controlling output current. The input group is the single input in question. All of the discussion in preceding chapters uses logical effort per input. Logical effort of a bundle, a group of related inputs. For example, a mul- tiplexer requires true and complement select signals; this pair might be grouped into a bundle. Because bundles of complementary pairs of signals occur frequently in CMOS circuits, we adopt a special notation: s stands s for a bundle containing the true signal s and the complement signal .The input group of a bundle contains all the signals in the bundle. Total logical effort, the logical effort of all inputs taken together. The input group contains all the input signals of the logic gate. Terminology and context determine which kind of logical effort applies. The adjective “total” is always used when total logical effort is meant, while the other two cases are distinguished by the signals associated with them in context. “The total logical effort of a 2-input NAND gate” is the logical effort of both inputs taken together, while “the logical effort of a 2-input NAND gate” is the logical effort per input of one of its two inputs. The logical effort of an input group is defined analogously to the logical effort per input, shown in the previous section. The analog of Definition 4.2 is: the g b logical effort b of an input group is just P C C b i b g = = b (4.1) C C inv inv 62 CHAPTER 4. CALCULATING THE LOGICAL EFFORT OF GATES C b where b is the combined input capacitance of every signal in the input group , C and inv is the input capacitance of an inverter designed to have the same drive capabilities as the logic gate whose logical effort we are calculating. A consequence of Equation 4.1 is that the logical efforts associated with input groups sum in a straightforward way. The total logical effort is the sum of the log- ical effort per input of every input to the logic gate. The logical effort of a bundle is the sum of the logical effort per input of every signal in the bundle. Thus a logic gate can be viewed as having a certain total logical effort that can be allocated to its inputs according to their contribution to the gate’s input capacitance. 4.3 Calculating logical effort Definition 4.2 provides a convenient method for calculating the logical effort of a logic gate. We have but to design a gate that has the same current drive character- istics as a reference inverter, calculate the input capacitances of each signal, and apply Equation 4.1 to obtain the logical effort. Because we compute the logical effort as a ratio of capacitances, the units we use to measure capacitance may be arbitrary. This observation simplifies the cal- culations enormously. First, assume that all transistors are of minimum length, so that a transistor’s size is completely captured by its width, w . The capacitance of the transistor’s gate is proportional to w and its ability to produce output cur- rent, or conductance, is also proportional to w . In most CMOS processes, pullup transistors must be wider than pulldown transistors to have the same conductance. = = p n is the ratio of PMOS to NMOS width in an inverter for equal conduc- tance. is the actual ratio of PMOS to NMOS width in an inverter. For simplicity, = = 2 we will often assume that . Under this assumption, an inverter will 2w have a pulldown transistor of width w and a pullup transistor of width ,as w shown in Figure 4.1a, so the total input capacitance can be said to be 3 .Inthis chapter, we will also find general expressions for logical effort as a function of . 6= In Chapter 9, we will consider the benefits of choosing . Let us now design a 2-input NAND gate so that it has the same drive char- acteristics as an inverter with a pulldown of width 1 and a pullup of width 2. Figure 4.1b shows such a NAND gate. Because the two pulldown transistors of the NAND gate are in series, each must have twice the conductance of the inverter pulldown transistor so that the series connection has a conductance equal to that of the inverter pulldown transistor. Therefore, these transistors are twice as wide as the inverter pulldown transistor. This reasoning assumes that transistors in series 4.3. CALCULATING LOGICAL EFFORT 63 a 2 4 b 2 2 x x 4 x a 1 2 a 1 2 b 1 (a)(b)(c) Figure 4.1: Simple gates. (a) The reference inverter. (b) A two-input NAND gate. (c) A two-input NOR gate. obey Ohm’s law for resistors in series. By contrast, each of the two pullup tran- sistors in parallel need be only as large as the inverter pullup transistor to achieve the same drive as the reference inverter.
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