Elementary Logic Gates

Name Inverter AND Gate OR Gate (NOT Gate) A A AZ Z Z Symbol B B

A B Z A B Z Truth A Z 0 0 0 0 0 0 Table 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 1 1 1 1 1 1 Logic Z = A’ = A Z = A • B = AB Z = A + B Equation

C. E. Stroud Combinational Logic Design (1/06) 1 Other Elementary Logic Gates NAND Gate NOR Gate (NOT AND) Name (NOT OR) A Z A Z B B A A Z Symbol Z B B

A B Z A B Z 0 0 1 Truth Table 0 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 1 0 1 1 0 Z = (A • B)’ = ABLogic Equation Z = (A + B)’ = A+B

C. E. Stroud Combinational Logic Design (1/06) 2 Using Truth Tables to Prove Theorems • DeMorgan’s Theorems T8a: (X+Y)’ = X’•Y’ T8b: (X•Y)’ = X’+Y’

X Y Z X Y Z a NOR gate is a NAND gate is equivalent to 0 0 1 equivalent to 0 0 1 an AND gate 0 1 0 an OR gate 0 1 1 with inverted 1 0 0 with inverted 1 0 1 inputs inputs 1 1 0 1 1 0 X X X X Z Z Y ⇔ Z Y ⇔ Z Y Y NOR NAND X X Z alternate Z NOR Y NAND Y logic symbols C. E. Stroud Combinational Logic Design (1/06) 3 Other Logic Gates Name Buffer Exclusive-OR Gate Exclusive-NOR Gate aka XOR Gate aka XNOR or NXOR Gate A A AZ Z Z Symbol B B

A B Z A B Z Truth A Z 0 0 0 0 0 1 Table 0 0 0 1 1 0 1 0 1 1 1 0 1 1 0 0 1 1 0 1 1 1 Logic Z = A Z = A⊕B = AB + AB Z = A⊕B = A B + AB Equation also denoted Z = A B

C. E. Stroud Combinational Logic Design (1/06) 4 Interesting Properties of Exclusive-OR • Controlled inverter ¾ X⊕0=X ¾ X⊕1=X’ • XOR with one input inverted = XNOR ¾ X⊕Y’=X’⊕Y=(X⊕Y)’ • XNOR with one input inverted = XOR ¾ (X⊕Y’)’=(X’⊕Y)’=X⊕Y • Constant output ¾ X⊕X=0 ¾ X⊕X’=1

C. E. Stroud Combinational Logic Design (1/06) 5 Exclusive-OR Implementations A’ • Z=A’B+AB’ A A’B • XOR & XNOR not considered 5 gates Z elementary logic gates by many designers B B’ AB’ (A(AB)’)’ A 4 gates A (A+B)’ (AB)’ Z 3 gates Z (B(AB)’)’ B B AB Z=((A(AB)’)’(B(AB)’)’)’ Z=((A+B)’+AB)’ = A+B+AB = A AB • B AB = A AB + B AB = (A+B)•AB = (A+B)(A+B) = A(A+B) + B(A+B) = AA’+AB’+A’B+BB’ = AA’+AB’+A’B+BB’=AB’+A’B = 0+AB’+A’B+0 = AB’+A’B C. E. Stroud Combinational Logic Design (1/06) 6 Functionally Complete Set of Gates

• If any digital circuit can be built from a set of gates, that set is said to be functionally complete • Functionally complete sets of gates: ¾ AND, OR, & NOT ¾ NAND ¾ NOR ¾ Multiplexers • To show a set of gates is functionally complete, we must show that you can construct AND, OR and NOT functions

C. E. Stroud Combinational Logic Design (1/06) 7 Functionally Complete Set of Gates • The NAND gate is A Z=A’ functionally complete ¾ We can build any digital logic circuit out of all NAND gates A • Same holds true for the NOR Z=AB B gate and the multiplexer • The XOR & XNOR are not A functionally complete Z=A+B B using DeMorgan’s Theorem

C. E. Stroud Combinational Logic Design (1/06) 8 Gate-level Representations • SOP expressions A ¾ AND-OR • With inverters for B Z complemented literals Z=A’B’C+A’BC+ABC’+ABC C ¾ aka 2-level AND-OR logic representation 8 gates • POS expressions A ¾ OR-AND • With inverters for Z complemented literals B Z=(A+B+C)•(A+B’+C) •(A’+B+C)•(A’+B+C’) C ¾ aka 2-level OR-AND logic representation

C. E. Stroud Combinational Logic Design (1/06) 9 Gate Level Representation

• from Boolean equation Z = (((A’B)’C)’+D’)’= ((A•B)•C)+D

A A’ (A’B)’ B ((A’B)’C)’ C Z D D’

C. E. Stroud Combinational Logic Design (1/06) 10 Circuit Analysis • Going from gate-level to A B C Z ¾truth table 0 0 0 0 • Apply 0s & 1s to inputs to get outputs 0 0 1 1 ¾Boolean equation 0 1 0 1 • Move equations to output 0 1 1 0 1 0 0 0 Z=(A+B’)C+A’BC’=AC+B’C+A’BC’ 1 0 1 1 A A+B’ 1 1 0 0 B B’ (A+B’)C 1 1 1 1 C Z A’ A’BC’ C’

C. E. Stroud Combinational Logic Design (1/06) 11 Circuit Analysis • We can implement different circuits for same logic function that are functionally equivalent (produce the correct output response for all input values) ¾ Which implementation is the best? • Depends on design goals and criteria • Area analysis ¾ Number of gates, G (most commonly used)

¾ Number of gate inputs and outputs, GIO (more accurate) • Bigger gates take up more area • Performance analysis (worst case path from inputs to outputs)

¾ Number of gates in worst case path from input to output, Gdel ¾ More accurate delay measurement per gate • Propagation delay = intrinsic (internal) delay + extrinsic (external) delay

• Relative prop delay, Pdel = # inputs to gate (intrinsic) + # loads (extrinsic) C. E. Stroud Combinational Logic Design (1/06) 12 Circuit Analysis Example • From previous example: Z=(A+B’)C+A’BC’ ¾# gates: G = 7 2 A A+B’ 2 B B’ (A+B’)C ¾# gate I/O: GIO = 19 2C 1+1 2+1 Z ¾Gate delay: G = 4 A’ 2+1 del 1+1 2+0 A’BC’ • worst case path: B→Z C’ 3+1 1+1 ¾Prop delay: Pdel = 12 • worst case path: B→Z

C. E. Stroud Combinational Logic Design (1/06) 13 Circuit Optimization • Obviously we want smallest, fastest circuit • Some Basic Goals: ¾Minimizing # product terms minimizes # of AND gates and # inputs to OR gate in a 2-level SOP (AND-OR) representation ¾Minimizing # literals in each product term minimizes # inputs to its AND gate • We can use postulates & theorems, but… ¾It would be nice to find a more reliable procedure

C. E. Stroud Combinational Logic Design (1/06) 14