AD720/AD721 RGB to NTSC/PAL Encoders

a RGB to NTSC/PAL Encoders AD720/AD721 FEATURES (subcarrier amplitude and phase) signals in accordance with Composite Video Output either NTSC or PAL standards. These two outputs are also Chrominance and Luminance (S-Video) Outputs combined to provide a composite video output. All three out- No External Filters or Delay Lines Required puts are available separately at voltages of twice the standard Drives 75 Ω Reverse-Terminated Loads signal levels as required for driving 75 Ω reverse terminated Compact 28-Pin PLCC cables. The AD721 also features a bypass mode, in which the Logic Selectable NTSC or PAL Encoding Modes RGB inputs may bypass the encoder section of the IC via three Automatically Selects Proper Chrominance Filter gain-of-two amplifiers suitable for driving 75 Ω reverse termi- Cutoff Frequency for Encoding Standard nated cables. Logic Selectable Encode or Power-Down Mode (AD720 The AD720 and AD721 provide a complete, fully calibrated Only) function, requiring only termination resistors, bypass capacitors, Logic Selectable Encode or Bypass Mode (AD721 Only) a clock input at four times the subcarrier frequency, and a com- Low Power: 200 mW typical posite sync pulse. There are two control inputs: one input APPLICATIONS selects the TV standard (NTSC/PAL) and the other (ENCD) RGB to NTSC or PAL Encoding powers down most sections of the chip when the encoding func- Drive RGB Signals into 75 Ω Load (AD721 Only) tion is not in use (AD720) or activates the triple bypass buffer to drive the RGB signals when RGB encoding is not required (AD721). All logical inputs are CMOS compatible. The chip PRODUCT DESCRIPTION operates from ±5 V supplies. The AD720 and AD721 RGB to NTSC/PAL Encoders convert red, green and blue color component signals into their corre- (continued on page 5) sponding luminance (baseband amplitude) and chrominance

FUNCTIONAL BLOCK DIAGRAM

NTSC/PAL DELAYED C-SYNC C-SYNC POWER AND GROUNDS ASNC SYNC DELAY DECODER NTSC/PAL +5V LOGIC C-SYNC BURST +5V ANALOG ANALOG ONLY ±180° SC 90°/270° Ð5V SC 90° (PAL ONLY) NTSC/PAL AGND ANALOG 4FSC QUADRATURE CLOCK DGND LOGIC ENCD DECODER AT 8FSC SC 0° BURST DC 5MHz 5MHz LUMINANCE OUTPUT* Y SAMPLED- RESTORE 2-POLE 4-POLE LP X2 Ð0.572V TO 1.43V NTSC RED DATA AND C-SYNC LP POST- PRE-FILTER DELAY LINE Ð0.6V TO 1.4V PAL INSERTION FILTER COMPOSITE OUTPUT* RGB-TO-YUV U 1.2MHz NTSC/PAL ∑ X2 Ð0.572V TO 2V NTSC GREEN ENCODING 4-POLE Ð0.6V TO 2V PAL MATRIX LPF 3.6MHz (NTSC) BALANCED ∑ 4.4MHz (PAL) X2 CHROMINANCE OUTPUT* V 1.2MHz MODULATORS 3-POLE LPF 572mVp-p NTSC BLUE 4-POLE 600mVp-p PAL LPF

X2 ROUT *NOTE: THE LUMINANCE, COMPOSITE, AND CHROMINANCE 1.5Vp-p AD721 (ONLY) OUTPUTS ARE AT TWICE NORMAL LEVELS FOR DRIVING 75Ω REVERSE-TERMINATED LINES. X2 GOUT 1.5Vp-p

X2 BOUT 1.5Vp-p

REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703 ° ± AD720/AD721–SPECIFICATIONS (TA = +25 C and supplies = 5 V unless otherwise noted) Parameter Conditions Min Typ Max Unit

SIGNAL INPUTS (RDIN, GRIN, BLIN) Input Amplitude NTSC 714 mV PAL 700 mV Input Resistances1 RDIN with Respect to AGND 2.3 kΩ GRIN with Respect to AGND 4.2 kΩ BLIN with Respect to AGND 4.2 kΩ Input Capacitance 5pF LOGIC INPUTS (C-SYNC, 4FSC, ENCD, NTSC) Logic LO Input Voltage 1 V Logic HI Input Voltage 4 V Logic LO Input Current (DC) <1 µA Logic HI Input Current (DC) <1 µA BYPASS AMPLIFIERS (AD721 Only) Gain Error Nominal Gain of ×22 –5 +5 % Small Signal –3 dB Bandwidth 100 MHz Output Offset Voltage (Active State) –50 +50 mV Output Voltage (Inactive State) –50 +50 mV VIDEO OUTPUTS3 (LUMA, CRMA, CMPS) Luminance (LUMA) Output Bandwidth 5 MHz Gain Error –5 ±1 +5 % Linearity ±0.1 % Sync Level NTSC 252 286 320 mV PAL 300 mV Chrominance (CRMA) Output Bandwidth NTSC 3.6 MHz PAL 4.4 MHz Color Burst Amplitude NTSC 257 286 315 mV p-p PAL 300 mV p-p Absolute Gain Error –15 ±5 +15 % Absolute Phase Error ±3 Degrees Chroma/Luma Time Alignment4 NTSC –170 ns Composite Output Absolute Gain Error –5 ±1 +5 % Differential Gain With Respect to Chroma Channel 0.1 % Differential Phase With Respect to Chroma Channel 0.1 Degrees Output Offset Voltage Chroma, Luma, or Composite Outputs 50 100 mV Chroma Feedthrough Monochrome Input 20 55 mV p-p POWER SUPPLIES (APOS, DPOS, VNEG) Recommended Supply Range Dual Supply ±4.75 ±5.25 V Full Output Current5 –5 V Supply 35 mA +5 V Supply 67 mA Zero Signal Quiescent Current –5 V Supply 10 20 35 mA +5 V Supply 10 20 35 mA Bypass Mode Quiescent Current –5 V Supply 14 20 mA (AD721 Only) +5 V Supply 14 20 mA

NOTES 1Input scaling resistors provide best scaling accuracy when source resistance is 37.5 Ω (75 Ω reverse-terminated input). 2Required for driving a 75 Ω double reverse terminated load. 3All outputs are measured at a reverse-terminated load; voltages at IC pins are twice those specified here. 4This is a predistortion (per FCC specifications) that compensates for the chroma/luma delay in the low-pass filter that separates the luminance and chrominance signals in a television receiver. 5CRMA, LUMA, and CMPS outputs are all connected to 75 Ω reverse-terminated loads; full-white signal for entire field. Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units. Specifications subject to change without notice.

–2– REV. 0 AD720/AD721

ABSOLUTE MAXIMUM RATINGS* PIN DESCRIPTIONS Supply Voltage ±VS ...... ±6V Internal Power Dissipation ...... 600 mW Pin Mnemonic* Description* ° ° Operating Temperature Range ...... 0 C to +70 C 1 (NC) GOUT (No Connection) Green Bypass Buffer Storage Temperature Range ...... –65°C to +150°C 2 (NC) APOS (No Connection) Analog Positive Supply; +5 V ± 5% Lead Temperature, Soldering 60 sec ...... +300°C 3 (NC) ROUT (No Connection) Red Bypass Buffer NOTE 4 AGND Analog Ground Connection *Stresses above those listed under “Absolute Maximum Ratings” may cause 5 ENCD A Logical High Enables the NTSC/PAL Encode permanent damage to the device. This is a stress rating only, and functional Mode (A Logical Low Powers Down the Chip) operation of the device at these or any other conditions above those indicated in the A Logical Low Enables the RGB Bypass Mode operational section of this specification is not implied. Exposure to absolute 6 RDIN Red Component Video Input maximum rating conditions for extended rating conditions for extended periods 0 mV to 714 mV for NTSC may affect device reliability. 0 mV to 700 mV for PAL θ ° Thermal characteristics: 28-pin plastic package: JA = 100 C. 7 AGND Analog Ground Connection 8 GRIN Green Component Video Input ORDERING GUIDE 0 mV to 714 mV for NTSC 0 mV to 700 mV for PAL Temperature Package 9 AGND Analog Ground Connection Model Range Package Option 10 BLIN Blue Component Video Input 0 mV to 714 mV for NTSC AD720JP 0°C to +70°C 28-Pin PLCC P-28A 0 mV to 700 mV for PAL AD721JP 0°C to +70°C 28-Pin PLCC P-28A 11 STND A Logical High Input Selects NTSC Encoding A Logical Low Input Selects PAL Encoding CMOS Logic Levels PIN CONNECTIONS 12 AGND Analog Ground Connection 28-Lead Plastic Leaded Chip Carrier (PLCC) Package 13 CRMA Chrominance Output; Subcarrier Only** 572 mV Peak-to-Peak for NTSC P-28A 600 mV Peak-to-Peak for PAL 14 APOS Analog Positive Supply; +5 V ± 5% 15 CMPS Composite Video Output** –572 mV to 2 V for NTSC –600 mV to 2 V for PAL APOS VNEG GOUT (NC) AGND BOUT (NC) APOS (NC) ROUT (NC) 16 APOS Analog Positive Supply; +5 V ± 5% 4 3 2 1 28 27 26 17 LUMA Luminance Plus SYNC Output** –572 mV to 1.43 V for NTSC –600 mV to 1.4 V for PAL 5 25 DGND ENCD 18 VNEG System Negative Supply; –5 V ± 5% RDIN 6 24 SYNC 19 DGND Digital Ground Connection 20 4FSC Clock Input at Four Times the Subcarrier Frequency AGND 7 23 DPOS AD720/AD721 14.318 180 MHz for NTSC RGB TO NTSC/PAL GRIN 8 22 ASNC 17.734 480 MHz for PAL ENCODER AGND 9 21 DPOS CMOS Logic Levels 21 DPOS Digital Positive Supply; +5 V ± 5% BLIN 10 20 4FSC 22 ASNC A Logical High Input Resets the Subcarrier Phase Every Frame STND 11 19 DGND A Logical Low Input Resets the Subcarrier Phase Every Fourth Frame 12 13 14 15 16 17 18 CMOS Logic Levels 23 DPOS Digital Positive Supply; +5 V ± 5% VNEG APOS APOS LUMA CMPS

AGND CRMA 24 SYNC Input for Composite Television NOTE: Synchronization Pulses CONNECTIONS IN ( ) PERTAIN ONLY TO AD720 Negative Sync Pulses CMOS Logic Levels 25 DGND Digital Ground Connections (One of Two) 26 VNEG System Negative Supply; –5 V ± 5% 27 (NC) BOUT (No Connection) Blue Bypass Buffer 28 APOS Analog Positive Supply; +5 V ± 5%

*( ) pertain only to AD720. **The luminance, chrominance, and composite outputs are at twice normal levels for driving 75 Ω reverse-terminated lines. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. WARNING! Although the AD720/AD721 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ESD SENSITIVE DEVICE

REV. 0 –3– AD720/AD721–Typical Characteristics

COMPOSITE VIDEO VOLTS IRE:FLT FRAMES SELECTED: 1 2; APL = 45.8% COMPOSITE 525 LINE NTSC; NO FILTERING µ SYNC SLOW CLAMP TO 0.00V AT 6.63 s TEKTRONIX TSG 300 AD720/AD721 SONY PRECISION MODE OFF SYNC = SOURCE COMPONENT VIDEO RGB RGB TO NTSC/PAL MONITOR WAVEFORM GENERATOR ENCODER MODEL 1342 100.0 3

75Ω Ω GENLOCK 75 0.5

4FSC 50.0 TEKTRONIX 1910 COMPOSITE VIDEO FSC PIXEL-CLOCK TEKTRONIX VM700A WAVEFORM GENERATOR GENERATOR WAVEFORM MONITOR

0.0 Figure 1. AD720/AD721 Evaluation Setup

DG DP(NTSC) (SYNC = EXT) FIELD = 1 LINE = 21 0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 DIFFERENTIAL GAIN (%) MIN = Ð0.10; MAX = 0.00; p-p/MAX = 0.10 MICROSECONDS 0.00 Ð0.04 0.00 Ð0.01 Ð0.04 Ð0.10 0.10 0.05 Figure 4. 100% Color Bars, NTSC 0.00

Ð0.05 VOLTS IRE:FLT FRAMES SELECTED: 1 2; APL = 11.3% Ð0.10 525 LINE NTSC; NO FILTERING SLOW CLAMP TO 0.00V AT 6.63µs PRECISION MODE OFF DIFFERENTIAL PHASE (°) MIN = 0.00; MAX = 0.07; p-p = 0.07 SYNC = SOURCE 0.00 0.05 0.05 0.04 0.07 0.01 100.0 0.10 0.05 0.5 0.00 Ð0.05 50.0 Ð0.10

1ST 2ND 3RD 4TH 5TH 6TH 0.0 Figure 2. Composite Output Differential Phase and Gain, NTSC (Nulled to Chroma Output)

VOLTS IRE:FLT NOISE REDUCTION: 15.05dB 0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 APL = 49.6% MICROSECONDS 525 LINE NTSC; NO FILTERING SLOW CLAMP TO 0.00V AT 6.63µs SYNC = SOURCE Figure 5. Multipulse, NTSC 100.0 FRAMES SELECTED: 1 2

H TIMING MEASUREMENT RS-170A (NTSC) 0.5 FIELD = 1 LINE = 22 8.0 50.0 CYCLES 5.35µs

4.82µs 0.0

85ns

39.4 IRE 39.2 IRE 73ns

0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 MICROSECONDS/PRECISION MODE OFF AVERAGE 32 TO 32

Figure 3. Modulated Pulse and Bar, NTSC Figure 6. Horizontal Timing, NTSC

H TIMING (PAL) LINE = 17 1.98µs

5.52µs

4.82µs

81ns 302.2mV 292.1mV 82ns

AVERAGE 32 TO 32

Figure 7. Horizontal Timing, PAL

–4– REV. 0 AD720/AD721

(continued from page 1) Y = 0.299R + 0.587G + 0.114B All required low-pass filters are on chip. After the input signals U = 0.493 (B-Y) pass through a precision RGB to YUV encoding matrix, two on- V = 0.877 (R-Y) chip low-pass filters limit the bandwidth of the U and V color For NTSC operation, the chroma amplitude is increased by the difference signals to 1.2 MHz prior to quadrature modulation of factor 1.06 prior to summation with the luminance output. The the color subcarrier; a third low-pass filter at 3.6 MHz (NTSC) burst signal is inserted into the Y channel in the encoding matrix. or 4.4 MHz (PAL) follows the modulators to limit the harmonic The three outputs of the encoding matrix, now transformed into Y, content of the output. U, and V components, take two paths. The Y (luminance) signal is Delays in the U and V chroma filters are matched by an on-chip passed through a delay line consisting of a prefilter, a sampled-data sampled data delay line in the Y signal path; to prevent aliasing, delay line, and a post filter. The pre- and post-filters prevent prefilter at 5 MHz is included ahead of the delay line and a post aliasing of harmonics back into the baseband video. The overall de- filter at 5 MHz is added after the delay line to suppress harmon- lay is a nominal –170 ns relative to the chrominance signal, in ics in the output. These low-pass filters are optimized for mini- keeping with broadcast requirements to compensate for delays in- mum pulse overshoot. The overall delay is about 170 ns, which troduced by the filters in the decoding process. precompensates for delays in the filters used to decode the The U and V components pass through 4-pole modified Bessel NTSC or PAL signal in a television receiver. (This precompen- low-pass filters with a 1.2 MHz –3 dB frequency to prevent sation delay is already present in TV broadcasts.) aliasing in the balanced modulators, where they modulate a The AD720 and AD721 are available in a 28-pin plastic leaded 3.579 545 000 MHz (NTSC) or 4.433 618 750 MHz (PAL) chip carrier for the 0°C to +70°C commercial temperature range. signal via a pair of balanced modulators driven in quadrature by the color subcarrier. THEORY OF OPERATION The AD720/AD721 4FSC input drives a digital divide-by-4 cir- Referring to the AD720/AD721 block diagram (Figure 8), the cuit (two flip-flops) to create the quadrature signal. The refer- RGB inputs (each 0 mV to 714 mV in NTSC or 0 mV to ence phase 0° is used for the U signal. In the NTSC mode, the 700 mV in PAL) are first encoded into luminance and color V signal is modulated at 90°, but in the PAL mode, the V difference signals. The luminance signal is called the “Y” modulation input alternates between 90° and 270° at half the signal and the color-difference signals are called U and V. The line rate as required by the PAL standard. The outputs of the RGB inputs are encoded into the YUV format using the balanced modulators are summed and low-pass filtered to re- transformation move harmonics.

X2 ROUT *NOTE: THE LUMINANCE, COMPOSITE, AND CHROMINANCE 1.5Vp-p AD721 (ONLY) OUTPUTS ARE AT TWICE NORMAL LEVELS FOR DRIVING 75Ω REVERSE-TERMINATED LINES. X2 GOUT 1.5Vp-p

X2 BOUT 1.5Vp-p

Figure 8. AD720/AD721 Functional Block Diagram

REV. 0 –5– AD720/AD721

The filtered output is summed with the luminance signal to cre- Asserting the ENCD pin to a logical low routes the AD721’s ate a composite video signal. The separate luminance, chromi- RGB inputs through three gain-of-two bypass buffers for driving nance, and composite video signals are amplified by gain-of-two 75 Ω reverse-terminated lines, bypassing the encoder section of amplifiers for driving 75 Ω reverse-terminated lines. The sepa- the AD721. The triple bypass amplifier is utilized to overcome rate luminance and chrominance outputs together are known as the loading effects of a “TV-out” connection on the RGB moni- “S-Video.” tor output. When a video encoder is connected to outputs of a The digital section of the AD720/AD721 is clocked by the current-out video RAMDAC or VGA controller, the R, G, and 4FSC input. It measures the width of pulses in the composite B signals to the monitor are loaded-down. This requires the use sync input to separate vertical, horizontal, and serration pulses of a gain block to properly drive the monitor. and to insert the subcarrier burst only after a valid horizontal sync pulse.

+5V FROM Ð5V FROM ANALOG SUPPLY ANALOG SUPPLY 0.1µF 0.1µF

ENCODE INPUT 4 3 2 1 28 27 26 ENCODE = CMOS HIGH AGND VNEG NC NC NC POWER DOWN = CMOS LOW NC 25 5 ENCD APOS DGND COMPOSITE SYNC INPUT IOR 6 RDIN SYNC 24 CMOS LOGIC LEVEL Ω NEGATIVE SYNC TIPS 75Ω 75 7 AGND DPOS 23 +5V FROM VIDEO DIGITAL SUPPLY RAM-DAC AD720 0.1µF ADV47X IOG 8 GRIN RGB TO NTSC/PAL ASNC 22 75Ω ADV71XX 75Ω ENCODER 9 AGND DPOS 21 +5V FROM 0.1µF DIGITAL SUPPLY IOB 10 BLIN 4FSC 20 Ω 75Ω 75 4 X SUBCARRIER INPUT 11 STND DGND 19 0.1µF CMOS LOGIC LEVELS NTCS = 14.318 180MHz APOS APOS CRMA CMPS VIDEO STANDARD AGND LUMA VNEG SELECTION INPUT PAL = 17.734 480MHz NTSC = CMOS HIGH 12 13 14 15 16 17 18 PAL = CMOS LOW Ð5V FROM ANALOG SUPPLY 75Ω LUMINANCE OUTPUT +5V FROM Ω ANALOG SUPPLY 75 COMPOSITE OUTPUT 0.1µF 75Ω CHROMINANCE OUTPUT

Figure 9. AD720 Application

75Ω RED OUTPUT 75Ω GREEN OUTPUT 0.1µF +5V FROM 75Ω ANALOG SUPPLY BLUE OUTPUT Ð5V FROM 0.1µF ANALOG SUPPLY

4 3 2 1 28 27 26 ENCODE INPUT AGND VNEG NC NC NC ENCODE = CMOS HIGH NC 5 25 BYPASS = CMOS LOW ENCD APOS DGND COMPOSITE SYNC INPUT IOR 6 RDIN SYNC 24 CMOS LOGIC LEVEL Ω NEGATIVE SYNC TIPS 75Ω 75 7 AGND DPOS 23 +5V FROM VIDEO DIGITAL SUPPLY RAM-DAC AD721 0.1µF ADV47X IOG 8 GRIN RGB TO NTSC/PAL ASNC 22 75Ω ADV71XX 75Ω ENCODER 9 AGND DPOS 21 +5V FROM 0.1µF DIGITAL SUPPLY IOB 10 BLIN 4FSC 20 Ω 75Ω 75 4 X SUBCARRIER INPUT 11 STND DGND 19 0.1µF CMOS LOGIC LEVELS NTCS = 14.318 180MHz APOS APOS CRMA CMPS VIDEO STANDARD AGND LUMA VNEG PAL = 17.734 480MHz SELECTION INPUT NTSC = CMOS HIGH 12 13 14 15 16 17 18 PAL = CMOS LOW Ð5V FROM ANALOG SUPPLY 75Ω LUMINANCE OUTPUT +5V FROM Ω ANALOG SUPPLY 75 COMPOSITE OUTPUT 0.1µF 75Ω CHROMINANCE OUTPUT

Figure 10. AD721 Application

–6– REV. 0 AD720/AD721

APPLYING THE AD720/AD721 separator in the AD720/AD721 ignores horizontal sync pulses Figure 9 shows the application of the AD720 and Figure 10 that are too long or too short. Figure 11 shows the timing win- shows the application of the AD721. Note that the AD720 and dows for valid NTSC and PAL horizontal sync pulses. AD721 differ from other analog encoders because they are dc coupled. This means that, for example, the expected RGB inputs are 0 mV to 714 mV in NTSC and 0 mV to 700 mV in NTSC: 5.30µs PAL: 5.46µs PAL. The luminance, chrominance, and composite outputs are also dc coupled. These outputs can drive a 75 Ω reverse- COLOR BURST terminated load. Unused outputs should be terminated with 150 Ω resistors. COMPOSITE SYNC PULSE The RGB data must be supplied to the AD720/AD721 at NTSC or PAL rates, interlaced format. Various VGA chip set vendors support this mode of operation. Most computers supply NTSC: 2.79µs NTSC: 2.51µs NTSC: 2.51µs RGB outputs in noninterlaced format at higher data rates than PAL: 3.21µs PAL: 2.25µs PAL: 2.25µs NTSC and PAL, which means that “outboard” encoders must supply some form of timing conversion before the RGB data IF THE TRAILING EDGE OF A COMPOSITE SYNC PULSE IS WITHIN reaches the AD720/AD721. THIS WINDOW, THE PULSE IS TREATED AS A HORIZONTAL SYNC PULSE. IF THE TRAILING EDGE IS OUTSIDE THIS WINDOW, THE PULSE IS TREATED Note also that the AD720/AD721 does not have internal dc res- AS AN EQUALIZING OR BLANKING PULSE. toration and does not accept sync on green. The composite sync Figure 11. NTSC and PAL Timing for Valid Horizontal input is a separate, CMOS logical-level input and must be syn- Sync Pulses chronized with the 4FSC input, which serves as the master clock for the AD720/AD721. When the horizontal sync pulses are too long or too short, a dc offset voltage (due to charge storage) increases on the output of The AD720/AD721 does not implement two elements of the the sampled data delay line’s auto-zero amplifier. Normally, this PAL and NTSC standards. In NTSC operation, it does not offset voltage is removed at the beginning of every line, as signi- support the 7.5 IRE unit setup (1 IRE unit = 7.14 mV)—this fied by the horizontal sync pulse. Without the horizontal sync must be added via software using the RGB inputs. Many RAM- pulse, the dc offset on the auto-zero amplifier increases over DACs, such as the Analog Devices ADV471 and ADV478, offer time (usually about three to five minutes) until it overrides the a logic-selectable setup mode. In PAL operation, the AD720/ luminance information. The end result is a slow fade to black or AD721 does not implement a 25 Hz subcarrier offset. white. Decoupling and Grounding Color Flickering—Asynchronous Operation Referring to the pin descriptions, the AD720/AD721 uses mul- The AD720/AD721 requires that its 4FSC and composite sync tiple analog grounds, digital grounds, digital positive supply in- signals be synchronized. In most systems, when the two signals puts, analog positive supply inputs, and analog negative supply are synchronized, the composite sync signal is generated using a inputs in order to maximize isolation between analog and digital 4FSC signal as the reference. After every four frames, the signal paths. AD720/AD721 resets the phase quadrature generator. When the The most sensitive input of the AD720/AD721 is the 4FSC pin: CSYNC and 4FSC are synchronized, this reset is transparent to any noise on this pin directly affects the subcarrier and causes the system because the reference phase does not change. When degradation of the picture. Digital and analog grounds should the CSYNC and 4FSC are not synchronized, the difference be kept separate and brought together at a single point. between the reference phase and its new value upon reset causes All power supply pins should be decoupled using 0.1 µF ceramic an instantaneous color shift, which appears as a flickering in the capacitors located as close to the AD720/AD721 as possible. In color. addition, ferrite beads may be slipped over the power supply Adding NTSC Setup leads to reduce high frequency noise. The easiest way to add the 7.5 IRE unit1 setup is to use a If a high speed RAM-DAC is used (e.g., capable of 80 MHz op- ADV471/478 or ADV477/475 or ADV473 type RAM-DAC, eration with subnanosecond rise times), care must be taken to which have a logic-selectable setup (called “pedestal” on some properly terminate the input printed-circuit-board traces to the data sheets and “setup” on others). AD720/AD721. Otherwise, ringing on these traces may occur Color Fidelity and cause degradation of the picture. A source impedance other than 37.5 Ω (75 Ωʈ75 Ω—a reverse-terminated 75 Ω input) can cause errors in the YUV APPLICATIONS HINTS encoding matrix, which is basically resistive and depends on the In applying the AD720/AD721, problems may arise due to in- correct source impedance for accuracy. Figures 9 and 10 show correct input signals. A few common situations follow. the correct interface between a RAM-DAC and the AD720 and Ω Fade to Black or White—Invalid Horizontal Sync Pulses AD721 respectively, using 75 reverse-terminated connections. Some systems produce sync pulses that are longer or shorter than the NTSC and PAL standards specify. The digital sync NOTE 1IRE unit = 7.14 mV.

REV. 0 –7– AD720/AD721

OUTLINE DIMENSIONS Dimensions shown in inches and (mm).

28-Lead Plastic Leaded Chip Carrier (PLCC) Package P-28A

0.180 (4.57) 0.165 (4.19) 0.048 (1.21) 0.056 (1.42) 0.042 (1.07) 0.042 (1.07) 0.025 (0.63) 0.015 (0.38) 0.048 (1.21) C1932–7.5–7/94 0.042 (1.07) 4 26 5 PIN 1 25 IDENTIFIER 0.021 (0.53) 0.013 (0.33) 0.050 (1.27) 0.430 (10.92) BSC TOP 0.390 (9.91) VIEW

0.032 (0.81) 0.026 (0.66) 11 19 12 18 0.020 0.040 (1.01) (0.50) 0.456 (11.58) 0.025 (0.64) R SQ 0.450 (11.43) 0.110 (2.79) 0.085 (2.16) 0.495 (12.57) SQ 0.485 (12.32) PRINTED IN U.S.A.

–8– REV. 0