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Digital PAL/NTSC Encoder with 10-Bit

SSAF™ and Advanced Power Management ADV7170/ADV7171

FEATURES Programmable delay ITU-R1 BT601/656 YCrCb to PAL/NTSC video encoder Individual on/off control of each DAC High quality 10-bit video DACs CCIR and square operation SSAF (super sub-alias filter) Integrated locking to external video source Advanced power management features Color control/burst signal control CGMS (copy generation management system) Interlaced/noninterlaced operation WSS (wide screen signalling) Complete on-chip video timing generator Simultaneous Y, U, V, C output format Programmable multimode master/slave operation 3 NTSC , PAL M/N2, PAL B/D/G/H/I, PAL60 Macrovision® AntiTaping Rev. 7.1 (ADV7170 only) Single 27 MHz clock required (×2 oversampling) support 80 dB video SNR insertion port (PAL-WST) 32-bit direct digital synthesizer for color subcarrier On-board color bar generation Multistandard video output support On-board voltage reference 2 2 Composite (CVBS) 2-wire serial MPU interface (I C®-compatible and Fast I C) Components S-Video (Y/C), YUV, and RGB Single supply 5 V or 3.3 V operation EuroSCART output (RGB + CVBS/LUMA) Small 44-lead MQFP/TQFP packages 4 Component YUV + CHROMA Industrial temperature grade = −40°C to +85°C Video input data port supports APPLICATIONS CCIR-656 4:2:2 8-bit parallel input format High performance DVD playback systems, portable video 4:2:2 16-bit parallel input format equipment including digital still cameras and laptop PCs, video games, PC video/ and digital Programmable simultaneous composite and S-Video or RGB satellite/cable systems (set-top boxes/IRD) (SCART)/YUV video outputs

Programmable luma filters (low-pass [PAL/NTSC]) notch, 1 ITU-R and CCIR are used interchangeably in this document (ITU-R has replaced extended (SSAF, CIF, and QCIF) CCIR recommendations). 2 Throughout the document N is referenced to PAL- Combination -N. Programmable chroma filters (low-pass [0.65 MHz, 1.0 MHz, 3 Protected by U.S. Patents 4,631,603;, 4,577,216, 4,819,098; and other intellectual 1.2 MHz and 2.0 MHz], CIF and QCIF) property rights. The Macrovision anticopy process is licensed for noncommercial Programmable VBI (vertical blanking interval) home use only, which is its sole intended use in the device. Please contact sales office for latest Macrovision version available. Programmable subcarrier frequency and phase 4 Refer to Table 8 for complete operating details. TTXREQ TTX

M POWER 10 U 10 MANAGEMENT CGMS AND WSS TELETEXT L 10-BIT DAC D (PIN 27) DAC CONTROL INSERTION INSERTION YUV TO T VAA 10 (SLEEP MODE) BLOCK BLOCK RGB I 10 MATRIX P 10-BIT DAC C (PIN 26) L DAC RESET 10 E X 10 COLOR 8 Y 8 9 9 E 10-BIT DAC B (PIN 31) ADD INTER- PROGRAMMABLE 10 DAC DATA SYNC LUMINANCE R P7–P0 4:2:2 TO YCrCb POLATOR 8 FILTER 4:4:4 TO U INTER- YUV U 8 8 8 10 10 P15–P8 POLATOR MATRIX ADD INTER- PROGRAMMABLE 8 V 8 8 8 10-BIT DAC A (PIN 32) BURST POLATOR 10 DAC FILTER V

HSYNC 10 ADV7170/ADV7171 VIDEO TIMING REAL-TIME 10 /VSYNC 2 V GENERATOR I C MPU PORT CONTROL SIN/COS VOLTAGE REF BLANK CIRCUIT DDS BLOCK REFERENCE RSET CIRCUIT COMP

CLOCK SCLOCK SDATA ALSB SCRESET/RTC GND 00221-001

Figure 1. Functional Block Diagram Protected by U.S. Patents 5,343,196; 5,442,355; and other intellectual property rights.

Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. : 781.461.3113 ©2002–2009 Analog Devices, Inc. All rights reserved. ADV7170/ADV7171

TABLE OF CONTENTS Specifications ...... 4 Mode Register 1 MR1 (MR17 to MR10) ...... 30

Dynamic Specifications ...... 6 MR1 Bit Description ...... 30

Timing Specifications ...... 7 Mode Register 2 MR2 (MR27 to MR20) ...... 30

Timing Diagrams...... 9 MR2 Bit Description ...... 30

Absolute Maximum Ratings ...... 10 Mode Register 3 MR3 (MR37 to MR30) ...... 32

Package Thermal Performance ...... 10 MR3 Bit Description ...... 32

ESD Caution ...... 10 Mode Register 4 MR4 (MR47 to MR40) ...... 33

Pin Configuration and Function Descriptions ...... 11 MR4 Bit Description ...... 33

General Description ...... 13 VSYNC_3H (MR43) ...... 33

Data Path Description ...... 13 Timing Mode Register 0 (TR07 to TR00) ...... 33

Internal Filter Response ...... 14 TR0 Bit Description ...... 34

Typical Performance Characteristics ...... 15 Timing Mode Register 1 (TR17 to TR10) ...... 34

Features ...... 18 TR1 Bit Description ...... 34

Color Bar Generation ...... 18 Subcarrier Frequency Registers 0 to 3 (FSC3 to FSC0) ...... 35

Square Pixel Mode ...... 18 Subcarrier Phase Registers (FP7 to FP0) ...... 35

Color Signal Control ...... 18 Closed Captioning Even Field Data Register 1 to 0 (CED15 to CED0) ...... 35 Burst Signal Control ...... 18 Closed Captioning Odd Field Data Registers 1 to 0 (CCD15 NTSC Pedestal Control ...... 18 to CCD0) ...... 35 Pixel Timing Description ...... 18 NTSC Pedestal/PAL Teletext Control Registers 3 to 0 (PCE15 Subcarrier Reset ...... 18 to PCE0, PCO15 to PCO0)/(TXE15 to TXE0, TXO15 to TXO0) ...... 36 Real-Time Control ...... 18 Teletext Request Control Register TC07 (TC07 to TC00) .... 36 Video Timing Description ...... 18 CGMS_WSS Register 0 C/W0 (C/W07 to C/W00) ...... 36 Power-On Reset ...... 26 C/W0 Bit Description ...... 36 SCH Phase Mode ...... 26 CGMS_WSS Register 1 C/W1 (C/W17 to C/W10) ...... 37 MPU Port Description ...... 26 C/W1 Bit Description ...... 37 Register Accesses ...... 27 CGMS Data Bits (C/W17 to C/W16) ...... 37 Register Programming ...... 28 CGMS_WSS Register 2 C/W1 (C/W27 to C/W20) ...... 37 Subaddress Register (SR7 to SR0) ...... 28 C/W2 Bit Description ...... 37 Register Select (SR5 to SR0) ...... 28 Appendices ...... 38 Mode Register 0 MR0 (MR07 to MR00) ...... 28 Appendix 1—Board Design and Layout Considerations...... 38 MR0 Bit Description ...... 28

Rev. C | Page 2 of 64 ADV7170/ADV7171

Appendix 2—Closed Captioning ...... 40 Appendix 7—Optional Output Filter ...... 48

Appendix 3—Copy Generation Management System Appendix 8—Optional DAC Buffering ...... 48 (CGMS) ...... 41 Appendix 9—Recommended Register Values ...... 49 Appendix 4—Wide Screen Signaling ...... 42 Appendix 10—Output Waveforms ...... 51 Appendix 5—Teletext Insertion ...... 43 Outline Dimensions ...... 61 Appendix 6—Waveforms ...... 44 Ordering Guide ...... 62

REVISION HISTORY

3/09—Rev. B to Rev. C

Changes to Table 8 ...... 10 Updated Outline Dimensions ...... 61 Added Figure 103, Renumbered Figures Sequentially ...... 61 Changes to Ordering Guide ...... 61

6/05—Rev. A to Rev. B Updated Format ...... Universal Changes to Features Section ...... 1 Changes to Table 8 ...... 10 Changes to Square Pixel Mode Section ...... 18 Changes to Figure 37 ...... 29 Changes to Figure 42 ...... 33 Changes to Subcarrier Frequency Registers 3 to 0 Section ...... 35 Changes to Figure 45 ...... 35 Changes to Figure 82 ...... 48 Changes to Ordering Guide ...... 62

6/02—Starting Rev. A to Rev. B Changes to Specifications ...... 3 Changes to Package Thermal Performance section...9

Rev. C | Page 3 of 64 ADV7170/ADV7171

SPECIFICATIONS

1 2 VAA = 5 V ± 5% , VREF = 1.235 V, RSET = 150 Ω. All specifications TMIN to TMAX , unless otherwise noted.

Table 1. 1 Parameter Conditions Min Typ Max Unit STATIC PERFORMANCE Resolution (Each DAC) 10 Bits Accuracy (Each DAC)

Integral Nonlinearity RSET = 300 Ω ±0.6 LSB Differential Nonlinearity Guaranteed monotonic ±1 LSB DIGITAL INPUTS

Input High Voltage, VINH 2 V

Input Low Voltage, VINL 0.8 V

Input Current, IIN VIN = 0.4 V or 2.4 V ±1 μA

Input Capacitance, CIN 10 pF DIGITAL OUTPUTS

Output High Voltage, VOH ISOURCE = 400 μA 2.4 V

Output Low Voltage, VOL ISINK = 3.2 mA 0.4 V Three-State Leakage Current 10 μA Three-State Output Capacitance 10 pF ANALOG OUTPUTS 3 Output Current RSET = 150 Ω, RL = 37.5 Ω 3 34.7 37 mA 4 Output Current RSET = 1041 Ω, RL = 262.5 Ω 5 mA DAC-to-DAC Matching 1.5 %

Output Compliance, VOC 0 +1.4 V

Output Impedance, ROUT 30 kΩ

Output Capacitance, COUT IOUT = 0 mA 30 pF VOLTAGE REFERENCE

Reference Range, VREF IVREFOUT = 20 μA 1.142 1.235 1.327 V POWER REQUIREMENTS5

VAA 4.75 5.0 5.25 V Normal Power Mode 6 IDAC (max) RSET = 150 Ω, RL = 37.5 Ω 150 155 mA 6 IDAC (min) RSET = 1041 Ω, RL = 262.5 Ω 20 mA 7 ICCT 75 95 mA Low Power Mode 6 IDAC (max) 80 mA 6 IDAC (min) 20 mA 7 ICCT 75 95 mA Sleep Mode 8 IDAC 0.1 μA 9 ICCT 0.001 μA Power Supply Rejection Ratio COMP = 0.1 μF 0.01 0.5 %/%

1 The min/max specifications are guaranteed over this range. The min/max values are typical over 4.75 V to 5.25 V. 2 Ambient temperature range TMIN to TMAX: −40°C to +85°C. The die temperature, TJ, must always be kept below 110°C. 3 Full drive into 37.5 Ω doubly terminated load. 4 Minimum drive current (used with buffered/scaled output load). 5 Power measurements are taken with clock frequency = 27 MHz. Max TJ = 110°C. 6 IDAC is the total current (min corresponds to 5 mA output per DAC; max corresponds to 37 mA output per DAC) to drive all four DACs. Turning off individual DACs reduces IDAC correspondingly. 7 ICCT (circuit current) is the continuous current required to drive the device. 8 Total DAC current in sleep mode. 9 Total continuous current during sleep mode. Rev. C | Page 4 of 64 ADV7170/ADV7171

1 2 VAA = 3.0 V to 3.6 V , VREF = 1.235 V, RSET = 150 Ω. All specifications TMIN to TMAX , unless otherwise noted.

Table 2. 1 Parameter Conditions Min Typ Max Unit STATIC PERFORMANCE3 Resolution (Each DAC) 10 Bits Accuracy (Each DAC)

Integral Nonlinearity RSET = 300 Ω ±0.6 LSB Differential Nonlinearity Guaranteed monotonic ±1 LSB 3 DIGITAL INPUTS

Input High Voltage, VINH 2 V

Input Low Voltage, VINL 0.8 V 3, 4 Input Current, IIN VIN = 0.4 V or 2.4 V ±1 μA

Input Capacitance, CIN 10 pF 3 DIGITAL OUTPUTS

Output High Voltage, VOH ISOURCE = 400 μA 2.4 V

Output Low Voltage, VOL ISINK = 3.2 mA 0.4 V Three-State Leakage Current 10 μA Three-State Output Capacitance 10 pF 3 ANALOG OUTPUTS 4, 5 Output Current RSET = 150 Ω, RL = 37.5 Ω 33 34.7 37 mA 6 Output Current RSET = 1041 Ω, RL = 262.5 Ω 5 mA DAC-to-DAC Matching 2.0 %

Output Compliance, VOC 0 1.4 V

Output Impedance, ROUT 30 kΩ

Output Capacitance, COUT IOUT = 0 mA 30 pF 3, 7 POWER REQUIREMENTS

VAA 3.0 3.3 3.6 V Normal Power Mode 8 IDAC (max) RSET = 150 Ω, RL = 37.5 Ω 150 155 mA 8 IDAC (min) RSET = 1041 Ω, RL = 262.5 Ω 20 mA 9 ICCT 35 mA Low Power Mode 8 IDAC (max) 80 mA 8 IDAC (min) 20 mA 9 ICCT 35 mA Sleep Mode 10 IDAC 0.1 μA 11 ICCT 0.001 μA Power Supply Rejection Ratio COMP = 0.1 μF 0.01 0.5 %/%

1 The min/max specifications are guaranteed over this range. The min/max values are typical over 3.0 V to 3.6 V. 2 Ambient temperature range TMIN to TMAX: −40°C to +85°C. The die temperature, TJ, must always be kept below 110°C. 3 Guaranteed by characterization. 4 Full drive into 37.5 Ω load. 5 DACs can output 35 mA typically at 3.3 V (RSET = 150 Ω and RL = 37.5 Ω); optimum performance obtained at 18 mA DAC current (RSET = 300 Ω and RL = 75 Ω). 6 Minimum drive current (used with buffered/scaled output load). 7 Power measurements are taken with clock frequency = 27 MHz. Max TJ = 110°C. 8 IDAC is the total current (min corresponds to 5 mA output per DAC, max corresponds to 38 mA output per DAC) to drive all four DACs. Turning off individual DACs reduces IDAC correspondingly. 9 ICCT (circuit current) is the continuous current required to drive the device. 10 Total DAC current in sleep mode. 11 Total continuous current during sleep mode.

Rev. C | Page 5 of 64 ADV7170/ADV7171

DYNAMIC SPECIFICATIONS

1 2 VAA = 5 V ± 5% , VREF = 1.235 V, RSET = 150 Ω. All specifications TMIN to TMAX , unless otherwise noted.

Table 3. 1 Parameter Conditions Min Typ Max Unit 3, 4 Normal power mode 0.3 0.7 % 3, 4 Normal power mode 0.4 0.7 Degrees 3, 4 Differential Gain Lower power mode 1.0 2.0 % 3, 4 Differential Phase Lower power mode 1.0 2.0 Degrees SNR3, 4(Pedestal) RMS 80 dB rms SNR3, 4(Pedestal) Peak periodic 70 dB p-p SNR3, 4(Ramp) RMS 60 dB rms SNR3, 4(Ramp) Peak periodic 58 dB p-p 3, 4 Accuracy 0.7 1.2 Degrees 3, 4 Color Saturation Accuracy 0.9 1.4 % 3, 4 Chroma Nonlinear Gain Referenced to 40 IRE 0.6 ±% 3 4 Chroma Nonlinear Phase 0.3 0.5 ±Degrees 3, 4 Chroma/Luma Intermod 0.2 0.4 ±% 3, 4 Chroma/Luma Gain Inequality 1.0 1.4 ±% 3, 4 Chroma/Luma Delay Inequality 0.5 2.0 ns 3, 4 Luminance Nonlinearity 0.8 1.4 ±% 3, 4 Chroma AM 82 85 dB 3, 4 Chroma PM Noise 79 81 dB

1 The min/max specifications are guaranteed over this range. The min/max values are typical over 4.75 V to 5.25 V. 2 Ambient temperature range TMIN to TMAX: −40°C to +85°C. The die temperature, TJ, must always be kept below 110°C. 3 Guaranteed by characterization. 4 These specifications are for the low-pass filter only and are guaranteed by design.

1 2 VAA = 3.0 V to 3.6 V , VREF = 1.235 V, RSET = 150 Ω. All specifications TMIN to TMAX , unless otherwise noted.

Table 4. 1 Parameter Conditions Min Typ Max Unit Differential Gain3 Normal power mode 1.0 % 3 Differential Phase Normal power mode 0.5 Degrees 3 Differential Gain Lower power mode 0.6 % 3 Differential Phase Lower power mode 0.5 Degrees SNR3 (Pedestal) RMS 78 dB rms SNR3 (Pedestal) Peak periodic 70 dB p-p SNR3 (Ramp) RMS 60 dB rms SNR3 (Ramp) Peak periodic 58 dB p-p 3 Hue Accuracy 1.0 Degrees 3 Color Saturation Accuracy 1.0 % 3, 4 Luminance Nonlinearity 1.4 ±% 3, 4 Chroma AM Noise 80 dB 3, 4 Chroma PM Noise 79 dB 3, 4 Chroma Nonlinear Gain Referenced to 40 IRE 0.6 ±% 3, 4 Chroma Nonlinear Phase 0.3 0.5 ±Degrees 3, 4 Chroma/Luma Intermod 0.2 0.4 ±%

1 The min/max specifications are guaranteed over this range. The min/max values are typical over 4.75 V to 5.25 V. 2 Ambient temperature range TMIN to TMAX: −40°C to +85°C. The die temperature, TJ, must always be kept below 110°C. 3 Guaranteed by characterization. 4 These specifications are for the low-pass filter only and are guaranteed by design. For other internal filters, see Table 10.

Rev. C | Page 6 of 64 ADV7170/ADV7171

TIMING SPECIFICATIONS

1 2 VAA = 4.75 V to 5.25 V , VREF = 1.235 V, RSET = 150 Ω. All specifications TMIN to TMAX , unless otherwise noted.

Table 5. Parameter Conditions Min Typ Max Unit 3, 4 MPU PORT SCLOCK Frequency 0 400 kHz

SCLOCK High Pulse Width, t1 0.6 μs

SCLOCK Low Pulse Width, t2 1.3 μs

Hold Time (Start Condition), t3 After this period the first clock is generated 0.6 μs

Setup Time (Start Condition), t4 Relevant for repeated start condition 0.6 μs

Data Setup Time, t5 100 ns

SDATA, SCLOCK Rise Time, t6 300 ns

SDATA, SCLOCK Fall Time, t7 300 ns

Setup Time (Stop Condition), t8 0.6 μs 3, 5 ANALOG OUTPUTS Analog Output Delay 7 ns DAC Analog Output 0 ns 5, 6 CLOCK CONTROL AND PIXEL PORT

fCLOCK 27 MHz

Clock High Time, t9 8 ns

Clock Low Time, t10 8 ns

Data Setup Time, t11 3.5 ns

Data Hold Time, t12 4 ns

Control Setup Time, t11 4 ns

Control Hold Time, t12 3 ns

Digital Output Access Time, t13 11 16 ns 4 Digital Output Hold Time, t14 8 ns 4 Pipeline Delay, t15 48 Clock cycles 3, 4, 7 TELETEXT

Digital Output Access Time, t16 20 ns

Data Setup Time, t17 2 ns

Data Hold Time, t18 6 ns 3, 4 RESET CONTROL RESET Low Time 6 ns

1 The min/max specifications are guaranteed over this range. The min/max values are typical over 4.75 V to 5.25 V range. 2 Ambient temperature range TMIN to TMAX: −40°C to +85°C. The die temperature, TJ, must always be kept below 110°C. 3 TTL input values are 0 V to 3 V, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. Analog output load ≤ 10 pF. 4 Guaranteed by characterization 5 Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition. 6 Pixel port consists of the following: Pixel inputs: P15–P0 Pixel controls: HSYNC, FIELD/VSYNC, BLANK Clock input: CLOCK 7 Teletext port consists of the following: Teletext output: TTXREQ Teletext input: TTX

Rev. C | Page 7 of 64 ADV7170/ADV7171

1 2 VAA = 3.0 V to 3.6 V , VREF = 1.235 V, RSET = 150 Ω. All specifications TMIN to TMAX , unless otherwise noted.

Table 6. Parameter Conditions Min Typ Max Unit 3, 4 MPU PORT SCLOCK Frequency 0 400 kHz

SCLOCK High Pulse Width, t1 0.6 μs

SCLOCK Low Pulse Width, t2 1.3 μs

Hold Time (Start Condition), t3 After this period the first clock is generated 0.6 μs

Setup Time (Start Condition), t4 Relevant for repeated start condition 0.6 μs

Data Setup Time, t5 100 ns

SDATA, SCLOCK Rise Time, t6 300 ns

SDATA, SCLOCK Fall Time, t7 300 ns

Setup Time (Stop Condition), t8 0.6 μs 3, 5 ANALOG OUTPUTS Analog Output Delay 7 ns DAC Analog Output Skew 0 ns 4, 5, 6 CLOCK CONTROL AND PIXEL PORT

fCLOCK 27 MHz

Clock High Time, t9 8 ns

Clock Low Time, t10 8 ns

Data Setup Time, t11 3.5 ns

Data Hold Time, t12 4 ns

Control Setup Time, t11 4 ns

Control Hold Time, t12 3 ns

Digital Output Access Time, t13 12 ns

Digital Output Hold Time, t14 8 ns

Pipeline Delay, t15 48 Clock cycles 3, 4, 7 TELETEXT

Digital Output Access Time, t16 23 ns

Data Setup Time, t17 2 ns

Data Hold Time, t18 6 ns 3, 4 RESET CONTROL RESET Low Time 6 ns

1 The max/min specifications are guaranteed over this range. The max/min values are typical over 3.0 V to 3.6 V range. 2 Ambient temperature range TMIN to TMAX: −40°C to +85°C. The die temperature, TJ, must always be kept below 110°C. 3 TTL input values are 0 V to 3 V, with input rise/fall times ≤3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. Analog output load ≤10 pF. 4 Guaranteed by characterization 5 Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition 6 Pixel Port consists of the following: Pixel inputs: P15–P0 Pixel controls: HSYNC, FIELD/VSYNC, BLANK Clock input: CLOCK 7 Teletext port consists of the following: Teletext output: TTXREQ Teletext input: TTX

Rev. C | Page 8 of 64 ADV7170/ADV7171

TIMING DIAGRAMS

t t3 t5 3 SDATA

t6 t1

SCLOCK

t2 t7 t4 t8 00221-002 Figure 2. MPU Port Timing Diagram

CLOCK

t9 t10 t12

HSYNC, CONTROL FIELD/VSYNC, I/PS BLANK

PIXEL INPUT DATA Cb Y Cr Y Cb Y

t11 t13

HSYNC, CONTROL FIELD/VSYNC, O/PS BLANK t 14 00221-003

Figure 3. Pixel and Control Data Timing Diagram

TTXREQ

t16

CLOCK

t17

t18 TTX

4 CLOCK 4 CLOCK 4 CLOCK 3 CLOCK 4 CLOCK CYCLES CYCLES CYCLES CYCLES CYCLES

00221-004 Figure 4. Teletext Timing Diagram

Rev. C | Page 9 of 64 ADV7170/ADV7171

ABSOLUTE MAXIMUM RATINGS

Table 7. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress VAA to GND 7 V rating only; functional operation of the device at these or any Voltage on Any Digital Input Pin GND − 0.5 V to VAA + 0.5 V other conditions above those indicated in the operational Storage Temperature (TS) −65°C to +150°C sections of this specification is not implied. Exposure to Junction Temperature (TJ) 150°C absolute maximum rating conditions for extended periods may Lead Temperature (Soldering, 10 sec) 260°C affect device reliability. Only one absolute maximum rating may 1 Analog Outputs to GND GND − 0.5 V to VAA be applied at any one time.

1 Analog output short circuit to any power supply or GND can be of an indefinite duration.

PACKAGE THERMAL PERFORMANCE Table 8. Allowable Operating Conditions for KS and KSU The 44-MQFP package used for this device takes advantage of Package Options an ADI patented thermal coastline lead frame construction. KS, WBS KSU This maximizes heat transfer into the leads and reduces the Conditions 3 V 5 V 3 V 5 V package thermal resistance. 4 DAC ON Double 75R1 Yes +70°C max +70°C max No 4 DAC ON Low Power2 Yes Yes Yes No For the MQFP package, the junction-to-ambient (θJA) thermal 4 DAC ON Buffering3 Yes Yes Yes Yes resistance in still air on a four-layer PCB is 35.5°C/W. The 3 DAC ON Double 75R Yes Yes Yes No junction-to-case thermal resistance (θJC) is 13.75°C/W. For the 3 DAC ON Low Power Yes Yes Yes Yes TQFP package, θJA in still air on a four-layer PCB is 53.2°C/W. 3 DAC ON Buffering Yes Yes Yes Yes θJC is 11.1°C/W. Junction Temperature = TJ = [VAA (Σ DAC Yes Yes Yes Yes Yes Output Current + ICCT) × θJA] + Ambient Temperature. Yes Yes Yes 4 DAC ON Buffering Yes Yes

1 DAC ON Double 75R refers to a condition where the DACs are terminated in a double 75R load and low power mode is disabled. 2 DAC ON Low Power refers to a condition where the DACs are terminated in a double 75R load and low power mode is enabled. 3 DAC ON Buffering refers to a condition where the DAC current is reduced to 5 mA and external buffers are used to drive the video load.

ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. C | Page 10 of 64 ADV7170/ADV7171

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS C SET CLOCK GND P4 P3 P1 P0 TTX TTXREQ SCRESET/RT R 44 43 42 41 40 39 38 37 36 35 34

VAA 1 33 VREF P5 2 PIN 1 32 DAC A P6 3 31 DAC B

P7 4 ADV7170/ADV7171 30 VAA MQFP/TQFP P8 5 29 GND

P9 6 TOP VIEW 28 VAA (Not to Scale) P10 7 27 DAC D P11 8 26 DAC C P12 9 25 COMP GND 10 24 SDATA

VAA 11 23 SCLOCK

12 13 14 15 16 17 18 19 20 21 22 AA P13 P14 P15 V GND GND ALSB RESET HSYNC BLANK 00221-005 FIELD/VSYNC Figure 5. Pin Configuration

Table 9. Pin Function Descriptions Input/ Pin No. Mnemonic Output Description

1, 11, 20, 28, 30 VAA P Power Supply (3 V to 5 V). 2 to 9, 12 to 14, P15 to P0 I 8-Bit 4:2:2 Multiplexed YCrCb Pixel Port (P7 to P0) or 16-Bit YCrCb Pixel Port (P15 to P0). 38 to 42 P0 represents the LSB. 10, 19, 21, 29, 43 GND G Ground Pin.

15 HSYNC I/O HSYNC (Mode 1 and Mode 2) Control Signal. This pin may be configured to output (master mode) or accept (slave mode) sync .

16 FIELD/VSYNC I/O Dual Function FIELD (Mode 1) and VSYNC (Mode 2) Control Signal. This pin may be configured to output (master mode) or accept (slave mode) these control signals.

17 BLANK I/O Video Blanking Control Signal. The pixel inputs are ignored when this is Logic Level 0. This signal is optional. 18 ALSB I TTL Address Input. This signal sets up the LSB of the MPU address.

22 RESET I The input resets the on-chip timing generator and sets the ADV7170/ADV7171 into default mode. This is NTSC operation, Timing Slave Mode 0, 8-bit operation, 2 × composite and S-Video out, and DAC B powered on and DAC D powered off. 23 SCLOCK I MPU Port Serial Interface Clock Input. 24 SDATA I/O MPU Port Serial Data Input/Output.

25 COMP O Compensation Pin. Connect a 0.1 μF capacitor from COMP to VAA. For optimum dynamic performance in low power mode, the value of the COMP capacitor can be lowered to as low as 2.2 nF. 26 DAC C O /S-Video C/V Analog Output. 27 DAC D O /S-Video Y/Y Analog Output. 31 DAC B O /Composite/U Analog Output. 32 DAC A O PAL/NTSC Output. Full-scale output is 180 IRE (1286 mV) for NTSC and 1300 mV for PAL.

33 VREF I/O Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).

34 RSET I A 150 Ω resistor connected from this pin to GND is used to control full-scale amplitudes of the video signals.

Rev. C | Page 11 of 64 ADV7170/ADV7171

Input/ Pin No. Mnemonic Output Description 35 SCRESET/RTC I This pin can be configured as an input by setting MR22 and MR21 of Mode Register 2. It can be configured as a subcarrier reset pin, in which case a low-to-high transition on this pin resets the subcarrier to Field 0. Alternatively, it may be configured as a real-time control (RTC) input. 36 TTXREQ O Teletext Data Request Signal. Defaults to GND when teletext not selected. Enables backward compatibility to ADV7175/ADV7176.

37 TTX I Teletext Data. Defaults to VAA when teletext not selected. Enables backward compatibility to ADV7175/ADV7176. 44 CLOCK I TTL Clock Input. Requires a stable 27 MHz reference clock for standard operation. Alternatively, a 24.5454 MHz (NTSC) or 29.5 MHz (PAL) can be used for square pixel operation.

Rev. C | Page 12 of 64 ADV7170/ADV7171

GENERAL DESCRIPTION The ADV7170/ADV7171 are integrated encoders DATA PATH DESCRIPTION that convert digital CCIR-601 4:2:2 8- or 16-bit component For PAL B/D/G/H/I/M/N, and NTSC M and N modes, YcrCb video data into a standard analog signal 4:2:2 data is input via the CCIR-656 compatible pixel port at a compatible with worldwide standards. 27 MHz data rate. The pixel data is demultiplexed to form three data paths. Y typically has a range of 16 to 235; Cr and Cb The on-board SSAF (super sub-alias filter) with extended typically have a range of 128 ± 112. However, it is possible to luminance frequency response and sharp stop band attenuation input data from 1 to 254 on Y, Cb, and Cr. The ADV7170/ enables studio-quality video playback on modern TVs, giving ADV7171 support PAL (B, D, G, H, I, M, N) and NTSC (with optimal horizontal line resolution. and without pedestal) standards. The appropriate SYNC, An advanced power management circuit enables optimal BLANK, and burst levels are added to the YCrCb data. control of power consumption in both normal operating modes Macrovision antitaping (ADV7170 only), closed-captioning, and power-down or sleep modes. and teletext levels are also added to Y, and the resultant data is interpolated to a rate of 27 MHz. The interpolated data is The ADV7170/ADV7171 support both PAL and NTSC square filtered and scaled by three digital FIR filters. pixel operation. The parts also incorporate WSS and CGMS-A data control generation. The U and V signals are modulated by the appropriate sub- carrier sine/cosine phases and added together to make up the The output video frames are synchronized with the incoming chrominance signal. The luma (Y) signal can be delayed 1 to data timing reference . Optionally, the encoder accepts 3 luma cycles (each cycle is 74 ns) with respect to the chroma and can generate HSYNC, VSYNC, and FIELD timing signals. signal. The luma and chroma signals are then added together to These timing signals can be adjusted to change pulse width and make up the composite video signal. All edges are slew rate position while the part is in the master mode. The encoder limited. requires a single, two-times pixel rate (27 MHz) clock for standard operation. Alternatively, the encoder requires a The YCrCb data is also used to generate RGB data with 24.5454 MHz clock for NTSC or 29.5 MHz clock for PAL appropriate SYNC and BLANK levels. The RGB data is in square pixel mode operation. All internal timing is generated synchronization with the composite video output. Alternatively, on-chip. analog YUV data can be generated instead of RGB.

A separate teletext port enables the user to directly input teletext The four 10-bit DACs can be used to output the following: data during the vertical blanking interval. Composite video + RGB video.

The ADV7170/ADV7171 modes are set up over a 2-wire, serial Composite video + YUV video. bidirectional port (I2C-compatible) with two slave addresses. Two composite video signals + LUMA Functionally, the ADV7170 and ADV7171 are the same with the and CHROMA (Y/C) signals. exception that the ADV7170 can output the Macrovision anticopy algorithm. Alternatively, each DAC can be individually powered off if not required. The ADV7170/ADV7171 are packaged in a 44-lead MQFP package and a 44-lead TQFP package. Video output levels are illustrated in Appendix 6—Waveforms.

Rev. C | Page 13 of 64 ADV7170/ADV7171

INTERNAL FILTER RESPONSE The Y filter supports several different frequency responses, including two low-pass responses, two notch responses, an extended (SSAF) response, a CIF response, and a QCIF response. The UV filter supports several different frequency responses, including four low-pass responses, a CIF response, and a QCIF response that are shown in Table 10 and Table 11 and Figure 6 to Figure 18.

Table 10. Luminance Internal Filter Specifications Filter Selection Pass-Band Ripple 3 dB Stop-Band Stop-Band Attenuation Filter Type MR04 MR03 MR02 (dB) (MHz) Cutoff (MHz) (dB) Low Pass (NTSC) 0 0 0 0.091 4.157 7.37 −56 Low Pass (PAL) 0 0 1 0.15 4.74 7.96 −64 Notch (NTSC) 0 1 0 0.015 6.54 8.3 −68 Notch (PAL) 0 1 1 0.095 6.24 8.0 −66 Extended (SSAF) 1 0 0 0.051 6.217 8.0 −61 CIF 1 0 1 0.018 3.0 7.06 −61 QCIF 1 1 0 Monotonic 1.5 7.15 −50

Table 11. Chrominance Internal Filter Specifications Filter Selection Pass-Band Ripple 3 dB Bandwidth Stop-Band Stop-Band Attenuation Filter Type MR07 MR06 MR05 (dB) (MHz) Cutoff (MHz) (dB) 1.3 MHz Low Pass 0 0 0 0.084 1.395 3.01 −45 .65 MHz Low Pass 0 0 1 Monotonic 0.65 3.64 −58.5 1.0 MHz Low Pass 0 1 0 Monotonic 1.0 3.73 −49 2.0 MHz Low Pass 0 1 1 0.0645 2.2 5.0 −40 Reserved 1 0 0 CIF 1 0 1 0.084 0.7 3.01 −45 QCIF 1 1 0 Monotonic 0.5 4.08 −50

Rev. C | Page 14 of 64 ADV7170/ADV7171

TYPICAL PERFORMANCE CHARACTERISTICS 0 0

–10 –10

–20 –20

–30 –30

–40 –40 MAGNITUDE (dB) MAGNITUDE (dB) –50 –50

–60 –60 00221-009 –70 00221-006 –70 0 0 2 4 6 8 10 12 2 4 6 8 10 12 FREQUENCY (MHz) FREQUENCY (MHz) Figure 6. NTSC Low-Pass Luma Filter Figure 9. PAL Notch Luma Filter

0 0

–10 –10

–20 –20

–30 –30

–40 –40 MAGNITUDE (dB) MAGNITUDE (dB) –50 –50

–60 –60

–70 00221-010 –70 00221-007 0 2 4 6 8 10 12 0 2 4 6 8 10 12 FREQUENCY (MHz) FREQUENCY (MHz) Figure 7. PAL Low-Pass Luma Filter Figure 10. Extended Mode (SSAF) Luma Filter

0 0

–10 –10

–20 –20

–30 –30

–40 –40 MAGNITUDE (dB) MAGNITUDE (dB) –50 –50

–60 –60

–70 00221-011 –70 00221-008 0 2 4 6 8 10 12 0 2 4 6 8 10 12 FREQUENCY (MHz) FREQUENCY (MHz) Figure 8. NTSC Notch Luma Filter Figure 11. CIF Luma Filter

Rev. C | Page 15 of 64 ADV7170/ADV7171

0 0

–10 –10

–20 –20

–30 –30

–40 –40 MAGNITUDE (dB) MAGNITUDE (dB) –50 –50

–60 –60

–70 00221-012 –70 00221-015 0 2 4 6 8 10 12 0 2 4 6 8 10 12 FREQUENCY (MHz) FREQUENCY (MHz) Figure 12. QCIF Luma Filter Figure 15. 1.0 MHz Low-Pass Chroma Filter

0 0

–10 –10

–20 –20

–30 –30

–40 –40 MAGNITUDE (dB) MAGNITUDE (dB) –50 –50

–60 –60

–70 00221-013 –70 00221-016 0 2 4 6 8 10 12 0 2 4 6 8 10 12 FREQUENCY (MHz) FREQUENCY (MHz) Figure 13. 1.3 MHz Low-Pass Chroma Filter Figure 16. 2.0 MHz Low-Pass Chroma Filter

0 0

–10 –10

–20 –20

–30 –30

–40 –40 MAGNITUDE (dB) MAGNITUDE (dB) –50 –50

–60 –60

–70 00221-014 –70 00221-017 0 2 4 6 8 10 12 0 2 4 6 8 10 12 FREQUENCY (MHz) FREQUENCY (MHz) Figure 14. 0.65 MHz Low-Pass Chroma Filter Figure 17. CIF Chroma Filter

Rev. C | Page 16 of 64 ADV7170/ADV7171

0

–10

–20

–30

–40 MAGNITUDE (dB) –50

–60

–70 00221-018 0 2 4 6 8 10 12 FREQUENCY (MHz) Figure 18. QCIF Chroma Filter

Rev. C | Page 17 of 64 ADV7170/ADV7171

FEATURES COLOR BAR GENERATION SUBCARRIER RESET The ADV7170/ADV7171 can be configured to generate Together with the SCRESET/RTC pin and Bit MR22 and 100/7.5/75/7.5 color bars for NTSC or 100/0/75/0 color bars Bit MR21 of Mode Register 2, the ADV7170/ADV7171 for PAL. These are enabled by setting MR17 of Mode Register 1 can be used in subcarrier reset mode. The subcarrier resets to Logic Level 1. to Field 0 at the start of the following field when a low-to-high transition occurs on this input pin. SQUARE PIXEL MODE REAL-TIME CONTROL The ADV7170/ADV7171 can be used to operate in square pixel mode. For NTSC operation, an input clock of 24.5454 MHz is Together with the SCRESET/RTC pin and Bit MR22 and required. Alternatively, for PAL operation, an input clock of 29.5 Bit MR21 of Mode Register 2, the ADV7170/ADV7171 can be MHz is required. The internal timing logic adjusts accordingly used to lock to an external video source. The real-time control for square pixel mode operation. When the ADV7171 is mode allows the ADV7170/ADV7171 to automatically alter the configured for PAL square pixel mode, it supports 768 active subcarrier frequency to compensate for line length variation. per line. NTSC square pixel mode supports 640 active When the part is connected to a device that outputs a digital pixels per line. data stream in the RTC format (such as a ADV7185 , shown in Figure 19), the part automatically changes to COLOR SIGNAL CONTROL the compensated subcarrier frequency on a line-by-line basis. The color information can be switched on and off the video This stream is 67 bits wide, and the subcarrier is output using Bit MR24 of Mode Register 2. contained in Bit 0 to Bit 21. Each bit is 2 clock cycles long. 00Hex should be written into all four subcarrier frequency BURST SIGNAL CONTROL registers when using this mode. The burst information can be switched on and off the video VIDEO TIMING DESCRIPTION output using Bit MR25 of Mode Register 2. The ADV7170/ADV7171 are intended to interface to off-the- NTSC PEDESTAL CONTROL shelf MPEG1 and MPEG2 decoders. Consequently, the The pedestal on both odd and even fields can be controlled on a ADV7170/ADV7171 accept 4:2:2 YCrCb pixel data via a line-by-line basis using the NTSC pedestal control registers. CCIR-656 pixel port, and they have several video timing modes This allows the pedestals to be controlled during the vertical of operation that allow them to be configured as either system blanking interval. master video timing generators or as slaves to the system video timing generator. The ADV7170/ADV7171 generate all of the PIXEL TIMING DESCRIPTION required horizontal and vertical timing periods and levels for The ADV7170/ADV7171 operate in either 8-bit or 16-bit the analog video outputs. YCrCb mode. The ADV7170/ADV7171 calculate the width and placement of 8-Bit YCrCb Mode analog sync pulses, blanking levels, and color burst envelopes. This default mode accepts multiplexed YCrCb inputs through Color bursts are disabled on appropriate lines, and serration the P7 to P0 pixel inputs. The inputs follow the sequence Cb0, and equalization pulses are inserted where required. Y0 Cr0, Y1 Cb1, Y2, and so on. The Y, Cb, and Cr data are input In addition, the ADV7170/ADV7171 support a PAL or NTSC on a rising clock edge. square pixel operation in slave mode. The part requires an input 16-Bit YCrCb Mode pixel clock of 24.5454 MHz for NTSC and an input pixel clock of 29.5 MHz for PAL. The internal horizontal line counters place the This mode accepts Y inputs through the P7 to P0 pixel inputs various video waveform sections in the correct location for the new and multiplexed CrCb inputs through the P15 to P8 pixel clock frequencies. inputs. The data is loaded on every second rising edge of CLOCK. The inputs follow the sequence Cb0, Y0 Cr0, Y1 Cb1, The ADV7170/ADV7171 have four distinct master and four Y2, and so on. distinct slave timing configurations. Timing Control is established with the bidirectional SYNC, BLANK, and FIELD/VSYNC pins. Timing Mode Register 1 can also be used to vary the timing pulse widths where they occur in relation to each other.

Rev. C | Page 18 of 64 ADV7170/ADV7171

CLOCK

COMPOSITE VIDEO SCRESET/RTC VIDEO (FOR EXAMPLE, GREEN/LUMA/Y VCR OR CABLE) DECODER (FOR EXAMPLE, ADV7185) P7–P0 RED/CHROMA/V BLUE/COMPOSITE/U

HSYNC COMPOSITE

FIELD/VSYNC

ADV7170/ADV7171

SEQUENCE RESERVED BIT2 H/LTRANSITION 4 BITS 5 BITS RESET COUNT START RESERVED RESERVED BIT3 LOW 14 BITS 128 RESERVED F PLL INCREMENT1 13 0 21 SC 0

RTC

TIME SLOT: 01 14 19 67 68 NOT USED IN ADV7170/ADV7171 VALID INVALID 8/LLC SAMPLE SAMPLE NOTES: 1 FSCPLL INCREMENT IS 22 BITS LONG, VALUE LOADED INTO ADV7170/ADV7171 FSC DDS REGISTER IS FSCPLL INCREMENTS BITS 21:0 PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS OF THE ADV7170/ADV7171. 2SEQUENCE BIT PAL: 0 = LINE NORMAL, 1 = LINE INVERTED NTSC: 0 = NO CHANGE 3RESET BIT RESET ADV7170/ADV7171 DDS 00221-019 Figure 19. RTC Timing and Connections

Vertical Blanking Data Insertion Mode 0 (CCIR-656): Slave Option It is possible to allow encoding of incoming YCbCr data on (Timing Register 0 TR0 = X X X X X 0 0 0) those lines of VBI that do not bear line sync or pre-/post- The ADV7170/ADV7171 are controlled by the SAV (start active equalization pulses (see Figure 21 to Figure 32). This mode of video) and EAV (end active video) time codes in the pixel data. operation is called “partial blanking” and is selected by setting All timing information is transmitted using a 4-byte synchroni- MR32 to 1. It allows the insertion of any VBI data (opened VBI) zation pattern. A synchronization pattern is sent immediately into the encoded output waveform. This data is present in the before and after each line during active picture and retrace. digitized incoming YcbCr data stream (for example, WSS data, Mode 0 is shown in Figure 20. The HSYNC, FIELD/VSYNC, CGMS, VPS, and so on). Alternatively, the entire VBI may be and BLANK (if not used) pins should be tied high during this blanked (no VBI data inserted) on these lines by setting MR32 mode. to 0.

ANALOG VIDEO

EAV SAV CODE C F 0 0 X 8 1 8 1 0 F F A A A 8 1 8 1 F 0 0 X C C C C C Y Y Y Y Y Y INPUT PIXELS r F 0 0 Y 0 0 0 0 0 F F B B B 0 0 0 0 F 0 0 Y b r b r b ANCILLARY DATA (HANC) 4 CLOCK 4 CLOCK NTSC/PAL M SYSTEM 268 CLOCK 1440 CLOCK (525 LINES/60Hz) 4 CLOCK 4 CLOCK PAL SYSTEM 280 CLOCK 1440 CLOCK (625 LINES/50Hz) END OF ACTIVE START OF ACTIVE VIDEO LINE VIDEO LINE 00221-020 Figure 20. Timing Mode 0 (Slave Mode)

Rev. C | Page 19 of 64 ADV7170/ADV7171

Mode 0 (CCIR-656): Master Option (Timing Register 0 TR0 = X X X X X 0 0 1) The ADV7170/ADV7171 generate H, V, and F signals required for the SAV (start active video) and EAV (end active video) time codes in the CCIR656 standard. The H bit is output on the HSYNC pin, the V bit is output on the BLANK pin, and the F bit is output on the FIELD/VSYNC pin. Mode 0 is illustrated in Figure 21 (NTSC) and Figure 22 (PAL). The H, V, and F transitions relative to the video waveform are illustrated in Figure 23.

DISPLAY DISPLAY VERTICAL BLANK

522 523 524 525 1 2 3 4 5 67 8 9 10 11 20 21 22

H

V

F EVEN FIELD ODD FIELD

DISPLAY DISPLAY VERTICAL BLANK

260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285

H

V

F ODD FIELD EVEN FIELD 00221-021 Figure 21. Timing Mode 0 (NTSC Master Mode)

Rev. C | Page 20 of 64 ADV7170/ADV7171

DISPLAY DISPLAY VERTICAL BLANK

622 623 624 625 1 2 3 4 5 67 21 22 23

H

V

F EVEN FIELD ODD FIELD

DISPLAY DISPLAY VERTICAL BLANK

309 310 311 312 313 314 315 316 317 318 319 320 334 335 336

H

V

F ODD FIELD EVEN FIELD 00221-022 Figure 22. Timing Mode 0 (PAL Master Mode)

ANALOG VIDEO

H

F

V

00221-023 Figure 23. Timing Mode 0 Data Transitions (Master Mode)

Rev. C | Page 21 of 64 ADV7170/ADV7171

Mode 1: Slave Option HSYNC, BLANK, FIELD (Timing Register 0 TR0 = X X X X X 0 1 0) In this mode the ADV7170/ADV7171 accept horizontal SYNC and odd/even FIELD signals. A transition of the FIELD input when HSYNC is low indicates a new frame, that is, vertical retrace. The BLANK signal is optional. When the BLANK input is disabled, the ADV7170/ADV7171 automatically blank all normally blank lines as per CCIR-624. Mode 1 is illustrated in Figure 24 (NTSC) and Figure 25 (PAL). DISPLAY DISPLAY VERTICAL BLANK

522 523 524 525 12345 6789 10 11 20 21 22 HSYNC

BLANK

FIELD EVEN FIELD ODD FIELD

DISPLAY DISPLAY VERTICAL BLANK

260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285

HSYNC

BLANK

FIELD ODD FIELD EVEN FIELD 00221-024 Figure 24. Timing Mode 1 (NTSC)

DISPLAY DISPLAY VERTICAL BLANK

622 623 624 625 1 2 3 4 5 67 21 22 23

HSYNC

BLANK

FIELD EVEN FIELD ODD FIELD

DISPLAY DISPLAY VERTICAL BLANK

309 310 311 312 313 314 315 316 317 318 319 320 334 335 336

HSYNC

BLANK

FIELD ODD FIELD EVEN FIELD 00221-025 Figure 25. Timing Mode 1 (PAL)

Rev. C | Page 22 of 64 ADV7170/ADV7171

Mode 1: Master Option HSYNC, BLANK, FIELD (Timing Register 0 TR0 = X X X X X 0 1 1) In this mode the ADV7170/ADV7171 can generate horizontal SYNC and odd/even FIELD signals. A transition of the FIELD input when HSYNC is low indicates a new frame, that is, vertical retrace. The BLANK signal is optional. When the BLANK input is disabled, the ADV7170/ADV7171 automatically blank all normally blank lines as per CCIR-624. Pixel data is latched on the rising clock edge following the timing signal transitions. Mode 1 is shown in Figure 24 (NTSC) and Figure 25 (PAL). Figure 26 illustrates the HSYNC, BLANK, and FIELD for an odd or even field transition relative to the pixel data.

HSYNC

FIELD

PAL = 12 × CLOCK/2 NTSC = 16 × CLOCK/2 BLANK

PIXEL DATA Cb Y Cr Y

PAL = 132 × CLOCK/2

NTSC = 122 × CLOCK/2 00221-026

Figure 26. Timing Mode 1 Odd/Even Field Transitions Master/Slave

Mode 2: Slave Option HSYNC, VSYNC, BLANK (Timing Register 0 TR0 = X X X X X 1 0 0) In this mode the ADV7170/ADV7171 accept horizontal and vertical SYNC signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7170/ADV7171 automatically blank all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 27 (NTSC) and Figure 28 (PAL).

DISPLAY DISPLAY VERTICAL BLANK

522 523 524 525 12345 6789 10 11 20 21 22

HSYNC

BLANK

VSYNC EVEN FIELD ODD FIELD

DISPLAY DISPLAY VERTICAL BLANK

260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285

HSYNC

BLANK

VSYNC ODD FIELD EVEN FIELD 00221-027 Figure 27. Timing Mode 2 (NTSC)

Rev. C | Page 23 of 64 ADV7170/ADV7171

DISPLAY DISPLAY VERTICAL BLANK

622 623 624 625 1 2 3 4 5 67 21 22 23

HSYNC

BLANK

VSYNC EVEN FIELD ODD FIELD

DISPLAY DISPLAY VERTICAL BLANK

309 310 311 312 313 314 315 316 317 318 319 320 334 335 336

HSYNC

BLANK VSYNC ODD FIELD EVEN FIELD

00221-028 Figure 28. Timing Mode 2 (PAL)

Mode 2: Master Option HSYNC, VSYNC, BLANK (Timing Register 0 TR0 = X X X X X 1 0 1) In this mode the ADV7170/ADV7171 can generate horizontal and vertical SYNC signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7170/ADV7171 automatically blank all normally blank lines as per CCIR-624. Mode 2 is shown in Figure 27 (NTSC) and Figure 28 (PAL). Figure 29 shows the HSYNC, BLANK, and VSYNC for an even-to-odd field transition relative to the pixel data. Figure 30 shows the HSYNC, BLANK, and VSYNC for an odd-to-even field transition relative to the pixel data.

HSYNC

VSYNC

PAL = 12 × CLOCK/2 BLANK NTSC = 16 × CLOCK/2

PIXEL Cb Y Cr Y DATA

PAL = 132 × CLOCK/2 NTSC = 122 × CLOCK/2 00221-029 Figure 29. Timing Mode 2 Even-to-Odd Field Transition Master/Slave

HSYNC

VSYNC PAL = 864 × CLOCK/2 NTSC = 858 × CLOCK/2 PAL = 12 × CLOCK/2 NTSC = 16 × CLOCK/2 BLANK

PIXEL Cb Y Cr Y Cb DATA

PAL = 132 × CLOCK/2 NTSC = 122 × CLOCK/2 00221-030 Figure 30. Timing Mode 2 Odd-to-Even Field Transition Master/Slave

Rev. C | Page 24 of 64 ADV7170/ADV7171

Mode 3: Master/Slave Option HSYNC, BLANK, FIELD (Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1) In this mode the ADV7170/ADV7171 accept or generate horizontal SYNC and odd/even FIELD signals. A transition of the FIELD input when HSYNC is high indicates a new frame, that is, vertical retrace. The BLANK signal is optional. When the BLANK input is disabled, the ADV7170/ADV7171 automatically blank all normally blank lines as per CCIR-624. Mode 3 is shown in Figure 31 (NTSC) and Figure 32 (PAL).

DISPLAY DISPLAY VERTICAL BLANK

522 523 524 525 1 2 3 4 5 67 8 9 10 11 20 21 22

HSYNC

BLANK

FIELD EVEN FIELD ODD FIELD

DISPLAY DISPLAY VERTICAL BLANK

260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285

HSYNC

BLANK

FIELD ODD FIELD EVEN FIELD

00221-031 Figure 31. Timing Mode 3 (NTSC)

DISPLAY DISPLAY VERTICAL BLANK

622 623 624 625 1 2 3 4 5 67 21 22 23

HSYNC

BLANK

FIELD EVEN FIELD ODD FIELD

DISPLAY DISPLAY VERTICAL BLANK

309 310 311 312 313 314 315 316 317 318 319 320 334 335 336

HSYNC

BLANK

FIELD ODD FIELD EVEN FIELD 00221-032 Figure 32. Timing Mode 3 (PAL)

Rev. C | Page 25 of 64 ADV7170/ADV7171

POWER-ON RESET 1 10101A1X

After power-up, it is necessary to execute a reset operation. ADDRESS CONTROL A reset occurs on the falling edge of a high-to-low transition SET UP BY on the RESET pin. This initializes the pixel port so that the pixel ALSB READ/WRITE inputs, P7 to P0, are selected. After reset, the ADV7170/ CONTROL ADV7171 is automatically set up to operate in NTSC mode. 0 WRITE 1 READ Subcarrier frequency code 21F07C16HEX is loaded into the 00221-033 Figure 33. ADV7170 Slave Address subcarrier frequency registers. All other registers, with the exception of Mode Register 0, are set to 00H. All bits in Mode Register 0 are set to Logic Level 0, except Bit MR44. Bit MR44 of Mode Register 4 is set to Logic Level 1. This 0 10101A1X enables the 7.5 IRE pedestal. ADDRESS CONTROL SET UP BY SCH PHASE MODE ALSB

The SCH phase is configured in default mode to reset every READ/WRITE CONTROL four (NTSC) or eight (PAL) fields to avoid an accumulation of 0 WRITE 1 READ SCH phase error over time. In an ideal system, zero SCH phase 00221-034 error would be maintained forever, but in reality, this is Figure 34. ADV7171 Slave Address impossible to achieve due to clock frequency variations. This effect is reduced by the use of a 32-bit DDS, which generates this SCH. To control the various devices on the bus, the following protocol must be followed: first, the master initiates a data Resetting the SCH phase every four or eight fields avoids the transfer by establishing a start condition, defined by a high-to- accumulation of SCH phase error and results in very minor low transition on SDATA while SCLOCK remains high. This SCH phase jumps at the start of the four or eight field sequence. indicates that an address/data stream follows. All peripherals Resetting the SCH phase should not be done if the video source respond to the start condition and shift the next eight bits does not have stable timing or the ADV7170/ADV7171 are (7-bit address + R/RW bit). The bits transfer from MSB down to configured in RTC mode (MR21 = 1 and MR22 = 1). Under LSB. The peripheral that recognizes the transmitted address these conditions (unstable video), the subcarrier phase reset responds by pulling the data line low during the ninth clock should be enabled (MR22 = 0 and MR21 = 1) but no reset pulse. This is known as an acknowledge bit. All other devices applied. In this configuration the SCH phase is never reset, withdraw from the bus at this point and maintain an idle which means the output video tracks the unstable input video. condition. The idle condition is where the device monitors the The subcarrier phase reset, when applied, resets the SCH phase SDATA and SCLOCK lines waiting for the start condition and to Field 0 at the start of the next field (for example, subcarrier the correct transmitted address. The R/RW bit determines the phase reset applied in Field 5 [PAL] on the start of the next field direction of the data. A Logic Level 0 on the LSB of the first byte SCH phase resets to Field 0). means that the master writes information to the peripheral. A Logic Level 1 on the LSB of the first byte means the master MPU PORT DESCRIPTION reads information from the peripheral. The ADV7170/ADV7171 support a 2-wire, serial (I2C- compatible) microprocessor bus driving multiple peripherals. Two inputs, serial data (SDATA), and serial clock (SCLOCK), carry information between any devices connected to the bus. Each slave device is recognized by a unique address. The ADV7170/ADV7171 each have four possible slave addresses for both read and write operations. These are unique addresses for each device and are shown in Figure 33 and Figure 34. The LSB sets either a read or write operation. Logic Level 1 corresponds to a read operation, while Logic Level 0 corre- sponds to a write operation. A 1 is set by setting the ALSB pin of the ADV7170/ADV7171 to Logic Level 0 or Logic Level 1.

Rev. C | Page 26 of 64 ADV7170/ADV7171

The ADV7170/ADV7171 act as standard slave devices on the REGISTER ACCESSES bus. The data on the SDATA pin is eight bits long, supporting The MPU can write to or read from all of the ADV7170/ the 7-bit addresses plus the R/RW bit. The ADV7170 has 48 ADV7171 registers except the subaddress register, which is a subaddresses, and the ADV7171 has 26 subaddresses to enable write-only register. The subaddress register determines which access to the internal registers. It therefore interprets the first register the next read or write operation accesses. All commu- byte as the device address and the second byte as the starting nications with the part through the bus start with an access to subaddress. The subaddresses’ auto-increment allows data to be the subaddress register. A read/write operation is performed written to or read from the starting subaddress. A data transfer from/to the target address, which then increments to the next is always terminated by a stop condition. The user can also address until a stop command on the bus is performed. access any unique subaddress register on a one-by-one basis without having to update all the registers. There is one exception. The subcarrier frequency registers should be updated in sequence, starting with Subcarrier Frequency Register 0. The auto-increment function should then be used to increment and access Subcarrier Frequency Register 1, Subcarrier Frequency Register 2, and Subcarrier Frequency Register 3. The subcarrier frequency registers should not be accessed independently.

Stop and start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, they cause an immediate jump to the idle condition. During a given SCLOCK high period, the user should issue only one start condition, one stop condition, or a single stop condition followed by a single start condition. If an invalid subaddress is issued by the user, the ADV7170/ADV7171 do not issue an acknowledge, and they return to the idle condition. If in auto-increment mode the user exceeds the highest subaddress, the following action is taken:

In read mode, the highest subaddress register contents continue to be output until the master device issues a no- acknowledge. This indicates the end of a read. A no- acknowledge condition is where the SDATA line is not pulled low on the ninth pulse.

In write mode, the data for the invalid byte is not loaded into any subaddress register, a no-acknowledge is issued by the ADV7170/ADV7171, and the part returns to the idle condition.

Figure 35 illustrates an example of data transfer for a read sequence and the start and stop conditions.

Figure 36 shows bus write and read sequences.

SDATA

SCLOCK S 1–7 8 9 1–7 8 9 1–7 8 9 P START ADDR R/W ACK SUBADDRESS ACK DATA ACK STOP 00221-035 Figure 35. Bus Data Transfer

Rev. C | Page 27 of 64 ADV7170/ADV7171

REGISTER PROGRAMMING This section describes each register, including subaddress MODE REGISTER 0 MR0 (MR07 TO MR00) register, mode registers, subcarrier frequency registers, (Address [SR4 to SR0] = 00H) subcarrier phase register, timing registers, closed captioning Figure 38 shows the various operations under the control of extended data registers, closed captioning data registers, and Mode Register 0. This register can be read from as well as NTSC pedestal control registers, in terms of its configuration. written to. SUBADDRESS REGISTER (SR7 TO SR0) MR0 BIT DESCRIPTION The communications register is an 8-bit, write-only register. Output Video Standard Selection (MR01 to MR00) After the part has been accessed over the bus and a read/write operation is selected, the subaddress is set up. The subaddress These bits are used to set up the encode mode. The ADV7170/ register determines to/from which register the operation takes ADV7171 can be set up to output NTSC, PAL B/D/G/H/I, and place. PAL M/N standard video. Luminance Filter Control (MR02 to MR04) Figure 37 shows the various operations under the control of the subaddress register. Zero should always be written to SR7 to SR6. These bits specify which luma filter is to be selected. The filter selection is made independent of whether PAL or NTSC is REGISTER SELECT (SR5 TO SR0) selected. These bits are set up to point to the required starting address. Chrominance Filter Control (MR05 to MR07) These bits select the chrominance filter. A low-pass filter can be selected with a choice of cutoff frequencies, 0.65 MHz, 1.0 MHz, 1.3 MHz, or 2 MHz, along with a choice of CIF or QCIF filters.

WRITE S SLAVE ADDR A(S) SUBADDR A(S) DATA A(S) DATA A(S) P SEQUENCE

LSB = 0 LSB = 1

READ S SLAVE ADDR A(S) SUBADDR A(S) S SLAVE ADDR A(S) DATA A(M) DATA A(M) P SEQUENCE S = START BIT A(S) = ACKNOWLEDGE BY SLAVE A (S) = NO-ACKNOWLEDGE BY SLAVE P = STOP BIT A(M) = ACKNOWLEDGE BY MASTER A (M) = NO-ACKNOWLEDGE BY MASTER 00221-036 Figure 36. Write and Read Sequences

Rev. C | Page 28 of 64 ADV7170/ADV7171

SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0

SR7–SR5 (000) ZERO SHOULD BE WRITTEN TO THESE BITS

ADV7171 SUBADDRESS REGISTER ADV7170 SUBADDRESS REGISTER POWER-UP/ POWER-UP/ SR5 SR4 SR3 SR2 SR1 SR0 RESET VALUE SR5 SR4 SR3 SR2 SR1 SR0 RESET VALUE (HEX) (HEX) 0 0 0 0 0 0 MODE REGISTER 0 00 000000MODE REGISTER 0 00 0 0 0 0 0 1 MODE REGISTER 1 58 0 0 0 0 0 1 MODE REGISTER 1 58 0 0 0 0 1 0 MODE REGISTER 2 00 0 0 0 0 1 0 MODE REGISTER 2 00 0 0 0 0 1 1 MODE REGISTER 3 00 0 0 0 0 1 1 MODE REGISTER 3 00 0 0 0 1 0 0 MODE REGISTER 4 10 0 0 0 1 0 0 MODE REGISTER 4 10 0 0 0 1 0 1 RESERVED 00 0 0 0 1 0 1 RESERVED 00 0 0 0 1 1 0 RESERVED 00 0 0 0 1 1 0 RESERVED 00 0 0 0 1 1 1 TIMING MODE REGISTER 0 00 0 0 0 1 1 1 TIMING MODE REGISTER 0 00 0 0 1 0 0 0 TIMING MODE REGISTER 1 00 0 0 1 0 0 0 TIMING MODE REGISTER 1 00 0 0 1 0 0 1 SUBCARRIER FREQUENCY REGISTER 0 16* 0 0 1 0 0 1 SUBCARRIER FREQUENCY REGISTER 0 16* 0 0 1 0 1 0 SUBCARRIER FREQUENCY REGISTER 1 7C 0 0 1 0 1 0 SUBCARRIER FREQUENCY REGISTER 1 7C 0 0 1 0 1 1 SUBCARRIER FREQUENCY REGISTER 2 F0 0 0 1 0 1 1 SUBCARRIER FREQUENCY REGISTER 2 F0 0 0 1 1 0 0 SUBCARRIER FREQUENCY REGISTER 3 21 0 0 1 1 0 0 SUBCARRIER FREQUENCY REGISTER 3 21 0 0 1 1 0 1 SUBCARRIER PHASE REGISTER 00 0 0 1 1 0 1 SUBCARRIER PHASE REGISTER 00 0 0 1 1 1 0 CLOSED CAPTIONING EXTENDED DATA BYTE 0 00 0 0 1 1 1 0 CLOSED CAPTIONING EXTENDED DATA BYTE 0 00 0 0 1 1 1 1 CLOSED CAPTIONING EXTENDED DATA BYTE 1 00 0 0 1 1 1 1 CLOSED CAPTIONING EXTENDED DATA BYTE 1 00 0 1 0 0 0 0 CLOSED CAPTIONING DATA BYTE 0 00 0 1 0 0 0 0 CLOSED CAPTIONING DATA BYTE 0 00 0 1 0 0 0 1 CLOSED CAPTIONING DATA BYTE 1 00 0 1 0 0 0 1 CLOSED CAPTIONING DATA BYTE 1 00 NTSC PEDESTAL CONTROL REG 0/ 010010 00 010010NTSC PEDESTAL CONTROL REG 0/ 00 PAL TTX CONTROL REG 0 PAL TTX CONTROL REG 0 NTSC PEDESTAL CONTROL REG 1/ 00 010011NTSC PEDESTAL CONTROL REG 1/ 00 010011PAL TTX CONTROL REG 1 PAL TTX CONTROL REG 1

NTSC PEDESTAL CONTROL REG 2/ 010100NTSC PEDESTAL CONTROL REG 2/ 00 010100PAL TTX CONTROL REG 2 00 PAL TTX CONTROL REG 2

NTSC PEDESTAL CONTROL REG 3/ 010101NTSC PEDESTAL CONTROL REG 3/ 00 010101PAL TTX CONTROL REG 3 00 PAL TTX CONTROL REG 3 0 1 0 1 1 0 CGMS_WSS_0 00 0 1 0 1 1 0 CGMS_WSS_0 00 0 1 0 1 1 1 CGMS_WSS_1 00 0 1 0 1 1 1 CGMS_WSS_1 00 0 1 1 0 0 0 CGMS_WSS_2 00 0 1 1 0 0 0 CGMS_WSS_2 00 0 1 1 0 0 1 TELETEXT REQUEST CONTROL REGISTER 00 0 1 1 0 0 1 TELETEXT REQUEST CONTROL REGISTER 00 0 1 1 0 1 0 RESERVED 00 0 1 1 0 1 1 RESERVED 00 0 1 1 1 0 0 RESERVED 00 0 1 1 1 0 1 RESERVED 00 0 1 1 1 1 0 MACROVISION REGISTERS 00 0 1 1 1 1 1 MACROVISION REGISTERS 00 1 0 0 0 0 0 MACROVISION REGISTERS 00 1 0 0 0 0 1 MACROVISION REGISTERS 00 1 0 0 0 1 0 MACROVISION REGISTERS 00 1 0 0 0 1 1 MACROVISION REGISTERS 00 *SUBCARRIER FREQUENCY REGISTER 0 = 16 IS 1 0 0 1 0 0 MACROVISION REGISTERS 00 INCORRECT ON POWER-UP FOR NTSC. THIS REGISTER SHOULD BE PROGRAMMED TO 1F FOR ACCURATE FSC. 1 0 0 1 0 1 MACROVISION REGISTERS 00 1 0 0 1 1 0 MACROVISION REGISTERS 00 1 0 0 1 1 1 MACROVISION REGISTERS 00 1 0 1 0 0 0 MACROVISION REGISTERS 00 1 0 1 0 0 1 MACROVISION REGISTERS 00 1 0 1 0 1 0 MACROVISION REGISTERS 00 1 0 1 0 1 1 MACROVISION REGISTERS 00 1 0 1 1 0 0 MACROVISION REGISTERS 00 1 0 1 1 0 1 MACROVISION REGISTERS 00 1 0 1 1 1 0 MACROVISION REGISTERS 00 1 0 1 1 1 1 MACROVISION REGISTERS 00 00221-037 Figure 37. Subaddress Register Map

Rev. C | Page 29 of 64 ADV7170/ADV7171

MR07 MR06 MR05 MR04 MR03 MR02 MR01 MR00

CHROMA FILTER SELECT OUTPUT VIDEO STANDARD SELECTION MR07 MR06 MR05 0001.3MHz LOW PASS FILTER MR01 MR00 0010.65MHz LOW PASS FILTER 00NTSC 0101.0MHz LOW PASS FILTER 01PAL (B, D, G, H, I) 0112.0MHz LOW PASS FILTER 10PAL (M) 100RESERVED 11RESERVED 101CIF 110Q CIF LUMA FILTER SELECT 111RESERVED MR04 MR03 MR02 000LOW PASS FILTER (NTSC) 001LOW PASS FILTER (PAL) 010NOTCH FILTER (NTSC) 001NOTCH FILTER (PAL) 100EXTENDED MODE 101CIF 110Q CIF 111RESERVED 00221-038 Figure 38. Mode Register 0 Color Bar Control (MR17) MODE REGISTER 1 MR1 (MR17 TO MR10) This bit can be used to generate and output an internal color bar (Address (SR4 to SR0) = 01H) test pattern. The color bar configuration is 100/7.5/75/7.5 for Figure 39 shows the various operations under the control of NTSC and 100/0/75/0 for PAL. It is important to note that when Mode Register 1. This register can be read from as well as color bars are enabled, the ADV7170/ADV7171 are configured written to. in a master timing mode. MR1 BIT DESCRIPTION MODE REGISTER 2 MR2 (MR27 TO MR20) Interlace Control (MR10) (Address [SR4 to SR0] = 02H) This bit is used to set up the output to interlaced or noninter- Mode Register 2 is an 8-bit-wide register. laced mode. This mode is only relevant when the part is in composite video mode. Figure 40 shows the various operations under the control of Mode Register 2. This register can be read from as well as Closed Captioning Field Selection (MR12 to MR11) written to. These bits control the fields on which closed captioning data is MR2 BIT DESCRIPTION displayed. Closed captioning information can be displayed on an odd field, even field, or both odd and even fields. Square Pixel Control (MR20) This bit is used to set up square pixel mode. This is available in DAC Control (MR16 to MR13) slave mode only. For NTSC, a 24.5454 MHz clock must be These bits can be used to power down the DACs. This can be supplied. For PAL, a 29.5 MHz clock must be supplied. used to reduce the power consumption of the ADV7170/ ADV7171 if any of the DACs are not required in the application.

Rev. C | Page 30 of 64 ADV7170/ADV7171

MR17 MR16 MR15 MR14 MR13 MR12 MR11 MR10

DAC A DAC D CLOSED CAPTIONING CONTROL CONTROL FIELD SELECTION MR16 MR14 MR12 MR11 0 NORMAL 0 NORMAL 0 0 NO DATA OUT 1 POWER-DOWN 1 POWER-DOWN 0 1 ODD FIELD ONLY 1 0 EVEN FIELD ONLY 1 1 DATA OUT (BOTH FIELDS)

COLOR BAR DAC B DAC C INTERLACE CONTROL CONTROL CONTROL CONTROL MR17 MR15 MR13 MR10 0 DISABLE 0 NORMAL 0 NORMAL 0 INTERLACED 1 ENABLE 1 POWER-DOWN 1 POWER-DOWN 1 NONINTERLACED 00221-039 Figure 39. Mode Register 1

MR27 MR26 MR25 MR24 MR23 MR22 MR21 MR20

CHROMINANCE GENLOCK CONTROL LOW POWER MODE CONTROL MR22 MR21 MR26 MR24 x 0 DISABLE GENLOCK 0 DISABLE 0 ENABLE COLOR 0 1 ENABLE SUBCARRIER 1 ENABLE 1 DISABLE COLOR RESET PIN 1 1 ENABLE RTC PIN

MR27 BURST ACTIVE VIDEO LINE SQUARE PIXEL CONTROL DURATION CONTROL RESERVED MR25 MR23 MR20 0 ENABLE BURST 0 720 PIXELS 0 DISABLE 1 DISABLE BURST 1 710 PIXELS/702 PIXELS 1 ENABLE 00221-040 Figure 40. Mode Register 2

MR37 MR36 MR35 MR34 MR33 MR32 MR31 MR30

TTXRQ BIT CHROMA OUTPUT VBI_OPEN MODE CONTROL SELECT MR30 MR32 MR31 MR36 MR34 0 DISABLE RESERVED 0 NORMAL 0 DISABLE 1 ENABLE 1 BIT REQUEST 1 ENABLE

INPUT DEFAULT TELETEXT DAC OUTPUT COLOR ENABLE MR37 MR35 MR33 DAC A DAC B DAC C DAC D 0 DISABLE 0 DISABLE 0 COMPOSITE BLUE/COMP/U RED/CHROMA/V GREEN/LUMA/Y 1 ENABLE 1 ENABLE 1 GREEN/LUMA/Y BLUE/COMP/U RED/CHROMA/V COMPOSITE 00221-041 Figure 41. Mode Register 3

Genlock Control (MR22 to MR21) a 1 selects ITU-R.BT470 standard for active video duration (710 pixels NTSC; 702 pixels PAL). These bits control the genlock feature of the ADV7170/ ADV7171. Setting MR21 to a Logic Level 1 configures the Chrominance Control (MR24) SCRESET/RTC pin as an input. Setting MR22 to Logic Level 0 This bit enables the color information to be switched on and off configures the SCRESET/RTC pin as a subcarrier reset input. the video output. Therefore, the subcarrier resets to Field 0 following a low-to- high transition on the SCRESET/RTC pin. Setting MR22 to Burst Control (MR25) Logic Level 1 configures the SCRESET/RTC pin as a real-time This bit enables the burst information to be switched on and off the control input. video output. Active Video Line Duration (MR23) Low Power Mode (MR26) This bit switches between two active video line durations. This bit enables the lower power mode of the ADV7170/ A 0 selects CCIR REC601 (720 pixels PAL/NTSC), and ADV7171, reducing the DAC current by 45%. Rev. C | Page 31 of 64 ADV7170/ADV7171

Reserved (MR27) DAC Output (MR33) A Logic Level 0 must be written to this bit. This bit is used to switch the DAC outputs from SCART to a EUROSCART configuration. A complete table of all DAC output MODE REGISTER 3 MR3 (MR37 TO MR30) configurations is shown in Table 12. (Address [SR4 to SR0] = 03H) Chroma Output Select (MR34) Mode Register 3 is an 8-bit-wide register. Figure 41 shows the With this active high bit it is possible to output YUV data with a various operations under the control of Mode Register 3. composite output on the fourth DAC or a chroma output on the MR3 BIT DESCRIPTION fourth DAC (0 = CVBS; 1 = CHROMA). Revision Code (MR30 to MR31) Teletext Enable (MR35) These bits are read-only and indicate the revision of the device. This bit must be set to 1 to enable teletext data insertion on the VBI Open (MR32) TTX pin. This bit determines whether or not data in the vertical blanking TTXREQ Bit Mode Control (MR36) interval (VBI) is output to the analog outputs or blanked. VBI This bit enables switching of the teletext request signal from a data insertion is not available in Slave Mode 0. Also, when both continuous high signal (MR36 = 0) to a bit wise request signal BLANK input control and VBI-open are enabled, BLANK input (MR36 = 1). control has priority; that is, VBI data insertion does not work. Input Default Color (MR37) This bit determines the default output color from the DACs for zero input pixel data (or disconnected). A Logic Level 0 means that the color corresponding to 00000000 is displayed. A Logic Level 1 forces the output color to for 00000000 pixel input video data.

Table 12. DAC Output Configuration Matrix MR34 MR40 MR41 MR33 DAC A DAC B DAC C DAC D Simultaneous Output 0 0 0 0 CVBS CVBS C Y 2 composite and Y/C 0 0 0 1 Y CVBS C CVBS 2 composite and Y/C 0 0 1 0 CVBS CVBS C Y 2 composite and Y/C 0 0 1 1 Y CVBS C CVBS 2 composite and Y/C 0 1 0 0 CVBS B R G RGB and composite 0 1 0 1 G B R CVBS RGB and composite 0 1 1 0 CVBS U V Y YUV and composite 0 1 1 1 Y U V CVBS YUV and composite 1 0 0 0 C CVBS C Y 1 composite, Y and 2C 1 0 0 1 Y CVBS C C 1 composite, Y and 2C 1 0 1 0 C CVBS C Y 1 composite, Y and 2C 1 0 1 1 Y CVBS C C 1 composite, Y and 2C 1 1 0 0 C B R G RGB and C 1 1 0 1 G B R C RGB and C 1 1 1 0 C U V Y YUV and C 1 1 1 1 Y U V C YUV and C

CVBS: Composite video baseband signal Y: Luminance component signal (for YUV or Y/C mode) C: Chrominance signal (for Y/C mode) U: Chrominance component signal (for YUV mode) V: Chrominance component signal (for YUV mode) R: RED (for RGB mode) G: GREEN Component video (for RGB mode) B: BLUE Component video (for RGB mode) Each DAC can be powered on or off individually with the following control bits (0 = ON; 1 = OFF): MR13-DAC C MR14-DAC D MR15-DAC B MR16-DAC A

Rev. C | Page 32 of 64 ADV7170/ADV7171

MR47 MR46 MR45 MR44 MR43 MR42 MR41 MR40

SLEEP MODE PEDESTAL RGB SYNC OUTPUT SELECT CONTROL CONTROL MR42 MR40 MR46 MR44 0 DISABLE 0 YC OUTPUT 0 DISABLE 0 PEDESTAL OFF 1 ENABLE 1 RGB/YUV OUTPUT 1 ENABLE 1 PEDESTAL ON

MR47 ACTIVE VIDEO VSYNC_3H RGB/YUV (0) FILTER CONTROL CONTROL MR43 MR45 MR41 ZERO SHOULD 0 DISABLE BE WRITTEN TO 0 DISABLE 1 ENABLE 0 RGB OUTPUT THIS BIT 1 ENABLE 1 YUV OUTPUT 00221-042 Figure 42. Mode Register 4

MODE REGISTER 4 MR4 (MR47 TO MR40) Active Video Filter Control (MR45) (Address (SR4 to SR0) = 04H) This bit controls the filter mode applied outside the active video Mode Register 4 is an 8-bit-wide register. Figure 42 shows the portion of the line. This filter ensures that the sync rise and fall various operations under the control of Mode Register 4. times are always on spec regardless of which luma filter is selected. This mode is enabled by a Logic Level 1. MR4 BIT DESCRIPTION Output Select (MR40) Sleep Mode Control (MR46) This bit specifies if the part is in composite video mode or When this bit is set to 1, sleep mode is enabled. With this mode RGB/YUV mode. Note that in RGB/YUV mode the composite enabled, power consumption of the ADV7170/ADV7171 is 2 signal is still available. reduced to typically 200 nA. The I C registers can be written to and read from when the ADV7170/ADV7171 are in sleep RGB/YUV Control (MR41) mode. If MR46 is set to a 0 when the device is in sleep mode, This bit enables the output from the RGB DACs to be set to the ADV7170/ADV7171 come out of sleep mode and resume YUV output video standard. normal operation. Also, if the RESET signal is applied during sleep mode, the ADV7170/ADV7171 come out of sleep mode RGB Sync (MR42) and resume normal operation. This bit is used to set up the RGB outputs with the sync information encoded on all RGB outputs. Reserved (MR47) A Logic Level 0 should be written to this bit. VSYNC_3H (MR43) When this bit is enabled (1) in slave mode, it is possible to TIMING MODE REGISTER 0 (TR07 TO TR00) drive the VSYNC active low input for 2.5 lines in PAL mode and (Address [SR4 to SR0] = 07H) 3 lines in NTSC mode. When this bit is enabled in master Figure 43 shows the various operations under the control of mode, the ADV7170/ADV7171 output an active low VSYNC Timing Register 0. This register can be read from as well as signal for 3 lines in NTSC mode and 2.5 lines in PAL mode. written to. Pedestal Control (MR44) This bit specifies whether a pedestal is to be generated on the NTSC composite video signal. This bit is invalid if the ADV7170/ADV7171 are configured in PAL mode.

Rev. C | Page 33 of 64 ADV7170/ADV7171

TR07 TR06 TR05 TR04 TR03 TR02 TR01 TR00

TIMING BLANK INPUT MASTER/SLAVE REGISTER RESET CONTROL CONTROL TR03 TR00 TR07 0 ENABLE 0 SLAVE TIMING 1 DISABLE 1 MASTER TIMING

PIXEL PORT LUMA DELAY TIMING MODE CONTROL SELECTION TR05 TR04 TR06 TR02 TR01 0 0 0ns DELAY 0 8 BIT 0 1 74ns DELAY 0 0 MODE 0 1 16 BIT 1 0 148ns DELAY 0 1 MODE 1 1 1 222ns DELAY 1 0 MODE 2 1 1 MODE 3 00221-043 Figure 43. Timing Register 0

TR0 BIT DESCRIPTION TIMING MODE REGISTER 1 (TR17 TO TR10) Master/Slave Control (TR00) (Address (SR4 to SR0) = 08H) This bit controls whether the ADV7170/ADV7171 is in Timing Register 1 is an 8-bit-wide register. Master or Slave Mode. Figure 44 shows the various operations under the control of Timing Mode Selection (TR02 to TR01) Timing Register 1. This register can be read from as well written to. This register can be used to adjust the width and position of These bits control the timing mode of the ADV7170/ ADV7171. the master mode timing signals. These modes are described in more detail in the Timing and Control section. TR1 BIT DESCRIPTION BLANK Control (TR03) HSYNC Width (TR11 to TR10) This bit controls whether the BLANK input is used when the These bits adjust the HSYNC pulse width. part is in slave mode. HSYNC to FIELD/VSYNC Delay (TR13 to TR12) Luma Delay (TR05 to TR04) These bits adjust the position of the HSYNC output relative to These bits control the addition of a luminance delay. Each bit the FIELD/VSYNC output. represents a delay of 74 ns. HSYNC to FIELD Rising Edge Delay (TR15 to TR14) Pixel Port Control (TR06) When the ADV7170/ADV7171 are in Timing Mode 1, these This bit is used to set the pixel port to accept 8-bit or 16-bit bits adjust the position of the HSYNC output relative to the data. If an 8-bit input is selected, the data will be set up on FIELD output rising edge. Pin P7 to Pin P0. VSYNC Width (TR15 to TR14) Timing Register Reset (TR07) When the ADV7170/ADV7171 are configured in Timing Toggling TR07 from low to high and low again resets the Mode 2, these bits adjust the VSYNC pulse width. internal timing counters. This bit should be toggled after power-up, reset or changing to a new timing mode. HSYNC to Pixel Data Adjust (TR17 to TR16) This enables the HSYNC to be adjusted with respect to the pixel data. This allows the Cr and Cb components to be swapped. This adjustment is available in both master timing mode and slave timing mode.

Rev. C | Page 34 of 64 ADV7170/ADV7171

TR17 TR16 TR15 TR14 TR13 TR12 TR11 TR10

HSYNC TO PIXEL HSYNC TO FIELD HSYNC TO HSYNC WIDTH DATA ADJUST RISING EDGE DELAY FIELD/VSYNC DELAY T (MODE 1 ONLY) TR11 TR10 A TR17 TR16 T TR13 TR12 B 001× TPCLK TR15 TR14 TC 000× TPCLK 000 × TPCLK 014× TPCLK x0T 011× TPCLK B 014 × TPCLK 1016× TPCLK x1TB + 32μs 102× TPCLK 108 × TPCLK 1 1 128 × TPCLK 113× TPCLK 1116 × TPCLK VSYNC WIDTH (MODE 2 ONLY) TR15 TR14

001× TPCLK 014× TPCLK 1016× TPCLK 1 1 128 × TPCLK

TIMING MODE 1 (MASTER/PAL) LINE 1 LINE 313 LINE 314

HSYNC TA

T TB C

FIELD/VSYNC 00221-044 Figure 44. Timing Register 1

SUBCARRIER FREQUENCY REGISTERS 0 TO 3 SUBCARRIER PHASE REGISTERS (FP7 TO FP0) (FSC3 TO FSC0) (Address [SR4 to SR0] = 0DH) (Address [SR4 to SR00] = 09H to 0CH) This 8-bit-wide register is used to set up the subcarrier phase. These 8-bit-wide registers are used to set up the subcarrier Each bit represents 1.41°. For normal operation this register is frequency. The value of these registers is calculated by using set to 00Hex. the following equation, rounded to the nearest integer: CLOSED CAPTIONING EVEN FIELD DATA .ofNo Subcarrier Frequency LineVideoofLineOneinValues × 232 REGISTER 1 TO 0 (CED15 TO CED0) 27. ClockMHzofNo LineVideoOneinCycles (Address [SR4–SR0] = 0E to 0FH) For example, in NTSC mode, These 8-bit-wide registers are used to set up the closed captioning extended data bytes on even fields. Figure 46 5.227 Subcarrier alueVFrequency 232 =×= 569408542 = 10721 FhCFd shows how the high and low bytes are set up in the registers. 1716

BYTE 1 CED15 CED14 CED13CED12 CED11 CED10 CED9 CED8 Note that on power-up, FSC Register 0 is set to 16h. A value of 1F as derived above is recommended. BYTE 0 CED7 CED6 CED5 CED4 CED3 CED2 CED1 CED0

00221-046 Program as follows: Figure 46. Closed Captioning Extended Data Register FSC Register 0: 1FH CLOSED CAPTIONING ODD FIELD DATA FSC Register 2: 7CH REGISTERS 1 TO 0 (CCD15 TO CCD0) FSC Register 3: F0H (Subaddress [SR4 to SR0] = 10H to 11H) FSC Register 4: 21H These 8-bit-wide registers are used to set up the closed Figure 45 shows how the frequency is set up by the four registers. captioning data bytes on odd fields. Figure 47 shows how the high and low bytes are set up in the registers. SUBCARRIER FREQUENCY FSC7 FSC6 FSC5 FSC4 FSC3 FSC2 FSC1 FSC0 REG 0 BYTE 1 CCD15 CCD14 CCD13CCD12 CCD11 CCD10 CCD9 CCD8 SUBCARRIER FREQUENCY FSC15 FSC14 FSC13 FSC12 FSC11 FSC10 FSC9 FSC8 REG 1 BYTE 0 CCD7 CCD6 CCD5 CCD4 CCD3 CCD2 CCD1 CCD0 SUBCARRIER 00221-047 FREQUENCY FSC23 FSC22 FSC21FSC20 FSC19FSC18 FSC17 FSC16 Figure 47. Closed Captioning Data Register REG 2

SUBCARRIER FREQUENCY FSC31 FSC30 FSC29 FSC28 FSC27FSC26 FSC25 FSC24

REG 3 00221-045

Figure 45. Subcarrier Frequency Register

Rev. C | Page 35 of 64 ADV7170/ADV7171

NTSC PEDESTAL/PAL TELETEXT CONTROL TTXREQ Rising Edge Control (TC07 to TC04) REGISTERS 3 TO 0 (PCE15 TO PCE0, PCO15 These bits control the position of the rising edge of TTXREQ. TO PCO0)/(TXE15 TO TXE0, TXO15 TO TXO0) It can be programmed from zero CLOCK cycles to a maximum (Subaddress [SR4–SR0] = 12H to 15H) of 15 CLOCK cycles. See Figure 59. These 8-bit-wide registers are used to enable the NTSC TTXREQ Falling Edge Control (TC03 to TC00) pedestal/PAL teletext on a line-by-line basis in the vertical These bits control the position of the falling edge of TTXREQ. blanking interval for both odd and even fields. Figure 48 and It can be programmed from zero CLOCK cycles to a max of Figure 49 show the four control registers. A Logic Level 1 in any 15 CLOCK cycles. This controls the active window for teletext of the bits of these registers has the effect of turning the pedestal data. Increasing this value reduces the amount of teletext bits off on the equivalent line when used in NTSC. A Logic Level 1 below the default of 360. If Bit TC03 to Bit TC00 are 00Hex in any of the bits of these registers has the effect of turning on when bits TC07 to TC04 are changed, the falling edge of teletext on the equivalent line when used in PAL. TTXREQ tracks that of the rising edge (that is, the time LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 between the falling and rising edge remains constant). FIELD 1/3 PCO7 PCO6 PCO5 PCO4 PCO3 PCO2 PCO1 PCO0 See Figure 59. LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 CGMS_WSS REGISTER 0 C/W0 (C/W07 TO C/W00) FIELD 1/3 PCO15 PCO14 PCO13 PCO12 PCO11 PCO10 PCO9 PCO8 (Address [SR4 to SR0] = 16H) LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 CGMS_WSS Register 0 is an 8-bit-wide register. Figure 51 FIELD 2/4 PCE7 PCE6 PCE5 PCE4 PCE3 PCE2 PCE1 PCE0 shows the operations under the control of this register. LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 FIELD 2/4 PCE15 PCE14 PCE13 PCE12 PCE11 PCE10 PCE9 PCE8 C/W0 BIT DESCRIPTION 00221-048 Figure 48. Pedestal Control Registers CGMS Data Bits (C/W03 to C/W00)

These four data bits are the final four bits of the CGMS data

LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9 LINE 8 LINE 7 output stream. Note it is CGMS data ONLY in these bit

FIELD 1/3 TXO7 TXO6 TXO5 TXO4 TXO3 TXO2 TXO1 TXO0 positions; that is, WSS data does not share this location.

LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15 CGMS CRC Check Control (C/W04) FIELD 1/3 TXO15 TXO14 TXO13 TXO12 TXO11 TXO10 TXO9 TXO8 When this bit is enabled (1), the last six bits of the CGMS data (that is, the CRC check sequence) are calculated internally by LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9 LINE 8 LINE 7 FIELD 2/4 TXE7 TXE6 TXE5 TXE4 TXE3 TXE2 TXE1 TXE0 the ADV7170/ADV7171. If this bit is disabled (0), the CRC values in the register are output to the CGMS data stream. LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15 FIELD 2/4 TXE15 TXE14 TXE13 TXE12 TXE11 TXE10 TXE9 TXE8 CGMS Odd Field Control (C/W05) 00221-049 Figure 49. Teletext Control Registers When this bit is set (1), CGMS is enabled for odd fields. Note TELETEXT REQUEST CONTROL REGISTER TC07 this is valid only in NTSC mode. (TC07 TO TC00) CGMS Even Field Control (C/W06) (Address [SR4 to SR0] = 19H) When this bit is set (1), CGMS is enabled for even fields. Note Teletext control register is an 8-bit-wide register. See Figure 50. this is valid only in NTSC mode. WSS Control (C/W07) When this bit is set (1), wide screen signaling is enabled. Note this is valid only in PAL mode.

Rev. C | Page 36 of 64 ADV7170/ADV7171

TC07 TC06 TC05 TC04 TC03 TC02 TC01 TC00

TTXREQ RISING EDGE CONTROL TTXREQ FALLING EDGE CONTROL TC07 TC06 TC05 TC04 TC03 TC02 TC01 TC00 0 0 0 0 0 PCLK 0 0 0 0 0 PCLK 0 0 0 1 1 PCLK 0 0 0 1 1 PCLK " " " " " PCLK " " " " " PCLK 1 1 1 0 14 PCLK 1 1 1 0 14 PCLK 1 1 1 1 15 PCLK 1 1 1 1 15 PCLK

00221-050 Figure 50. Teletext Control Register

C/W07 C/W06 C/W05 C/W04 C/W03 C/W02 C/W01 C/W00

WIDE SCREEN CGMS ODD FIELD C/W03 – C/W00 SIGNAL CONTROL CONTROL C/W07 C/W05 CGMS DATA BITS 0 DISABLE 0 DISABLE 1 ENABLE 1 ENABLE

CGMS EVEN FIELD CGMS CRC CHECK CONTROL CONTROL C/W06 C/W04 0 DISABLE 0 DISABLE 1 ENABLE 1 ENABLE 00221-051 Figure 51. CGMS_WSS Register 0

CGMS_WSS REGISTER 1 C/W1 (C/W17 TO C/W10) CGMS_WSS REGISTER 2 C/W1 (C/W27 TO C/W20) (Address [SR4 to SR0] = 17H) (Address [SR4 to SR0] = 18H) CGMS_WSS Register 1 is an 8-bit-wide register. Figure 52 CGMS_WSS Register 2 is an 8-bit-wide register. Figure 53 shows the operations under the control of this register. shows the operations under the control of this register. C/W1 BIT DESCRIPTION C/W2 BIT DESCRIPTION CGMS/WSS Data Bits (C/W15 to C/W10) CGMS/WSS Data Bits (C/W27 to C/W20) These bit locations are shared by CGMS data and WSS data. In These bit locations are shared by CGMS data and WSS data. In NTSC mode, these bits are CGMS data. In PAL mode, these bits NTSC mode, these bits are CGMS data. In PAL mode, these bits are WSS data. are WSS data. CGMS DATA BITS (C/W17 TO C/W16) These bits are CGMS data bits only.

C/W17 C/W16 C/W15 C/W14 C/W13 C/W12 C/W11 C/W10

C/W17 – C/W16 C/W15 – C/W10

CGMS DATA BITS CGMS/WSS DATA BITS

00221-052 Figure 52. CGMS_WSS Register 1

C/W27 C/W26 C/W25 C/W24 C/W23 C/W22 C/W21 C/W20

C/W27 – C/W20 CGMS/WSS DATA BITS 00221-053 Figure 53. CGMS_ WSS Register 2

Rev. C | Page 37 of 64 ADV7170/ADV7171

APPENDICES APPENDIX 1—BOARD DESIGN Supply Decoupling AND LAYOUT CONSIDERATIONS For optimum performance, bypass capacitors should be installed using the shortest leads possible, consistent with The ADV7170/ADV7171 are highly integrated circuits reliable operation, to reduce the lead inductance. Best containing both precision analog and high speed is obtained with 0.1 μF ceramic capacitor circuitry. They have been designed to minimize interference decoupling. Each group of VAA pins on the ADV7170/ effects of the high speed digital circuitry on the integrity of the ADV7171 must have at least one 0.1 μF decoupling capacitor analog circuitry. It is imperative that these same design and to GND. These capacitors should be placed as close as possible layout techniques be applied to the system level design so that to the device. high speed, accurate performance is achieved. Figure 54 shows the analog interface between the device and monitor. It is important to note that while the ADV7170/ADV7171 contain circuitry to reject power supply noise, this rejection The layout should be optimized for lowest noise on the decreases with frequency. If a high frequency switching power ADV7170/ADV7171 power and ground lines by shielding the supply is used, the designer should pay close attention to digital inputs and providing good decoupling. The lead length reducing power supply noise and consider using a three- between groups of VAA and GND pins should be minimized to terminal voltage regulator for supplying power to the analog minimize inductive ringing. power plane. Ground Planes Digital Signal Interconnect The ground plane should encompass all ADV7170/ADV7171 The digital inputs to the ADV7170/ADV7171 should be isolated ground pins, voltage reference circuitry, power supply bypass as much as possible from the analog outputs and other analog circuitry for the ADV7170/ADV7171, the analog output traces, circuitry. Also, these input signals should not overlay the analog and all the digital signal traces leading up to the ADV7170/ power plane. ADV7171. The ground plane is the board’s common ground plane. Due to the high clock rates involved, long clock lines to the Power Planes ADV7170/ADV7171 should be avoided to reduce noise pickup. The ADV7170, the ADV7171, and any associated analog Any active termination resistors for the digital inputs should be circuitry should each have its own power plane, referred to connected to the regular PCB power plane (VCC) and not to the as the analog power plane (VAA). This power plane should be analog power plane. connected to the regular PCB power plane (VCC) at a single Interconnect point through a ferrite bead. This bead should be located within three inches of the ADV7170/ADV7171. The ADV7170/ADV7171 should be located as close as possible to the output connectors to minimize noise pickup and The metallization gap separating device power plane and board reflections due to impedance mismatch. power plane should be as narrow as possible to minimize the obstruction to the flow of heat from the device into the general The video output signals should overlay the ground plane, not board. the analog power plane, to maximize the high frequency power supply rejection. The PCB power plane should provide power to all digital logic on the PC board, and the analog power plane should provide Digital inputs, especially pixel data inputs and clocking signals, power to all ADV7170/ADV7171 power pins and voltage should never overlay any of the analog signal circuitry and reference circuitry. should be kept as far away as possible.

Plane-to-plane noise coupling can be reduced by ensuring that For best performance, the outputs should each have a 75 Ω load portions of the regular PCB power and ground planes do not resistor connected to GND. These resistors should be placed as overlay portions of the analog power plane unless they can be close as possible to the ADV7170/ADV7171 to minimize arranged so that the plane-to-plane noise is common-mode. reflections.

The ADV7170/ADV7171 should have no inputs left floating. Any inputs that are not required should be tied to ground.

Rev. C | Page 38 of 64 ADV7170/ADV7171

POWER SUPPLY DECOUPLING FOR EACH POWER SUPPLY GROUP

0.1μF 0.01μF L1 (FERRITE BEAD) 5V (VAA)

5V (VAA) 5V (VAA) 5V 1, 11, 20, 28, 30 10μF 33μF VCC 0.1μF 0.1μF GND VAA 25 COMP

33 VREF DAC D 27 75Ω 38–42, ADV7170/ 2–9, 12–14 ADV7171

DAC C 26 5V (VAA) P15–P0 S-VIDEO 75Ω 4kΩ RESET 35 SCRESET/RTC DAC B 31 100nF 15 HSYNC 75Ω UNUSED INPUTS 16 FIELD/VSYNC SHOULD BE GROUNDED DAC A 32 5V (VCC) 17 BLANK 75Ω 5V (VCC) 5V (VCC) 100kΩ 22 RESET 5kΩ 5kΩ TTX 100Ω 37 TTX SCLOCK 23 TTXREQ 36 TTXREQ 100Ω MPU BUS SDATA 24 100kΩ 44 CLOCK R 34 5V (V ) SET AA ALSB GND 150Ω 18 TELETEXT PULL-UP AND 10kΩ PULL-DOWN RESISTORS 10, 19, 21, SHOULD ONLY BE USED 29, 43 IF THESE PINS ARE NOT CONNECTED

27MHz CLOCK (SAME CLOCK AS USED BY MPEG2 DECODER) 00221-054 Figure 54. Recommended Analog Circuit Layout

The circuit in Figure 55 can be used to generate a 13.5 MHz waveform using the 27 MHz clock and the HSYNC pulse. This waveform is guaranteed to produce the 13.5 MHz clock in synchronization with the 27 MHz clock. This 13.5 MHz clock can be used if a 13.5 MHz clock is required by the MPEG decoder. This guarantees that the Cr and Cb pixel information is input to the ADV7170/ADV7171 in the correct sequence.

D Q D Q 13.5MHz CLOCK CK CK

HSYNC

00221-055 Figure 55. Circuit to Generate 13.5 MHz

Rev. C | Page 39 of 64 ADV7170/ADV7171

APPENDIX 2—CLOSED CAPTIONING FCC Code of Federal Regulations (CFR) 47 Section 15.119 and EIA608 describe the closed captioning information for Line 21 The ADV7170/ADV7171 support closed captioning, conform- and Line 284. ing to the standard television synchronizing waveform for color transmission. Closed captioning is transmitted during the The ADV7170/ADV7171 use a single buffering method. This blanked active line time of the odd fields Line 21 and the even means that the closed captioning buffer is only one byte deep; fields Line 284. therefore, there is no frame delay in outputting the closed captioning data, unlike other 2-byte deep buffering systems. Closed captioning consists of a 7-cycle sinusoidal burst that is The data must be loaded at least one line before (Line 20 or frequency- and phase-locked to the caption data. After the clock Line 283) it is outputted on Line 21 and Line 284. A typical run-in signal, the is held for two data bits and is implementation of this method is to use VSYNC to interrupt a followed by a Logic Level 1 start bit. 16 bits of data follow the microprocessor, which in turn loads the new data (two bytes) in start bit. These consist of two 8-bit bytes, seven data bits and every field. If no new data is required for transmission, you one odd parity bit. The data for these bytes is stored in Closed must insert zeros in both the data registers; this is called Captioning Data Register 0 and Closed Captioning Data nulling. It is also important to load control codes, all of which Register 1. are double bytes, on Line 21, or a TV does not recognize them. The ADV7170/ADV7171 also support the extended closed If you have a message like “Hello World,” which has an odd captioning operation, which is active during even fields and is number of characters, it is important to pad it out to an even encoded on 284. The data for this operation is stored number to get end-of-caption, 2-byte control code to land in in Closed Captioning Extended Data Register 0 and Closed the same field. Captioning Extended Data Register 1.

All clock run-in signals and timing to support closed captioning on Line 21 and Line 284 are automatically generated by the ADV7170/ADV7171. All pixel inputs are ignored during Line 21 and Line 284.

10.5 ± 0.25μs 12.91μs 7 CYCLES OF 0.5035MHz (CLOCK RUN-IN) TWO 7-BIT + PARITY ASCII CHARACTERS (DATA)

S P P T A A D0–D6 A R D0–D6 R 50 IRE R I I T T T Y Y BYTE 0 BYTE 1

40 IRE REFERENCE COLOR BURST (9 CYCLES) FREQUENCY = FSC = 3.579545MHz AMPLITUDE = 40 IRE

10.003μs 27.382μs 33.764μs 00221-056 Figure 56. Closed Captioning Waveform (NTSC)

Rev. C | Page 40 of 64 ADV7170/ADV7171

APPENDIX 3—COPY GENERATION MANAGEMENT SYSTEM (CGMS) The ADV7170/ADV7171 support copy generation management systems (CGMS) conforming to the standard. CGMS data is transmitted on Line 20 of the odd fields and Line 283 of even fields. Bit C/W05 and Bit C/W06 control whether or not CGMS data is output on odd and even fields. CGMS data can only be transmitted when the ADV7170/ADV7171 are configured in NTSC mode. The CGMS data is 20 bits long; the function of each of these bits is shown below. The CGMS data is preceded by a reference pulse of the same amplitude and duration as a CGMS bit (see Figure 57). The bits are output from the configuration registers in the following order: C/W00 = C16, C/W01 = C17, C/W02 = C18, C/W03 = C19, C/W10 = C8, C/W11 = C9, C/W12 = C10, C/W13 = C11, C/W14 = C12, C/W15 = C13, C/W16 = C14, C/W17 = C15, C/W20 = C0, C/W21 = C1, C/W22 = C2, C/W23 = C3, C/W24 = C4, C/W25 = C5, C/W26 = C6, C/W27 = C7. If the Bit C/W04 is set to a Logic Level 1, the last six bits, C19 to C14, which comprise the 6-bit CRC check sequence, are calculated automatically on the ADV7170/ADV7171 based on the lower 14 bits (C0 to C13) of the data in the data registers and output with the remaining 14 bits to form the complete 20 bits of the CGMS data. The calculation of the CRC sequence is based on the polynomial X6 + X + 1 with a preset value of 111111. If C/W04 is set to a Logic Level 0, all 20 bits (C0 to C19) are directly output from the CGMS registers (no CRC is calculated; it must be calculated by the user). Function of CGMS Bits Word 0 – 6 Bits

Word 1 – 4 Bits

Word 2 – 6 Bits

CRC – 6 Bits CRC Polynomial = X6 + X + 1 (Preset to 111111)

Word 0 1 0

B1 16:94:3

B2 Display Format Letterbox Normal

B3 Undefined Word 0

B4, B5, B6 Identification information about video and other signals (for example, audio)

Word 1

B7, B8, B9, B10 Identification signal incidental to Word 0

Word 2

B11, B12, B13, B14 Identification signal and information incidental to Word 0

+100 IRE

REF CRC SEQUENCE +70 IRE C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19

0 IRE

49.1μs ± 0.5μs –40 IRE 11.2μs

2.235μs ± 20ns 00221-057

Figure 57. CGMS Waveform Diagram

Rev. C | Page 41 of 64 ADV7170/ADV7171

APPENDIX 4—WIDE SCREEN SIGNALING The ADV7170/ADV7171 support wide screen signaling (WSS) conforming to the standard. WSS data is transmitted on Line 23. WSS data can only be transmitted when the ADV7170/ADV7171 are configured in PAL mode. The WSS data is 14 bits long; the function of each of these bits is as shown below.

The WSS data is preceded by a run-in sequence and a start code (see Figure 58). The bits are output from the configuration registers in the following order:

C/W20 = W0, C/W21 = W1, C/W22 = W2, C/W23 = W3, C/W24 = W4, C/W25 = W5, C/W26 = W6, C/W27 = W7, C/W10 = W8, C/W11 = W9, C/W12 = W10, C/W13 = W11, C/W14 = W12, C/W15 = W13.

If Bit C/W07 is set to a Logic Level 1, it enables the WSS data to be transmitted on Line 23. The latter portion of Line 23 (42.5 μs from the falling edge of HSYNC) is available for the insertion of video.

Function of CGMS Bits Bit 0 to Bit 2 Aspect Ratio/Format/Position

Bit 3 is odd parity check of Bit 0 to Bit 2

B0 B1 B2 B3 Aspect Ratio Format Position

0 0 0 1 4:3 Full format Nonapplicable

1 0 0 0 14:9 Letterbox Center

0 1 0 0 14:9 Letterbox Top

1 1 0 1 16:9 Letterbox Center

0 0 1 0 16:9 Letterbox Top

1 0 1 1 >16:9 Letterbox Center

0 1 1 1 14:9 Full format Center

1 1 1 0 16:9 Nonapplicable Nonapplicable

B4 B9 B10 0 Camera Mode 0 0 No open 1 Mode 1 0 Subtitles in active image area B5 0 1 Subtitles out of active image area 0 Standard Coding 1 1 Reserved 1 Motion Adaptive Color Plus B11 B6 0 No information 0 No Helper 1 Surround sound mode 1 Modulated Helper B12 RESERVED B7 RESERVED B13 RESERVED

500mV W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 RUN-IN START ACTIVE SEQUENCE CODE VIDEO

11.0μs

38.4μs

42.5μs 00221-058 Figure 58. WSS Waveform Diagram

Rev. C | Page 42 of 64 ADV7170/ADV7171

APPENDIX 5—TELETEXT INSERTION Teletext Protocol

The tPD is the time needed by the ADV7170/ADV7171 to The relationship between the TTX bit clock (6.9375 MHz) and interpolate input data on TTX and insert it onto the CVBS the system CLOCK (27 MHz) for 50 Hz is as follows: or Y outputs, such that it appears tSYNTTXOUT = 10.2 μs after the (27 MHz/4) = 6.75 MHz leading edge of the horizontal signal. Time TTXDEL is the pipeline delay time by the source that is gated by the TTXREQ (6.9375 × 106/6.75 × 106) = 1.027777 signal in order to deliver TTX data. Thus, 37 TTX bits correspond to 144 clocks (27 MHz), and With the programmability offered with the TTXREQ signal on each bit has a width of nearly four clock cycles. The ADV7170/ the rising/falling edges, the TTX data is always inserted at the ADV7171 use an internal sequencer and variable phase correct position of 10.2 μs after the leading edge of horizontal interpolation filter to minimize the phase jitter and thus sync pulse, thus enabling a source interface with variable generate a bandlimited signal that can be output on the CVBS pipeline delays. and Y outputs. The width of the TTXREQ signal must always be maintained to At the TTX input, the bit duration scheme repeats after every 37 allow the insertion of 360 (to comply with the Teletext Standard TTX bits or 144 clock cycles. The protocol requires that TTX of PAL-WST) teletext bits at a text data rate of 6.9375 Mbits/sec; Bit 10, Bit 19, Bit 28, and Bit 37 are carried by three clock cycles; this is achieved by setting TC03 to TC00 to 0. The insertion all other bits are carried by four clock cycles. After 37 TTX bits, window is not open if the teletext enable bit (MR35) is set to 0. the next bits with three clock cycles are Bit 47, Bit 56, Bit 65, and Bit 74. This scheme holds for all following cycles of 37 TTX bits, until all 360 TTX bits are completed. All teletext lines are implemented in the same way. Individual control of teletext lines is controlled by teletext setup registers.

45 BYTES (360 BITS) – PAL

TELETEXT VBI LINE ADDRESS AND DATA

RUN-IN CLOCK

00221-059 Figure 59. Teletext VBI Line

tSYNTTXOUT

CVBS/Y

tPD

HSYNC tPD

10.2μs

TTXDATA

TTXDEL

TTXREQ PROGRAMMABLE PULSE EDGES TTXST

tSYNTTXOUT = 10.2μs tPD = PIPELINE DELAY THROUGH ADV7170/ADV7171 TTX = TTXREQ TO TTX (PROGRAMMABLE RANGE = 4 BITS [0–15 CLOCK CYCLES]) DEL 00221-060

Figure 60. Teletext Functionality Diagram

Rev. C | Page 43 of 64 ADV7170/ADV7171

APPENDIX 6—WAVEFORMS NTSC Waveforms (with Pedestal)

+130.8 IRE PEAK COMPOSITE 1268.1mV

+100 IRE REF 1048.4mV

714.2mV +7.5 IRE 387.6mV 0 IRE BLANK LEVEL 334.2mV

–40 IRE SYNC LEVEL 48.3mV 00221-061

Figure 61. NTSC Composite Video Levels

+100 IRE REF WHITE 1048.4mV

714.2mV

+7.5 IRE BLACK LEVEL 387.6mV 0 IRE BLANK LEVEL 334.2mV

–40 IRE SYNC LEVEL 48.3mV 00221-062

Figure 62. NTSC Luma Video Levels

963.8mV PEAK CHROMA

629.7mV p-p 286mV p-p 650mV BLANK/BLACK LEVEL

335.2mV PEAK CHROMA

0mV 00221-063

Figure 63. NTSC Chroma Video Levels

+100 IRE REF WHITE 1052.2mV

720.8mV

+7.5 IRE BLACK LEVEL 387.5mV 0 IRE BLANK LEVEL 331.4mV

–40 IRE SYNC LEVEL 45.9mV 00221-064

Figure 64. NTSC RGB Video Levels

Rev. C | Page 44 of 64 ADV7170/ADV7171

NTSC Waveforms (without Pedestal)

+130.8 IRE PEAK COMPOSITE 1289.8mV

+100 IRE REF WHITE 1052.2mV

714.2mV

0 IRE BLANK/BLACK LEVEL 338mV

–40 IRE SYNC LEVEL 52.1mV 00221-065 Figure 65. NTSC Composite Video Levels

+100 IRE REF WHITE 1052.2mV

714.2mV

0 IRE BLANK/BLACK LEVEL 338mV

–40 IRE SYNC LEVEL 52.1mV 00221-066

Figure 66. NTSC Luma Video Levels

978mV PEAK CHROMA

694.9mV p-p 286mV p-p 650mV BLANK/BLACK LEVEL

299.3mV PEAK CHROMA

0mV 00221-067

Figure 67. NTSC Chroma Video Levels

+100 IRE REF WHITE 1052.2mV

715.7mV

0 IRE BLANK/BLACK LEVEL 336.5mV

–40 IRE SYNC LEVEL 51mV 00221-068 Figure 68. NTSC RGB Video Levels

Rev. C | Page 45 of 64 ADV7170/ADV7171

PAL Waveforms

1284.2mV PEAK COMPOSITE

1047.1mV REF WHITE

696.4mV

350.7mV BLANK/BLACK LEVEL

50.8mV SYNC LEVEL 00221-069 Figure 69. PAL Composite Video Levels

1047mV REF WHITE

696.4mV

350.7mV BLANK/BLACK LEVEL

50.8mV SYNC LEVEL 00221-070 Figure 70. PAL Luma Video Levels

989.7mV PEAK CHROMA

672mV p-p 300mV p-p 650mV BLANK/BLACK LEVEL

317.7mV PEAK CHROMA

0mV 00221-071

Figure 71. PAL Chroma Video Levels

1050.2mV REF WHITE

698.4mV

351.8mV BLANK/BLACK LEVEL

51mV SYNC LEVEL 00221-072 Figure 72. PAL RGB Video Levels

Rev. C | Page 46 of 64 ADV7170/ADV7171

UV Waveforms A A WHITE YELLOW CYAN GREEN MAGENT RED BLUE BLACK WHITE YELLOW CYAN GREEN MAGENT RED BLUE BLACK +505mV +505mV +423mV +334mV LEVEL +171mV +82mV BETACAM LEVEL 0mV 0mV

–82mV 0mV 0mV

–171mV

–334mV –423mV

–505mV 00221-076

–505mV 00221-073

Figure 73. NTST 100% Color Bars, No Pedestal U Levels Figure 76. NTSC 100% Color Bars, No Pedestal V Levels A WHITE YELLOW CYAN GREEN MAGENTA RED BLUE BLACK WHITE YELLOW CYAN GREEN MAGENT RED BLUE BLACK +467mV +467mV +391mV +309mV BETACAM LEVEL +158mV +76mV

BETACAM LEVEL 0mV 0mV

–76mV 0mV 0mV

–158mV

–309mV –391mV

–467mV 00221-077

–467mV 00221-074

Figure 74. NTSC 100% Color Bars with Pedestal U Levels Figure 77. NTSC 100% Color Bars with Pedestal V Levels A A WHITE YELLOW CYAN GREEN MAGENT RED BLUE BLACK WHITE YELLOW CYAN GREEN MAGENT RED BLUE BLACK +350mV +350mV +293mV +232mV SMPTE LEVEL

+118mV +57mV SMPTE LEVEL 0mV 0mV

–57mV

0mV 0mV

–118mV

–293mV –232mV

–350mV 00221-078

–350mV 00221-075

Figure 75. PAL 100% Color Bars, U Levels Figure 78. PAL 100% Color Bars, V Levels

Rev. C | Page 47 of 64 ADV7170/ADV7171

APPENDIX 7—OPTIONAL OUTPUT FILTER APPENDIX 8—OPTIONAL DAC BUFFERING If an output filter is required for the CVBS, Y, UV, Chroma, and When external buffering of the ADV7170/ADV7171 DAC RGB outputs of the ADV7170/ADV7171, the filter shown in outputs is needed, the configuration in Figure 81 is recom- Figure 79 can be used. Plots of the filter characteristics are mended. This configuration shows the DAC outputs running shown in Figure 80. An output filter is not required if the at half (18 mA) their full current (36 mA) capability. This allows outputs of the ADV7170/ADV7171 are connected to most the ADV7170/ADV7171 to dissipate less power; the analog analog monitors or analog TVs. However, if the output signals current is reduced by 50% with a RSET of 300 Ω and a RLOAD of are applied to a system where sampling is used (for example, 75 Ω. This mode is recommended for 3.3 V operation, because digital TVs), then a filter is required to prevent aliasing. optimum performance is obtained from the DAC outputs at

18 mA with a VAA of 3.3 V. This buffer also adds extra isolation

22pF on the video outputs (see the buffer circuit in Figure 82). When calculating absolute output full-scale current and voltage, 1.8μH use the following equations: FILTER I/P FILTER O/P

270pF 330pF 75R OUT OUT ×= RIV LOAD

( × KV ) 00221-079 I = REF Figure 79. Output Filter OUT RSET

0 K = 2146.4 Vconstant, REF = 235.1 V

10 VAA

20 ADV7170/ADV7171 30 OUTPUT VREF DAC A CVBS BUFFER 40 OUTPUT DAC B BUFFER CVBS 50 PIXEL DIGITAL MAGNITUDE (dB) PORT CORE

60 OUTPUT DAC C BUFFER LUMA

70 RSET OUTPUT 300Ω DAC D CHROMA 80 00221-080 BUFFER 100k 1M 10M 100M

FREQUENCY (Hz) 00221-081 Figure 80. Output Filter Plot Figure 81. Output DAC Buffering Configuration

VCC+

5 4

AD8061 1 OUTPUT TO TV MONITOR INPUT/ OPTIONAL 3 2 FILTER O/P

V – CC 00221-082

Figure 82. Recommended Output DAC Buffer

Rev. C | Page 48 of 64 ADV7170/ADV7171

APPENDIX 9—RECOMMENDED REGISTER VALUES output and the internal color bar generator is switched off. In the examples shown, the timing mode is set to Mode 0 in slave The ADV7170/ADV7171 registers can be set depending on the format. TR02 to TR00 of the Timing Register 0 control the user standard required. timing modes. For a detailed explanation of each bit in the The following examples give the various register formats for command registers, please see the Register Programming several video standards. section. TR07 should be toggled after setting up a new timing mode. Timing Register 1 provides additional control over the In each case, the output is set to composite o/p with all DACs position and duration of the timing signals. In the examples, powered up and with the BLANK input control disabled. this register is programmed in default mode. Additionally, the burst and color information are enabled on the

Table 13. PAL B/D/G/H/I (FSC = 4.43361875 MHz) Table 14. PAL M (FSC = 3.57561149 MHz) Address Data Address Data 00Hex Mode Register 0 05Hex 00Hex Mode Register 0 02Hex 01Hex Mode Register 1 00Hex 01Hex Mode Register 1 00Hex 02Hex Mode Register 2 00Hex 02Hex Mode Register 2 00Hex 03Hex Mode Register 3 00Hex 03Hex Mode Register 3 00Hex 04Hex Mode Register 4 00Hex 04Hex Mode Register 4 00Hex 07Hex Timing Register 0 00Hex 07Hex Timing Register 0 00Hex 08Hex Timing Register 1 00Hex 08Hex Timing Register 1 00Hex 09Hex Subcarrier Frequency Register 0 CBHex 09Hex Subcarrier Frequency Register 0 A3Hex 0AHex Subcarrier Frequency Register 1 8AHex 0AHex Subcarrier Frequency Register 1 EFHex 0BHex Subcarrier Frequency Register 2 09Hex 0BHex Subcarrier Frequency Register 2 E6Hex 0CHex Subcarrier Frequency Register 3 2AHex 0CHex Subcarrier Frequency Register 3 21Hex 0DHex Subcarrier Phase Register 00Hex 0DHex Subcarrier Phase Register 00Hex 0EHex Closed Captioning Ext Register 0 00Hex 0EHex Closed Captioning Ext Register 0 00Hex 0FHex Closed Captioning Ext Register 1 00Hex 0FHex Closed Captioning Ext Register 1 00Hex 10Hex Closed Captioning Register 0 00Hex 10Hex Closed Captioning Register 0 00Hex 11Hex Closed Captioning Register 1 00Hex 11Hex Closed Captioning Register 1 00Hex 12Hex Pedestal Control Register 0 00Hex 12Hex Pedestal Control Register 0 00Hex 13Hex Pedestal Control Register 1 00Hex 13Hex Pedestal Control Register 1 00Hex 14Hex Pedestal Control Register 2 00Hex 14Hex Pedestal Control Register 2 00Hex 15Hex Pedestal Control Register 3 00Hex 15Hex Pedestal Control Register 3 00Hex 16Hex CGMS_WSS Register 0 00Hex 16Hex CGMS_WSS Register 0 00Hex 17Hex CGMS_WSS Register 1 00Hex 17Hex CGMS_WSS Register 1 00Hex 18Hex CGMS_WSS Register 2 00Hex 18Hex CGMS_WSS Register 2 00Hex 19Hex Teletext Request Control Register 00Hex 19Hex Teletext Request Control Register 00Hex

Rev. C | Page 49 of 64 ADV7170/ADV7171

Table 15. PAL N (FSC = 4.43361875 MHz) Table 17. Power-Up Reset Values NTSC (FSC = 3.5795454 MHz) Address Data Address Data 00Hex Mode Register 0 05Hex 00Hex Mode Register 0 00Hex 01Hex Mode Register 1 00Hex 01Hex Mode Register 1 58Hex 02Hex Mode Register 2 00Hex 02Hex Mode Register 2 00Hex 03Hex Mode Register 3 00Hex 03Hex Mode Register 3 00Hex 04Hex Mode Register 4 00Hex 04Hex Mode Register 4 10Hex 07Hex Timing Register 0 00Hex 07Hex Timing Register 0 00Hex 08Hex Timing Register 1 00Hex 08Hex Timing Register 1 00Hex 09Hex Subcarrier Frequency Register 0 CBHex 09Hex Subcarrier Frequency Register 0 16Hex 0AHex Subcarrier Frequency Register 1 8AHex 0AHex Subcarrier Frequency Register 1 7CHex 0BHex Subcarrier Frequency Register 2 09Hex 0BHex Subcarrier Frequency Register 2 F0Hex 0CHex Subcarrier Frequency Register 3 2AHex 0CHex Subcarrier Frequency Register 3 21Hex 0DHex Subcarrier Phase Register 00Hex 0DHex Subcarrier Phase Register 00Hex 0EHex Closed Captioning Ext Register 0 00Hex 0EHex Closed Captioning Ext Register 0 00Hex 0FHex Closed Captioning Ext Register 1 00Hex 0FHex Closed Captioning Ext Register 1 00Hex 10Hex Closed Captioning Register 0 00Hex 10Hex Closed Captioning Register 0 00Hex 11Hex Closed Captioning Register 1 00Hex 11Hex Closed Captioning Register 1 00Hex 12Hex Pedestal Control Register 0 00Hex 12Hex Pedestal Control Register 0 00Hex 13Hex Pedestal Control Register 1 00Hex 13Hex Pedestal Control Register 1 00Hex 14Hex Pedestal Control Register 2 00Hex 14Hex Pedestal Control Register 2 00Hex 15Hex Pedestal Control Register 3 00Hex 15Hex Pedestal Control Register 3 00Hex 16Hex CGMS_WSS Register 0 00Hex 16Hex CGMS_WSS Register 0 00Hex 17Hex CGMS_WSS Register 1 00Hex 17Hex CGMS_WSS Register 1 00Hex 18Hex CGMS_WSS Register 2 00Hex 18Hex CGMS_WSS Register 2 00Hex 19Hex Teletext Request Control Register 00Hex 19Hex Teletext Request Control Register 00Hex

Table 16. PAL60 (FSC = 4.43361875 MHz) Address Data 00Hex Mode Register 0 04Hex 01Hex Mode Register 1 00Hex 02Hex Mode Register 2 00Hex 03Hex Mode Register 3 00Hex 04Hex Mode Register 4 00Hex 07Hex Timing Register 0 00Hex 08Hex Timing Register 1 00Hex 09Hex Subcarrier Frequency Register 0 CBHex 0AHex Subcarrier Frequency Register 1 8AHex 0BHex Subcarrier Frequency Register 2 09Hex 0CHex Subcarrier Frequency Register 3 2AHex 0DHex Subcarrier Phase Register 00Hex 0EHex Closed Captioning Ext Register 0 00Hex 0FHex Closed Captioning Ext Register 1 00Hex 10Hex Closed Captioning Register 0 00Hex 11Hex Closed Captioning Register 1 00Hex 12Hex Pedestal Control Register 0 00Hex 13Hex Pedestal Control Register 1 00Hex 14Hex Pedestal Control Register 2 00Hex 15Hex Pedestal Control Register 3 00Hex 16Hex CGMS_WSS Register 0 00Hex 17Hex CGMS_WSS Register 1 00Hex 18Hex CGMS_WSS Register 2 00Hex 19Hex Teletext Request Control Register 00Hex

Rev. C | Page 50 of 64 ADV7170/ADV7171

APPENDIX 10—OUTPUT WAVEFORMS

0.6

0.4

0.2 VOLTS

0.0

–0.2 L608

0.0 10.0 20.0 30.0 40.0 50.0 60.0 MICROSECONDS : 0.00dB APL = 39.1% PRECISION MODE OFF SOUND-IN-SYNC OFF 625 LINE PAL NO FILTERING SYNCHRONOUS SYNC = SOURCE SLOW CLAMP TO 0.00V AT 6.72μs FRAMES SELECTED: 1 2 3 4 00221-083 Figure 83. 100/0/75/0 PAL Color Bars

0.5 VOLTS

0.0

L575

0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 MICROSECONDS APL NEEDS SYNC = SOURCE! PRECISION MODE OFF SOUND-IN-SYNC OFF 625 LINE PAL NO FILTERING SYNCHRONOUS SYNC = A

SLOW CLAMP TO 0.00V AT 6.72μs FRAMES SELECTED: 1 00221-084

Figure 84. 100/0/75/0 PAL Color Bars Luminance

Rev. C | Page 51 of 64 ADV7170/ADV7171

0.5

VOLTS 0.0

–0.5 L575

10.0 20.0 30.0 40.0 50.0 60.0 MICROSECONDS NO BRUCH SIGNAL APL NEEDS SYNC = SOURCE! PRECISION MODE OFF SOUND-IN-SYNC OFF 625 LINE PAL NO FILTERING SYNCHRONOUS SYNC = A

SLOW CLAMP TO 0.00V AT 6.72μs FRAMES SELECTED: 1 00221-085

Figure 85. 100/0/75/0 Pal Color Bars Chrominance

100.0

0.5

50.0 IRE:FLT VOLTS

0.0 0.0

–50.0 F1 L76

0.0 10.0 20.0 30.0 40.0 50.0 60.0 MICROSECONDS APL = 44.6% PRECISION MODE OFF 525 LINE NTSC NO FILTERING SYNCHRONOUS SYNC = A

SLOW CLAMP TO 0.00V AT 6.72μs FRAMES SELECTED: 1 2 00221-086

Figure 86. 100/7.5/75/7.5 NTSC Color Bars

Rev. C | Page 52 of 64 ADV7170/ADV7171

0.6

0.4 50.0

0.2 IRE:FLT VOLTS

0.0 0.0

–0.2 F2 L238

10.0 20.0 30.0 40.0 50.0 60.0 MICROSECONDS NOISE REDUCTION: 15.05dB APL = 44.7% PRECISION MODE OFF 525 LINE NTSC NO FILTERING SYNCHRONOUS SYNC = SOURCE

SLOW CLAMP TO 0.00V AT 6.72μs FRAMES SELECTED: 1 2 00221-087

Figure 87. 100/7.5/75/7.5 NTSC Color Bars Luminance

0.4 50.0

0.2

VOLTS 0.0 IRE:FLT

–0.2

–50.0 –0.4

F1 L76

0.0 10.0 20.0 30.0 40.0 50.0 60.0 MICROSECONDS NOISE REDUCTION: 15.05dB APL NEEDS SYNC = SOURCE! PRECISION MODE OFF 525 LINE NTSC NO FILTERING SYNCHRONOUS SYNC = B

SLOW CLAMP TO 0.00V AT 6.72μs FRAMES SELECTED: 1 2 00221-088

Figure 88. 100/7.5/75/7.5 NTSC Color Bars Chrominance

Rev. C | Page 53 of 64 ADV7170/ADV7171

V APL = 39.6% SYSTEM LINE L608 ANGLE (DEG) 0.0 GAIN × 1.000 0.000dB cy 625 LINE PAL BURST FROM SOURCE DISPLAY +V AND –V

R g M g

75%

100% YI b

U

yl B

G Cy m g

r

SOUND IN SYNC OFF 00221-089

Figure 89. PAL Vector Plot

R–Y APL = 45.1% SYSTEM LINE L76F1 ANGLE (DEG) 0.0 GAIN × 1.000 0.000dB I cy 525 LINE NTSC BURST FROM SOURCE

R M g Q

YI b 100% B–Y

75% B

G Cy –Q

–I

SETUP 7.5%

00221-090 Figure 90. NTSC Vector Plot

Rev. C | Page 54 of 64 ADV7170/ADV7171

COLOR BAR (NTSC) WFM → FCC COLOR BAR FIELD = 2 LINE = 28 LUMINANCE LEVEL (IRE) 0.4 0.2 0.2 0.0 0.2 0.1 0.2 0.1 30.0 20.0 10.0 0.0 –10.0

CHROMINANCE LEVEL (IRE) 0.0 –0.2 –0.2 –0.3 –0.2 –0.3 0.0 0.0 1.0

0.0

–1.0

CHROMINANCE PHASE (DEG) . . . . . –0.1 –0.2 –0.2 –0.1 –0.3 –0.2 - - - - -

0.0

–1.0

–2.0

GRAY YELLOW CYAN GREEN MAGENTA RED BLUE BLACK

AVERAGE: 32 → 32 REFERENCE 75/7.5/75/7.5 COLOR BAR STANDARD 00221-091

Figure 91. NTSC Color Bar Measurement

DGDP (NTSC) WFM → 5 STEP BLOCK MODE START F2 L64, STEP = 32, END = 192 DIFFERENTIAL GAIN (%) MIN = –0.00 MAX = 0.11 p-p/MAX = 0.11 0.00 0.08 0.07 0.11 0.07 0.05

0.3

0.2

0.1

0.0

–0.1

DIFFERENTIAL PHASE (DEG) MIN = 0.02 MAX = 0.14 p-p = 0.16 0.00 0.03 –0.02 0.14 0.10 0.10

0.20

0.15

0.10

0.05

–0.00

–0.05

–0.10

1ST 2ND 3RD 4TH 5TH 6TH 00221-092

Figure 92. NTSC Differential Gain and Phase Measurement

Rev. C | Page 55 of 64 ADV7170/ADV7171

LUMINANCE NONLINEARITY (NTSC) WFM → 5 STEP FIELD = 2 LINE = 21 LUMINANCE NONLINEARITY (%) p-p = 0.2 99.9 100.0 99.9 99.9 99.8

100.4 100.3 100.2 100.1 100.0 99.9 99.8 99.7 99.6 99.5 99.4 99.3 99.2 99.1 99.0 98.9 98.8 98.7 98.6

1ST 2ND 3RD 4TH 5TH 00221-093

Figure 93. NTSC Luminance Nonlinearity Measurement

CHROMINANCE AM PM (NTSC) WFM → APPROPRIATE FULL FIELD (BOTH FIELDS) BANDWIDTH 100Hz TO 500kHz

AM NOISE –68.4dB RMS

–75.0 –70.0 –65.0 –60.0 –55.0 –50.0 –45.0 –40.0 dB RMS

PM NOISE –64.4dB RMS

–75.0 –70.0 –65.0 –60.0 –55.0 –50.0 –45.0 –40.0 dB RMS

(0dB = 714mV p-p WITH AGC FOR 100% CHROMINANCE LEVEL) 00221-094 Figure 94. NTSC AMPM Noise Measurement

Rev. C | Page 56 of 64 ADV7170/ADV7171

NOISE SPECTRUM (NTSC) WFM → PEDESTAL FIELD = 2 LINE = 64 AMPLITUDE (0dB = 714mV p-p) NOISE LEVEL = –80.1dB RMS BANDWIDTH 100kHz TO FULL

–5.0 –10.0 –15.0 –20.0 –25.0 –30.0 –35.0 –40.0 –45.0 –50.0 –55.0 –60.0 –65.0 –70.0 –75.0 –80.0 –85.0 –90.0 –95.0 –100.0

1.0 2.0 3.0 4.0 5.0 6.0

(MHz) 00221-095 Figure 95. NTSC SNR Pedestal Measurement

NOISE SPECTRUM (NTSC) WFM → RAMP SIGNAL FIELD = 2 LINE = 64 AMPLITUDE (0dB = 714mV p-p) NOISE LEVEL = –61.7dB RMS BANDWIDTH 10kHz TO FULL (TILT NULL)

–5.0 –10.0 –15.0 –20.0 –25.0 –30.0 –35.0 –40.0 –45.0 –50.0 –55.0 –60.0 –65.0 –70.0 –75.0 –80.0 –85.0 –90.0 –95.0 –100.0

1.0 2.0 3.0 4.0 5.0

(MHz) 00221-096 Figure 96. NTSC SNR Ramp Measurement

Rev. C | Page 57 of 64 ADV7170/ADV7171

PARADE SMPTE/EBU PAL

mV Y(A) mV Pb(B) mV Pr(C)

700 250 250

600 200 200

500 150 150

400 100 100

300 50 50

200 0 0

100 –50 –50

0 –100 –100

–100 –150 –150

–200 –200 –200

–300 –250 –250

00221-097 Figure 97. PAL YUV Parade Plot

LIGHTNING COLORBARS: 75% SMPTE/EBU (50Hz) AVERAGE 32 → 32 L183 Pk-WHITE (100%) 700.0mV SETUP 0.0% COLOR p-p 525.0mV

YI G R CY M B –274.82 –173.24 –88.36 88.31 174.35 260.51 0.93% 0.19% 0.19% 0.28% –0.65% –0.14% B–Y W YI CY 462.80 YI 864.78 –0.50% –0.88%

G G 307.54 CY M –0.21% 216.12 R –0.33% M R 156.63 –0.22% B B B 61.00 1.92% R

G M CY YI

W R–Y

CY G B YI M R –262.17 –218.70 –42.54 41.32 212.28 252.74 –0.13% –0.51% 0.69% –0.76% –3.43% –3.72%

COLOR Pk-Pk: B–Y 532.33mV 1.40% R–Y 514.90mV –1.92%

Pk-WHITE: 700.4mV (100%) SETUP –0.01% DELAY: B–Y –6ns R–Y –6ns 00221-098

Figure 98. PAL YUV Lighting Plot

Rev. C | Page 58 of 64 ADV7170/ADV7171

COMPONENT NOISE LINE = 202 AMPLITUDE (0dB = 700mV p-p) NOISE dB RMS BANDWIDTH 10kHz TO 5.0MHz

0.0 –5.0 –10.0 –15.0 →Y 82.1 Pb 82.3 –20.0 Pr 83.3 –25.0 –30.0 –35.0 –40.0 –45.0 –50.0 –55.0 –60.0 –65.0 –70.0 –75.0 –80.0 –85.0 –90.0 –95.0 –100.0 1.0 2.0 3.0 4.0 5.0 6.0

(MHz) 00221-099 Figure 99. PAL YUV SNR Plot

COMPONENT MULTIBURST LINE = 202 AMPLITUDE (0dB = 100% OF 688.1mV 683.4mV 668.9mV) (dB) 0.04 –0.02 –0.05 –0.68 –2.58 –8.05

0.0

Y –5.0

–10.0

0.49 0.99 2.00 3.99 4.79 5.79

0.21 0.23 –0.78 –2.59 –7.15 0.0

Pb –5.0

–10.0 0.49 0.99 1.99 2.39 2.89

0.25 0.25 –0.77 –2.59 –7.13

0.0

Pr –5.0

–10.0

0.49 0.99 1.99 2.39 2.89 00221-100 (MHz) Figure 100. PAL YUV Multiburst Response

Rev. C | Page 59 of 64 ADV7170/ADV7171

COMPONENT VECTOR SMPTE/EBU, 75%

R

M g

YI

BK

B

G

CY

00221-101 Figure 101. PAL YUV Vector Plot

mV GREEN (A) mV BLUE (B) mV RED (C)

700 700 700

600 600 600

500 500 500

400 400 400

300 300 300

200 200 200

100 100 100

0 0 0

–100 –100 –100

–200 –200 –200

–300 –300 –300

00221-102 Figure 102. PAL RGB Waveforms

Rev. C | Page 60 of 64 ADV7170/ADV7171

OUTLINE DIMENSIONS 14.15 1.03 2.45 13.90 SQ 0.88 MAX 13.65 0.73

44 34

1.95 REF 1 33

SEATING PIN 1 PLANE TOP VIEW 10.20 (PINS DOWN) 10.00 SQ 9.80 2.20 2.00 0.23 1.80 0.11 11 23 0.25 MIN 7° 12 22 0.10 0° COPLANARITY 0.45 VIEW A 0.30 0.80 BSC LEAD WIDTH VIEW A LEAD PITCH ROTATED 90° CCW

COMPLIANT TO JEDEC STANDARDS MO-112-AA-1 041807-A Figure 103. 44-Lead Thin Plastic Quad Flat Package [MQFP] (S-44-2) Dimensions shown in millimeters

1.20 MAX 12.00 BSC SQ

0.75 44 34 0.60 1 33 0.45 PIN 1

TOP VIEW 10.00 (PINS DOWN) BSC SQ 0° MIN 1.05 0.20 1.00 0.09 0.95 7° 3.5° 11 23 0.15 SEATING 0° 12 22 0.05 PLANE 0.08 MAX COPLANARITY VIEW A 0.80 0.45 BSC 0.37 LEAD PITCH VIEW A 0.30 ROTATED 90° CCW

COMPLIANT TO JEDEC STANDARDS MS-026ACB Figure 104. 44-Lead Thin Plastic Quad Flat Package [TQFP] (SU-44) Dimensions shown in millimeters

Rev. C | Page 61 of 64 ADV7170/ADV7171

13.45 1.03 2.45 13.20 SQ 0.88 MAX 12.95 0.73

44 34

1.60 REF 1 33

SEATING PIN 1 PLANE TOP VIEW 10.20 (PINS DOWN) 10.00 SQ 9.80 2.20 2.00 0.23 1.80 0.11 11 23 0.25 7° 12 22 0.10 0.10 0° COPLANARITY 0.45 VIEW A 0.29 0.80 BSC LEAD WIDTH VIEW A LEAD PITCH ROTATED 90° CCW

COMPLIANT TO JEDEC STANDARDS MS-022-AB-1 041807-A Figure 105. 44-Lead Metric Quad Flat Package [MQFP] (S-44-1) Dimensions shown in millimeters

ORDERING GUIDE Model Temperature Range Package Descriptions Package Options ADV7170KSZ1 −40°C to +85°C 44-Lead Metric Quad Flat Package [MQFP] S-44-2 1 ADV7170KSZ-REEL −40°C to +85°C 44-Lead Metric Quad Flat Package [MQFP] S-44-2 1 ADV7170KSUZ −40°C to +85°C 44-Lead Thin Plastic Quad Flat Package [TQFP] SU-44 1 ADV7170KSUZ-REEL −40°C to +85°C 44-Lead Thin Plastic Quad Flat Package [TQFP] SU-44 1 ADV7171KSZ −40°C to +85°C 44-Lead Metric Quad Flat Package [MQFP] S-44-2 1 ADV7171KSZ-REEL −40°C to +85°C 44-Lead Metric Quad Flat Package [MQFP] S-44-2 1 ADV7171KSUZ −40°C to +85°C 44-Lead Thin Plastic Quad Flat Package [TQFP] SU-44 1 ADV7171KSUZ-REEL −40°C to +85°C 44-Lead Thin Plastic Quad Flat Package [TQFP] SU-44 1 ADV7171WBSZ-REEL −40°C to +85°C 44-Lead Metric Quad Flat Package [MQFP] S-44-1 EVAL-ADV7170EBM Evaluation Board EVAL-ADV7171EBM Evaluation Board

1 Z = RoHS Compliant Part.

Rev. C | Page 62 of 64 ADV7170/ADV7171

NOTES

Rev. C | Page 63 of 64 ADV7170/ADV7171

NOTES

Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.

©2002–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Printed in the U.S.A. D00221-0-3/09(C)

Rev. C | Page 64 of 64