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ADV7170/ADV7171 Digital PAL/NTSC Video Encoder with 10

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ADV7170/ADV7171 Digital PAL/NTSC Video Encoder with 10 Digital PAL/NTSC Video Encoder with 10-Bit SSAF™ and Advanced Power Management ADV7170/ADV7171 FEATURES Programmable LUMA delay ITU-R1 BT601/656 YCrCb to PAL/NTSC video encoder Individual on/off control of each DAC High quality 10-bit video DACs CCIR and square pixel operation SSAF (super sub-alias filter) Integrated subcarrier locking to external video source Advanced power management features Color signal control/burst signal control CGMS (copy generation management system) Interlaced/noninterlaced operation WSS (wide screen signalling) Complete on-chip video timing generator Simultaneous Y, U, V, C output format Programmable multimode master/slave operation 3 NTSC M, PAL M/N2, PAL B/D/G/H/I, PAL60 Macrovision® AntiTaping Rev. 7.1 (ADV7170 only) Single 27 MHz clock required (×2 oversampling) Closed captioning support 80 dB video SNR Teletext insertion port (PAL-WST) 32-bit direct digital synthesizer for color subcarrier On-board color bar generation Multistandard video output support On-board voltage reference 2 2 Composite (CVBS) 2-wire serial MPU interface (I C®-compatible and Fast I C) Components S-Video (Y/C), YUV, and RGB Single supply 5 V or 3.3 V operation EuroSCART output (RGB + CVBS/LUMA) Small 44-lead MQFP/TQFP packages 4 Component YUV + CHROMA Industrial temperature grade = −40°C to +85°C Video input data port supports APPLICATIONS CCIR-656 4:2:2 8-bit parallel input format High performance DVD playback systems, portable video 4:2:2 16-bit parallel input format equipment including digital still cameras and laptop PCs, video games, PC video/multimedia and digital Programmable simultaneous composite and S-Video or RGB satellite/cable systems (set-top boxes/IRD) (SCART)/YUV video outputs Programmable luma filters (low-pass [PAL/NTSC]) notch, 1 ITU-R and CCIR are used interchangeably in this document (ITU-R has replaced extended (SSAF, CIF, and QCIF) CCIR recommendations). 2 Throughout the document N is referenced to PAL- Combination -N. Programmable chroma filters (low-pass [0.65 MHz, 1.0 MHz, 3 Protected by U.S. Patents 4,631,603;, 4,577,216, 4,819,098; and other intellectual 1.2 MHz and 2.0 MHz], CIF and QCIF) property rights. The Macrovision anticopy process is licensed for noncommercial Programmable VBI (vertical blanking interval) home use only, which is its sole intended use in the device. Please contact sales office for latest Macrovision version available. Programmable subcarrier frequency and phase 4 Refer to Table 8 for complete operating details. TTXREQ TTX M POWER 10 U 10 MANAGEMENT CGMS AND WSS TELETEXT L 10-BIT DAC D (PIN 27) DAC CONTROL INSERTION INSERTION YUV TO T VAA 10 (SLEEP MODE) BLOCK BLOCK RGB I 10 MATRIX P 10-BIT DAC C (PIN 26) L DAC RESET 10 E X 10 COLOR 8 Y 8 9 9 E 10-BIT DAC B (PIN 31) ADD INTER- PROGRAMMABLE 10 DAC DATA SYNC LUMINANCE R P7–P0 4:2:2 TO YCrCb POLATOR 8 FILTER 4:4:4 TO U INTER- YUV U 8 8 8 10 10 P15–P8 POLATOR MATRIX ADD INTER- PROGRAMMABLE 8 V 8 8 8 10-BIT DAC A (PIN 32) BURST POLATOR CHROMINANCE 10 DAC FILTER V HSYNC 10 ADV7170/ADV7171 VIDEO TIMING REAL-TIME 10 FIELD/VSYNC 2 V GENERATOR I C MPU PORT CONTROL SIN/COS VOLTAGE REF BLANK CIRCUIT DDS BLOCK REFERENCE RSET CIRCUIT COMP CLOCK SCLOCK SDATA ALSB SCRESET/RTC GND 00221-001 Figure 1. Functional Block Diagram Protected by U.S. Patents 5,343,196; 5,442,355; and other intellectual property rights. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. or otherwise under any patent or patent rights of Analog Devices. Trademarks and Tel: 781.329.4700 www.analog.com registered trademarks are the property of their respective companies. Fax: 781.461.3113 ©2002–2009 Analog Devices, Inc. All rights reserved. ADV7170/ADV7171 TABLE OF CONTENTS Specifications ..................................................................................... 4 Mode Register 1 MR1 (MR17 to MR10) ................................. 30 Dynamic Specifications ............................................................... 6 MR1 Bit Description .................................................................. 30 Timing Specifications .................................................................. 7 Mode Register 2 MR2 (MR27 to MR20) ................................. 30 Timing Diagrams.......................................................................... 9 MR2 Bit Description .................................................................. 30 Absolute Maximum Ratings .......................................................... 10 Mode Register 3 MR3 (MR37 to MR30) .................................... 32 Package Thermal Performance ................................................. 10 MR3 Bit Description .................................................................... 32 ESD Caution ................................................................................ 10 Mode Register 4 MR4 (MR47 to MR40) ................................. 33 Pin Configuration and Function Descriptions ........................... 11 MR4 Bit Description .................................................................. 33 General Description ....................................................................... 13 VSYNC_3H (MR43) .................................................................. 33 Data Path Description ................................................................ 13 Timing Mode Register 0 (TR07 to TR00) ............................... 33 Internal Filter Response ............................................................. 14 TR0 Bit Description ................................................................... 34 Typical Performance Characteristics ........................................... 15 Timing Mode Register 1 (TR17 to TR10) ............................... 34 Features ............................................................................................ 18 TR1 Bit Description ................................................................... 34 Color Bar Generation ................................................................ 18 Subcarrier Frequency Registers 0 to 3 (FSC3 to FSC0) ......... 35 Square Pixel Mode ...................................................................... 18 Subcarrier Phase Registers (FP7 to FP0) ................................. 35 Color Signal Control .................................................................. 18 Closed Captioning Even Field Data Register 1 to 0 (CED15 to CED0) .......................................................................................... 35 Burst Signal Control ................................................................... 18 Closed Captioning Odd Field Data Registers 1 to 0 (CCD15 NTSC Pedestal Control ............................................................. 18 to CCD0) ..................................................................................... 35 Pixel Timing Description .......................................................... 18 NTSC Pedestal/PAL Teletext Control Registers 3 to 0 (PCE15 Subcarrier Reset .......................................................................... 18 to PCE0, PCO15 to PCO0)/(TXE15 to TXE0, TXO15 to TXO0) .......................................................................................... 36 Real-Time Control ..................................................................... 18 Teletext Request Control Register TC07 (TC07 to TC00) .... 36 Video Timing Description ........................................................ 18 CGMS_WSS Register 0 C/W0 (C/W07 to C/W00) .............. 36 Power-On Reset .......................................................................... 26 C/W0 Bit Description ................................................................ 36 SCH Phase Mode ........................................................................ 26 CGMS_WSS Register 1 C/W1 (C/W17 to C/W10) .............. 37 MPU Port Description ............................................................... 26 C/W1 Bit Description ................................................................ 37 Register Accesses ........................................................................ 27 CGMS Data Bits (C/W17 to C/W16) ...................................... 37 Register Programming ................................................................... 28 CGMS_WSS Register 2 C/W1 (C/W27 to C/W20) .............. 37 Subaddress Register (SR7 to SR0) ............................................ 28 C/W2 Bit Description ................................................................ 37 Register Select (SR5 to SR0) ...................................................... 28 Appendices ...................................................................................... 38 Mode Register 0 MR0 (MR07 to MR00) ................................. 28 Appendix 1—Board Design and Layout Considerations...... 38 MR0 Bit Description .................................................................. 28 Rev. C | Page 2 of 64 ADV7170/ADV7171 Appendix 2—Closed Captioning .............................................. 40 Appendix 7—Optional Output Filter ....................................... 48 Appendix 3—Copy Generation Management System Appendix 8—Optional DAC Buffering ..................................
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