<<

NEW PRODUCTS - Concept® HDL New Standard in Schematic Capture Concept HDL replaces SCALD, adding many new features for FPGA design.

by Randy Hartgrove, Product Marketing Manager, , [email protected]

adence Design Systems has introduced Concept HDL, a Concept HDL and FPGA Design Creation new HDL-based design creation tool to replace the Concept HDL supports top-down, mixed-level, and bottom-up C older SCALD-based system. SCALD is a proprietary FPGA design flows. For the top-down and mixed-level flows format that offered many advantages in its time, but now yields Concept HDL is integrated with Synplify from Synplicity for to the future. Concept HDL, based on the industry standards design synthesis. Concept HDL writes and VHDL directly Verilog-HDL or VHDL, offers all the capabilities of its prede- from a block diagram schematic that is defined in either Verilog or VHDL. The design is used by Synplify to synthesize the cessor and in the PE13.5 release offers many new features that structural netlist that can be passed to the are essential for FPGA designs including tools. This combination of high- support for the new Virtex family from Xilinx. level block diagram definition in Concept HDL Enter Concept HDL and synthesis in Synplify make a powerful FPGA The HDL-centric data model upon which top-down design environment. Concept HDL is built provides well-defined A mixed-level design consists of modules in industry standards for expressing design Concept HDL defined in FPGA vendor primitives structure, configuration, expansion, inherit- as well as modules that are described using ance, scoping, constraints, and property Verilog or VHDL. Concept HDL can also treat annotations. The use of the standard also modules as black boxes for designs where the provides for easy third-party tool integration FPGA layout or synthesis is complete and should and a tighter, more natural union with simula- not be redone. The top-down and mixed-level tors like the Verilog®-XL simulator, NC Verilog® flows feature a tight integration between Concept simulator, Leapfrog® simulator, or AffirmaTM NC HDL and Synplify that includes generation of VHDL simulator. Synplify project and constraint files. This Concept HDL also features the new Occur- provides Concept HDL with the ability to pass rence Property File (OPF) that supports the constraints to the synthesis engine to control the proper reuse of hierarchical logic blocks. In this way, way the design is implemented in the physical device. redundant logic does not need to be duplicated in the design, The End of SCALD as You Know It but is merely referenced as many times as needed. The OPF With the future of design safely established with Concept HDL, keeps separate property annotations for the different instances the SCALD architecture will no longer be available. Cadence of reused logic but permits proper design expansion to either Design Systems, Inc. has offered all of its customers who are an FPGA or PCB design. using the SCALD architecture a no-charge migration to the new Concept HDL also offers the On-Line Electrical Connectivity HDL solution. As previously mentioned, in the PE 13.5 release Server (OLECS), a new feature that expands the design to a Concept HDL also provides support for the Xilinx Virtex fully evaluated state for a variety of analyses or electrical rule technology, which is not checks. OLECS gives Concept HDL an supported by SCALD. In fact, understanding of the complete design, For more information about the powerful features of Concept HDL, or to learn more neither Xilinx nor Cadence and moves it out of the realm of schematic about the transition from SCALD to HDL, Design Systems, Inc. will capture into design creation. Combine the please visit the Cadence website at support the SCALD architec- OPF and OLECS features together and you www.cadence.com. Registered users of ture with new technology, so begin to understand what a step forward Cadence tools may also visit SourceLink for more information on the transition. now is the time to make the Concept HDL offers you. switch.

XCell 31 - 1Q99 25