Does FPGA-Based Prototyping Really Have to Be This Difficult?

Does FPGA-based prototyping really have to be this difficult?

Embedded Conference Finland

Andrew Marshall May 2017 What is FPGA-Based Prototyping?

• Primary platform for pre-silicon software development and validation • Maps a digital ASIC, ASSP, SoC design or part thereof into one or more FPGAs

• Allows SW to simulate in real world environments • Provides pre-silicon execution speeds in MHz • Enables connectivity to real peripherals • Runs real world traffic flows including interrupts and unpredictable events • Runs error conditions and handling errata with other system components

• Ever-increasing verification requirements driven by growing hardware and software complexity

• Fast time to results is essential to ensure projects can meet schedules

• Right tools for the right job: Combination of formal, simulation, emulation and FPGA prototyping

FPGA Prototyping …

Emulation …

Simulation …

Formal … Main core engine usage engine core Main

Project timeline Tapeout Silicon

Debug Software

FPGA-based prototyping has become the methodology of choice for early software development.

BUT …

Prototyping implementation and bring-up takes too long and there has, so far, not been any easy transition from simulation and emulation into FPGA-based prototyping.

4-6 weeks 4-6 weeks 4 weeks 2 weeks

RTL Memory Compile Automatic / manual In-circuit FPGA timing closure (P&R) preparation remodeling Synthesis Multi-FPGA partitioning bring-up

3 months … and more!

RTL Memory Compile Automatic / manual In-circuit Functional model validation preparation remodeling Synthesis Multi-FPGA partitioning bring-up ▲ Traditional

◄ Protium™ S1

• No RTL modifications needed • Pre-FPGA P&R model validation – Clocking / number of clocks – Multiple design integrations per day – Automated memory compilation and modeling – Avoids time-consuming FPGA P&R

• Fully automatic, multi-FPGA partitioning • Fully integrated FPGA P&R – Optional manual optimization – Automatic constraint generation – Guaranteed P&R success

• Traditional imitations: • Protium™ benefits: – Gated clock, multiplexed clocks – No hold-time violations in user clock domains – # of clocks – Removes any FPGA-specific clock limitations – Difficult to achieve FPGA timing closure – Supports unlimited # of design clocks – Long iteration times / long FPGA P&R times – Improves FPGA timing closure – Unpredictable results & prototype behavior – Accelerates FPGA P&R times

Clock distribution on the board Clock generation in the FPGA

• FPGA built in & XSRAM – Benefits: – Automatic mapping of any memory type – Support for multi-port memories – Support for backdoor upload/download – XSRAM adds: – Increases FPGA internal memory from 80Mbits to 128MBytes • XDRAM – Benefits: Protium FPGA X – Adds DDRx bulk memories XDRAM Board DUT DDRn K7 – Supports LPDDR2/3/4; DDR3/4; HBM Controller S

DDRn I/f O Logic – No change to design memory controller and firmware DDR3 D Ctrl I

UD Module M – Support for backdoor upload/download M Upload/Download – Acts as memory speed bridge (timing, refresh, etc.) • Directly Connected or Full Custom – Daughter cards available for more custom approaches if required

Software Applications Middleware Operating Systems (OS) Drivers Firmware / HAL • Waveforms across partitions SoC, Sub-System or IP • Backdoor memory access • Quickly change boot code, software, etc. • Design-centric view vs. FPGA-centric ARM V8 CPUSubsystem Application Specific Components

Cortex Cortex Cortex Cortex -A53Compute-A53 -A57 A57 Customer’sBoot • Clock control • Force/release 3D DSP processo Modem L2Sub cache SystemL2 cache ApplicationGFX A/V-Specificr Components ARM M0 • Start/stop the clock on demand • Predefined signals (at compile time) to “0” Cache coherent fabric

or “1” during runtime SoC interconnect fabric • Fully scriptable runtime environment

GPI UAR • Remote access • Monitor signal Ethe HDMI O T DDR PCIe USB3.0 r Display 3 Gen 2,3 SATA INTC High Speed, net General- PMU I2C • Real-time monitoring of predefined (at 3. 2. MIPI Low-Speed • Network resource anytime from anywhere Wired0 0 Interface Purpose MIPI SPI PHY PHY PHY WLAN P P PeripheralsJTA Time H H Low-speed peripheral Peripherals PeripheralsLTE G r compile time) signals Y Y subsystem • High-performance link to software model High speed, wired interface peripherals Other peripherals Low speed peripherals

Hardware Debug: RTL Software Debug: C Code

Probes JTAG

Performance (single board, multi-FPGA)

Prototyping Automatic mode Further Optimization design 100MHz Phase 3

… Design-based Phase 2 user manual refinement 10MHz

Higher effort Phase 1 performance optimization 5MHz Automatic for quick functionality 3MHz

10 © 2017 Cadence Design Systems, Inc. All rights reserved. “Protium™ has incredibly simplified our prototyping Fast Time-to-Prototype (TTP) flow. It allowed us to significantly improve prototyping bring-up time.”

Riad Ben Mouhoub Networking ◄ 81% PhD/Tech Leader, Microsemi Corporation

Networking ◄ 85% Traditional Consumer ◄ 88% Protium S1

CPU ◄ 91%

Consumer ◄ 89%

Networking ◄ 91%

Mobile ◄ 79%

0 5 10 15 20 25 30 35 Bring-up time (weeks) Note: Sample customer bring-up gains over traditional FPGA-based Prototyping solutions 11 © 2017 Cadence Design Systems, Inc. All rights reserved. Microsemi @ CDNLive … challenges & requirements

“The Cadence Protium S1 platform ensures scalability to hundreds of software developers at the earliest possible point during the development flow, and allows developers to focus on design validation and software development rather than prototype bring-up. The common flow with the Cadence Palladium Z1 emulation platform enables a smooth transition from emulation to prototyping, which greatly improves productivity.”

-Peter Ryser, Senior Director for System Software, Integration, and Validation, Xilinx

Protium G1 Protium S1-SC Protium S1-MC (2H 2017)

Single board Single chassis system Multi-chassis configuration • 1 FPGA • 2-8 FPGAs • 8-24 FPGAs • Up to 25M ASIC gates • Up to 200M ASIC gates • Up to 600M ASIC gates • Affordable and scalable • Flexible and scalable • Highest capacity • Highest performance • Fastest bring-up • Flexible use modes • Early software development • Unique SW debug capabilities • Advanced debug • IP verification • Early software development • High performance regression • HW/SW integration • Full system validation 15 © 2017 Cadence Design Systems, Inc. All rights reserved. Protium S1 System and Environment Comprehensive prototyping solution: High-performance and optimized

Software Multi-Fabric Compiler

ASIC RTL Debug probes (Verilog / VHDL / and trigger Accessories SV) conditions

M D e m e b o Integrated Compile r u g y HDL-ICE i c o Enginefor fast n compile s m 600MG p e r i t l B e e r o r a r d f i Partitioni l ng e

Board router

FPGA P&R

FPGA bit files

SpeedBridge® Hardware Interfaces

Transaction Interface

Memory Cards 25MG 200MG Memory Models

• Fast time-to-prototyping (months down to weeks) – No RTL changes – Automatic partitioning/memory compilation – Fully integrated FPGA place-and-route

• Scalable performance (3-100MHz) – From fully automatic to fully manual – Advanced black-box methodology

• Advanced software debug – Memory upload/download – Force and release – SCE-MI transaction interface

17 © 2017 Cadence Design Systems, Inc. All rights reserved. © 2017 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective holders. PCI Express and PCIe are registered trademarks of PCI-SIG.