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Cadence SPB / Orcad 17.4 System Requirements
A Parallel Systems Technical Note Cadence SPB / OrCAD 17.4 System Requirements Supported Operating Systems Windows 10 (64-bit) Professional, including Dark Theme mode Windows Server 2012 (All Service Packs) Windows Server 2012 R2 Windows Server 2016 Note: Cadence Allegro and OrCAD products do not support Windows 10 Starter and Home Basic. In addition, Windows Server support does not include support for Windows Remote Desktop. Windows RT and Tablets/Phones, including Windows 10 Phone, are not supported. Note: 64-bit Windows require 64-bit Flex software dongle drivers if using dongle-based licensing. Recommended Hardware Intel® Core™ i7 4.30 GHz or AMD Ryzen™ 7 4.30 GHz with at least 4 cores Note: Faster processors are preferred. 16 GB RAM 50 GB free disk space (SSD drive is recommended) 1920 x 1200 display resolution with true color (at least 32bit colour) A dedicated graphics card supporting OpenGL, minimum 2GB (with additional support for DX11 for 3D Canvas) Dual monitors (For physical design) Broadband Internet connection for some service Ethernet port/card (for network communications and security hostID) Three-button Microsoft-compatible mouse Supported MATLAB Version R2019A-64Bit (For the PSpice-MATLAB interface) Microsoft SharePoint for Allegro Pulse Cadence® Allegro® Pulse supports an interface to Microsoft SharePoint. Following are the requirements for SharePoint: • Windows Server 2012 (64-bit) • SharePoint Foundation 2013 • Microsoft SQL Server 2012 (64-bit) • Following 64-bit browsers: • Microsoft® Internet Explorer® 11.0 on windows • Mozilla Firefox 52.0 ESR on Windows • Mozilla Firefox 52.0 on Linux • Google Chrome 58.0 on Windows Using Spaces in File and Directory Names Support for spaces in file and directory names applies only to Windows. -
GS40 0.11-Μm CMOS Standard Cell/Gate Array
GS40 0.11-µm CMOS Standard Cell/Gate Array Version 1.0 January 29, 2001 Copyright Texas Instruments Incorporated, 2001 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the materials, methods, techniques, or apparatus described herein are the exclusive property of Texas Instruments. No disclosure of information or drawings shall be made to any other person or organization without the prior consent of Texas Instruments. IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this war- ranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (“Critical Applications”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WAR- RANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. -
Learning Openaccess Problem Areas Programmers Need to Understand Kevin Nesmith Chief Architect
Learning OpenAccess Problem Areas Programmers Need to Understand Kevin Nesmith Chief Architect June 25, 2014 Innova&on Through Collabora&ve R&D Overview • Why teach “Learning OpenAccess?” • Why OpenAccess? • Documentaon and training • ProBlems geng started • Uli?es • lib.defs (cds.lib) • Domains • Observers • Namespaces • Translators • Hierarchy • Some helpful tools – oaScript – oaDeBugging Suite • Who’s involved in this OpenAccess effort Innova&on Through Collabora&ve R&D 2 Why teach “Learning OpenAccess” at IEEE? Innova&on Through Collabora&ve R&D “ipsa sciena potestas est” • “Knowledge itself is power” (Sir Francis Bacon) • Knowing more about the inner workings of OpenAccess will make you more – Producve – Valuable • Improve your joB related proBlem solving skills • Reviewing what you already know keeps the informaon fresh in your Brain • Even if you only rememBer 1% from today, its more than what you knew yesterday Innova&on Through Collabora&ve R&D 4 Background of OpenAccess • mid 1990’s, SEMATECH created Chip Hierarchical Design System: Technical Data (CHDStd) • 1999 SEMATECH asked Si2 to take ownership of the CHDStd program to find a way to make is successful • This eventually lead to a new project called OpenAccess • To address concerns of CHDStd, a replacement for the CHDStd API was needed • Si2 put out a call for a technology contriBu?on • Cadence answered the call Innova&on Through Collabora&ve R&D 5 WHY OPENACCESS? Innova&on Through Collabora&ve R&D OpenAccess as a Concept • Eliminate translaon steps in the EDA flow • Prevent -
Electronic Design Automation Tools Part 2 by Christopher Henderson This Article Provides an Overview of the Electronic Design Automation (EDA) Design Tools
Issue 126 December 2019 Electronic Design Automation Tools Part 2 By Christopher Henderson This article provides an overview of the Electronic Design Automation (EDA) design tools. The EDA industry is an interesting ecosystem and bears discussing, so that the design engineer can Page 1 Electronic Design understand the environment. Automation Tools In last month’s feature article we discussed the three major EDA Part 2 tool suppliers: Cadence Design Systems, Synopsys, and Mentor Graphics, which is now owned by Siemens. Here in Part II we will Page 5 Technical Tidbit briefly discuss interoperability issues between the three major platforms. We’ll also discuss other suppliers developing tools in this area. Finally, we’ll discuss the use case and the strengths and Page 8 Ask the Experts weaknesses of the tool suites. Each of the three major EDA firms creates products that work well within their own portfolio, but what about across the three major Page 10 Spotlight providers? What if you want to create designs using tools from across two or more of the providers? This is a major challenge because it requires that one work with different formats for different files, which Page 13 Upcoming Courses requires translators, scripts and additional programs. What would be most useful is a good interoperability standard, and the good news is that there is one. It is called OpenAccess and is supported and promoted by the Silicon Integration Initiative. OpenAccess actually had its start as the result of a lawsuit against Cadence. Users sued Cadence, claiming that their internal format gave them a controlling monopoly in the design area, and a judge agreed with them. -
An Introduction to Openaccess Scripting
An Introduction to OpenAccess Scripting James D. Masters Intel Corp Design Automation Conference June 6, 2011 1 What is it? • Standalone direct interface to OpenAccess (OA) – No dependencies beyond OA and no licensing fees – Performance and memory usage is good for a scripting language • Matches C++ API with some melding to native language features – Existing C++ API documentation can be referenced – Auto conversions to/from native types (e.g. strings, integers, floats) • Includes convenience functions to reduce code and improve productivity – More natural interface; e.g. native array of (1.234, 9.876) instead of oaPoint(1234, 9876) 2 How does it work? Perl API Python API Ruby API Tcl API C# API Language-Specific Bindings Type Mapping Type Mapping Type Mapping Type Mapping Type Mapping Common Wrapper Architecture Interface Common SWIG Framework OA API C++ Programming Interface • Common interface through SWIG ensures cross-language consistency and reuse • All languages interface OA through the official OA API 3 Basic type mapping • Some basic OA types are mapped to native types in the target language Perl Python Ruby Tcl C# oaBoolean integer bool Boolean integer bool oa*Int integer int Fixnum integer int, uint, long,ulong oaFloat/Double Float float Float float float/double oaString string string String string string oaArray array array Array list IList<T> oaTime oaTime oaTime Time oaTime DateTime oaTimestamp integer int Fixnum integer uint oaComplex oaComplex complex OaComplex oaComplex oaComplex oaPoint oaPoint/array oaPoint/array OaPoint/Array -
Designcon 2016 Needs and Capabilities for Modeling Of
DesignCon 2016 Needs and Capabilities for Modeling of Capacitor Derating Panel discussion Brad Brim, Cadence Design Systems Istvan Novak, Oracle Tim Michalka, Qualcomm Technologies Wilmer Companioni, KEMET Electronics Shoji Tsubota, Murata Manufacturing Sam Chitwood, Cadence Design Systems Abstract Capacitors vary with temperature, bias voltage and age; a phenomenon typically referred to as derating. Libraries of SPICE or S-parameter models are provided by component manufacturers for non-derated components - new capacitors at a specific temperature and bias. Detailed derating data and related methodologies are often considered manufacturer-proprietary. Some manufacturers provide software to generate and display derated models while others specify general derating behavior in data sheets. OEMs have expressed a desire for more detailed and automated power integrity analyses to consider derating effects. Representatives from component manufacturers, OEMs and EDA will discuss these analysis needs and the electrical models required to support such. Audience participation is strongly encouraged to help judge the breadth of industry need in this area and help influence future contributions. TITLE Needs and Capabilities for Modeling of Capacitor Derating Moderator: Image Brad Brim (Cadence) Participants: Istvan Novak (Oracle) Tim Michalka (Qualcomm) Wilmer Companioni (KEMET) Shoji Tsubota (Murata) Sam Chitwood (Cadence) Needs and Capabilities for Modeling of Capacitor Derating Brad Brim (Cadence) 1 Moderator Brad Brim Product Engineering Architect, Cadence Design Systems [email protected] Brad has been in the EDA industry for more than 25 years. His graduate studies and initial commercial contributions were in the area of electromagnetic simulation and passive component modeling for circuit simulation. Some of the products he has worked on include: Momentum, ADS, HFSS, PowerSI and OptimizePI. -
ASIC Design Flow Steps [Makefile Targets] Synthesis Tool Descriptions
Identity development Research centre identities Institute for Communicating & Collaborative Systems Institute for Computing Systems Architecture Processor Automated Synthesis by iTerative Analysis Project Centre for Intelligent Systems http://groups.inf.ed.ac.uk/pasta/ & their Applications Laboratory for Foundations of Computer Science Institute of Perception, EnCore Processor Design Flow Action and Behaviour Institute for Adaptive & Neural Computation e-Science Institute RTL to Gates Synthesis Informatics Life-Sciences Institute Synthesis Tools ASIC Design Flow Steps [Makefile targets] Synthesis Tool Descriptions Floorplanning Configuration Start RTL-Description RTL Synthesis RTL Description Design Compiler rtl_config config Pre-processing/Compiling of micro-code definitions and of Verilog files. [dc_shell-t] RTL synthesis solution that performs advanced arithmetic optimisation, critical path synthesis, register retiming etc. It enables a developer to optimise a design for timing, IP Libraries area, power and test. RTL-to-Gates synthesis flow takes a RTL HW description and a standard cell Design Rule library as input, and produces a gate-level netlist as output. The resulting gate-level Checking netlist is a completely structural description with only standard cells at the leaves of RTL Vendor Logic Synthesis the design. This step also creates a SAIF (Switching Activity Interchange Format) Database Libraries Design forward-annotation file starting from the top level of the design. RTL to Placed rtl2gates synth GDS II OUT Compiler Power Optimisation & Analysis Gates Synthesis Layout [dc_shell-t] Power vs. Creates floorplan information including core size, placement sites, port locations, Compiler Power Compiler performs both RTL and gate-level power floorplan floorplan Schematic RAM locations, as well as routing and placement obstructions. -
GS30 Product Overview
GS30 0.15-µm CMOS Standard Cell/Gate Array Version 1.0 February, 2001 Copyright Texas Instruments Incorporated, 2001 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the materials, methods, techniques, or apparatus described herein are the exclusive property of Texas Instruments. No disclosure of information or drawings shall be made to any other person or organization without the prior consent of Texas Instruments. IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this war- ranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (“Critical Applications”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WAR- RANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. -
Cadence Design Systems, Inc
Confidential Cadence Design Systems, Inc. February/March 2019 Safe Harbor Statement and Regulation G Safe Harbor Statement The following discussion contains forward looking statements, and our actual results may differ materially from those expectations discussed here. Additional information concerning factors that could cause such a difference can be found in our Form 10-Q for the quarter ended September 29, 2018, our Form 10-K for the year ended December 29, 2018, the company’s future filings with the Securities and Exchange Commission and the cautionary statements regarding forward-looking statements in our February 19, 2019 earnings press release for the quarter ended December 29, 2018. Regulation G In addition to financial results prepared in accordance with Generally Accepted Accounting Principles, or GAAP, this presentation will also contain certain non-GAAP financial measures. Cadence management believes that in addition to using GAAP results in evaluating our business, it can also be useful to measure results using certain non-GAAP financial measures. Investors and potential investors are encouraged to review the reconciliation of non-GAAP financial measures with their most direct comparable GAAP financial results, including those set forth in our February 19, 2019 press release and our CFO Commentary for the quarter ended December 29, 2018, both of which can be found in the quarterly earnings section of the investor relations portion of our website at cadence.com. 2 © 2019 Cadence Design Systems, Inc. All rights reserved. Cadence-at-a-glance • Leading provider of system design enablement (SDE) solutions – software, hardware, and IP • Mission critical technology for designing today’s electronic systems • Culture of innovation - more than 20 significant new products in last 3 years • Subscription software model with very high customer renewal rates and loyalty • Revenue: ~$2.14B • Headquarters in Silicon Valley ~7500 employees worldwide NASDAQ: CDNS; S&P 500 & Nasdaq 100 indexes 3 © 2019 Cadence Design Systems, Inc. -
EDA Scripting Unleashed: Real-Life Examples Using Oascript and Oaxpop
EDA Scripting Unleashed: Real-Life Examples Using oaScript and oaxPop James D. Masters Intel Corp Si2CON October 6, 2015 1 Agenda • oaScript overview • oaxPop overview • Intel’s experience with oaScript and oaxPop – Framework bundle of required packages – Performance observations – Density Calculator application – Methodology Checker application • oaScript/oaxPop Roadmap • Summary 2 oaScript overview • Standalone direct interface to OpenAccess (OA) using Perl, Python, Ruby, or Tcl – Enables rapid development of powerful OA-based software – Performance and memory usage is mostly comparable to that of a C++ application (a few exceptions will be mentioned later) • Matches OA C++ API very closely – Existing C++ API documentation can be referenced – Auto conversion of types between C++ and scripting language • Includes convenience functions to reduce code and improve productivity • Initiated in 2009, and refined over the past 6 years in Si2’s oaScript working group (code base is stable) 3 oaScript interaction with OA API (via SWIG) Language-Specific Perl API Python API Ruby API Tcl API Bindings Type Mapping Type Mapping Type Mapping Type Mapping Common Wrapper Architecture Interface Common SWIG Framework C++ Programming OA API Interface • Uses the Simplified Wrapper and Interface Generator (SWIG) tool to expose C++ APIs to scripting languages – Common interface through SWIG ensures cross-language consistency and reuse – All languages interface OA through the official OA API 4 oaxPop overview • Provides high-speed polygon manipulation capabilities -
Cadence Design Systems, Inc. 2020 Proxy Statement
NOTICE OF 2020 ANNUAL MEETING OF STOCKHOLDERS The 2020 Annual Meeting of Stockholders of CADENCE DESIGN SYSTEMS, INC., a Delaware corporation, will be held as follows: When: Where: April 30, 2020 Cadence San Jose Campus 1:00 p.m. Pacific Time 2655 Seely Avenue, Building 10 San Jose, California 95134 Items of Business: The purpose of the 2020 Annual Meeting of Stockholders is to consider and take action on the following: 1. To elect the nine directors named in the proxy statement to serve until the 2021 Annual Meeting of Stockholders and until their successors are elected and qualified, or until the directors’ earlier death, resignation or removal. 2. To approve the amendment of the Omnibus Equity Incentive Plan. 3. To vote on an advisory resolution to approve named executive officer compensation. 4. To ratify the selection of PricewaterhouseCoopers LLP as the independent registered public accounting firm of Cadence for its fiscal year ending January 2, 2021. 5. To vote on a stockholder proposal regarding special stockholder meetings, if properly presented at the meeting. 6. To transact such other business as may properly come before the meeting or any adjournment or postponement thereof. These items of business are more fully described in the proxy statement accompanying this notice. Record Date: Holders of Cadence Design Systems, Inc. common stock at the close of business on March 2, 2020 are entitled to notice of and to vote at the 2020 Annual Meeting of Stockholders and any adjournment or postponement thereof. How to Vote: Your vote is important to us. Please cast your vote promptly via the internet, telephone or mail. -
Cadence Design Systems, Inc. Incoming Letter Dated December 21, 2018
UNITED STATES SECURITIES AND EXCHANGE COMMISSION WASHINGTON, D .C. 20549 DIVISION OF CORPORATION FINANCE February 27, 2019 John P. Kelsh Sidley Austin LLP [email protected] Re: Cadence Design Systems, Inc. Incoming letter dated December 21, 2018 Dear Mr. Kelsh: This letter is in response to your correspondence dated December 21, 2018 and February 12, 2019 concerning the shareholder proposal (the “Proposal”) submitted to Cadence Design Systems, Inc. (the “Company”) by John Chevedden (the “Proponent”) for inclusion in the Company’s proxy materials for its upcoming annual meeting of security holders. We also have received correspondence from the Proponent dated December 27, 2018, January 25, 2019 and February 24, 2019. Copies of all of the correspondence on which this response is based will be made available on our website at http://www.sec.gov/divisions/corpfin/cf-noaction/14a-8.shtml. For your reference, a brief discussion of the Division’s informal procedures regarding shareholder proposals is also available at the same website address. Sincerely, M. Hughes Bates Special Counsel Enclosure cc: John Chevedden *** *** FISMA & OMB Memorandum M-07-16 February 27, 2019 Response of the Office of Chief Counsel Division of Corporation Finance Re: Cadence Design Systems, Inc. Incoming letter dated December 21, 2018 The Proposal requests that the board take each step necessary so that each voting requirement in the Company’s charter and bylaws (that is explicit or implicit due to default to state law) that calls for a greater than simple majority vote be eliminated and replaced by a requirement for a majority of the votes cast for and against applicable proposals, or a simple majority in compliance with applicable laws.