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Virtuoso System Design Platform Unified “System-Aware” Platform for IC and Package Design

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Virtuoso System Design Platform Unified “System-Aware” Platform for IC and Package Design Virtuoso System Design Platform Unified “system-aware” platform for IC and package design The Cadence® Virtuoso® System Design Platform is a holistic, system-based solution that provides the functionality to drive simulation and LVS-clean layout of ICs and packages from a single schematic. There are two key flows: implementation and analysis. The implementation flow is used to create an IC package schematic in Virtuoso Schematic Editor and then transfer the schematic data to Cadence SiP Layout to layout the physical design. In addition, this flow offers the capability to generate and verify library parts, output a bill of materials (BOM), and perform layout versus schematic (LVS) checking. The analysis flow is used to extract and simulate any portion of the system (IC-package-PCB) regardless of the layout design status. Moreover, this flow offers the capability to automatically generate schematics for the PCB and IC package layouts, bind the instances of the IC package to the IC schematic or models, and build testbenches to simulate the system using the Virtuoso ADE Product Suite plus Spectre® Multi-Mode Simulation interface. Cadence Sigrity™ models extracted from the PCB and IC package layouts get automatically stitched into the generated schematic. Seamless package/board-level layout parasitic back-annotation flow Virtuoso “Chip” View Virtuoso Schematic Sigrity Extracted Representing System-Level Design Cadence SiP Layout Interconnect Model HPJ VSS Single source schematic automates package-level LVS RST RX1 KEY SP TX1 Allegro GaN Constraints VID RGB Lib Connectivity AUD VCC IC to package co-design flow with LVL checking ® LVS Allegro Footprints Si GaAs Sip Design Si GaAs GaN Virtuoso SE Symbol Virtuoso SE Symbol Virtuoso SE Symbol 6SN7 470 p Q1 2 5 0.01 µf Automated package-level library development Automated package-level library 1 4 H T1 500 KΩ R2 Volume 3 7 8 6 R Outside Sourced Design Virtuoso Design Virtuoso Design Figure 1: Virtuoso System Design Platform Flow Virtuoso System Design Platform Introduction identify and eliminate such errors at easily co-design between the die and the an early design stage and long before package to achieve better package-level The task of designing a chip that meets tapeout, it is essential to have a familiar routing and/or wire bonding. all product expectations once placed into design and simulation environment that a package and then onto a PCB is very The Virtuoso System Design Platform auto-enables the IC designer to simulate challenging. With the recent growth in analysis flow allows the IC designer to the IC in context of the entire PCB and heterogeneous integration, now consider import a PCB and package layout with package system and its parasitics. While designing multiple chips, across multiple its corresponding parasitic models, repre- such an environment exists for simulating technologies, that integrate onto a single sented by S-parameters or SPICE, to the I/O to I/O interconnects for digital ICs, package and then are integrated onto IC design environment. The flow reads the the Virtuoso System Design Platform is a PCB. For even the most experienced PCB or package connectivity and creates a the first seamless flow of its kind that designers, this can be a frightening schematic with parasitic models stitched- allows simulation of the analog/RF IC in proposition. in. The schematic becomes ready to context of a complete PCB/package circuit simulate in context of the PCB or package system. Unification of the Virtuoso and Allegro/Sigrity Platforms The Virtuoso System Design Platform environment helps to integrate and simulate the IC in context of all such package/PCB interconnects and external components. This assumes greater impor- tance because the IC, package, and IC Package PCB PCB are typically designed by different teams using different design tools across Figure 2: How IC, package, and PCB relate geographic locations, all independent of the others and at different stages of the design cycle. The Virtuoso System Today, designing at the “system- inclusive of parasitics. This flow empowers Design Platform brings the package and level” (IC-package-PCB) involves a lot the IC designer and minimizes design PCB-level layout parasitics into a common of educated guesswork regarding the iterations. schematic, enabling cross-domain downstream effects of the package/PCB simulation of the complete system. This The Virtuoso System Design Platform on the performance and reliability of helps designers identify critical perfor- provides an IC-centric solution with your chip(s). The Virtuoso System Design mance deviations before tapeout. both a top-down implementation flow Platform takes this guesswork out of Communication of required modifications and bottom-up analysis-centric flow. designing chips accounting for system- can then be driven directly to package/ The analysis-based flow helps bring in level effects. PCB teams. the complete simulation environment, Traditionally, the analog/RF IC designer requiring minimal knowledge in PCB or An important feature here is to intel- would only simulate standalone ICs package and electromagnetic simulation ligently stitch the parasitics models into without considering the effects of the domains. A colossal improvement in the simulation schematic. If the models package and PCB. The package contains productivity is predicted with such an also contain discrete devices, they should a single or multiple ICs and interconnects. integrated solution. be auto-filtered when the simulation It also probably contains discrete compo- schematic is created so that they are not The Virtuoso System Design Platform nents required by the ICs to function. double-counted in the simulation. implementation flow provides the Similarly, the PCB contains several capability to drive IC and package packages and interconnects and discrete layout through a single schematic components. It is important to simulate editor. By having the same schematic the entire system together to capture the editor (Virtuoso Schematic Editor), the performance at high frequencies. Because IC designer is in a much better position the IC designer and the package designer to do system-level design in a common use different schematic entry tools, the environment with pre-layout system IC designer must re-capture the package simulations (IC and package together) and system schematic as a testbench around then drive the layout of the respective the IC schematic to do combined system domain. This flow also automates much simulations. Earlier, such system analysis of the package-level library development had been largely a manual effort with process by generating die footprints to be error-prone stitching of package models used in SiP Layout. Advanced users can to the rest of the system schematic. To www.cadence.com 2 Virtuoso System Design Platform Virtuoso System Design There are primarily two flows in the Once your package or PCB is designed Platform Virtuoso System Design Platform, the using the implementation flow described implementation and the analysis flow. above, the analysis flow lets you import The Virtuoso System Design Platform flow The implementation flow allows you to PCB and package layout in the Virtuoso traces through the following products design schematics of packages in the environment as a schematic along with in the IC, package, PCB, and EM solver Virtuoso Schematic Editor before pushing the automatically stitched parasitic models domains: it to a package layout editor. It further of the components and traces early in the • Virtuoso Schematic Editor: For creating allows you to export die footprints and design cycle, and carry out a parasitic- the package schematic symbols from the Virtuoso Layout Suite aware system-level simulation. You can and use them to construct a package simulate such a system, identify critical • Virtuoso Layout Suite: For die export schematic. The bidirectional flow of performance metric deviation early, and • Cadence SiP Layout XL: For design and data dynamically propagates edits in the communicate required modifications to layout of multi-die packages schematic to SiP Layout and conversely. the package and PCB teams. • Sigrity EM solvers: For extracting Generating a BOM, visualizing design models of PCB and package differences in an intuitive manner, and looking at layout reports constitute some • Spectre Multi-Mode Simulation: For of the other key features of this flow. enabling system simulations Virtuoso System Design Platform Virtuoso IC Domain IC Layout and Package/Module-Level Schematic Virtuoso ADE-MTS Circuit Simulation Connectivity/Discrete Devices and LVS Smart N-Port S-Parameters Smart N-Port DFII Bidirectional Connectivity/ DFII Library Constraints with LVS Library Device Model Mapping File BOM Package/PCB Sigrity Domain Allegro Arbitrary Structure Modeling Library Parasitic Extraction Physical Package and PCB Design Implementation (Top-Down) Flow Allegro Analysis (Bottom-Up) Flow Figure 3: The Virtuoso System Design Platform flow Benefits • Creates a package or PCB parasitic- Features aware schematic that can be simulated By integrating the Virtuoso, Allegro, with the Virtuoso Analog Design Die export Sigrity, and Spectre platforms, the Environment including multi-technology The Virtuoso System Design Platform Virtuoso System Design Platform entails simulations. This is an essential provides a key feature to generate the following three key benefits: mechanism to realize complete system- footprint and symbol information from a • Updates the
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