Virtuoso System Design Platform Unified “system-aware” platform for IC and package design

The Cadence® Virtuoso® System Design Platform is a holistic, system-based solution that provides the functionality to drive simulation and LVS-clean layout of ICs and packages from a single schematic. There are two key flows: implementation and analysis.

The implementation flow is used to create an IC package schematic in Virtuoso Schematic Editor and then transfer the schematic data to Cadence SiP Layout to layout the physical design. In addition, this flow offers the capability to generate and verify library parts, output a bill of materials (BOM), and perform layout versus schematic (LVS) checking.

The analysis flow is used to extract and simulate any portion of the system (IC-package-PCB) regardless of the layout design status. Moreover, this flow offers the capability to automatically generate schematics for the PCB and IC package layouts, bind the instances of the IC package to the IC schematic or models, and build testbenches to simulate the system using the Virtuoso ADE Product Suite plus Spectre® Multi-Mode Simulation interface. Cadence Sigrity™ models extracted from the PCB and IC package layouts get automatically stitched into the generated schematic.

Seamless package/board-level layout parasitic back-annotation flow

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Figure 1: Virtuoso System Design Platform Flow Virtuoso System Design Platform

Introduction identify and eliminate such errors at easily co-design between the die and the an early design stage and long before package to achieve better package-level The task of designing a chip that meets tapeout, it is essential to have a familiar routing and/or wire bonding. all product expectations once placed into design and simulation environment that a package and then onto a PCB is very The Virtuoso System Design Platform auto-enables the IC designer to simulate challenging. With the recent growth in analysis flow allows the IC designer to the IC in context of the entire PCB and heterogeneous integration, now consider import a PCB and package layout with package system and its parasitics. While designing multiple chips, across multiple its corresponding parasitic models, repre- such an environment exists for simulating technologies, that integrate onto a single sented by S-parameters or SPICE, to the I/O to I/O interconnects for digital ICs, package and then are integrated onto IC design environment. The flow reads the the Virtuoso System Design Platform is a PCB. For even the most experienced PCB or package connectivity and creates a the first seamless flow of its kind that designers, this can be a frightening schematic with parasitic models stitched- allows simulation of the analog/RF IC in proposition. in. The schematic becomes ready to context of a complete PCB/package circuit simulate in context of the PCB or package system. Unification of the Virtuoso and Allegro/Sigrity Platforms The Virtuoso System Design Platform environment helps to integrate and simulate the IC in context of all such package/PCB interconnects and external components. This assumes greater impor- tance because the IC, package, and IC Package PCB PCB are typically designed by different teams using different design tools across Figure 2: How IC, package, and PCB relate geographic locations, all independent of the others and at different stages of the design cycle. The Virtuoso System Today, designing at the “system- inclusive of parasitics. This flow empowers Design Platform brings the package and level” (IC-package-PCB) involves a lot the IC designer and minimizes design PCB-level layout parasitics into a common of educated guesswork regarding the iterations. schematic, enabling cross-domain downstream effects of the package/PCB simulation of the complete system. This The Virtuoso System Design Platform on the performance and reliability of helps designers identify critical perfor- provides an IC-centric solution with your chip(s). The Virtuoso System Design mance deviations before tapeout. both a top-down implementation flow Platform takes this guesswork out of Communication of required modifications and bottom-up analysis-centric flow. designing chips accounting for system- can then be driven directly to package/ The analysis-based flow helps bring in level effects. PCB teams. the complete simulation environment, Traditionally, the analog/RF IC designer requiring minimal knowledge in PCB or An important feature here is to - would only simulate standalone ICs package and electromagnetic simulation ligently stitch the parasitics models into without considering the effects of the domains. A colossal improvement in the simulation schematic. If the models package and PCB. The package contains productivity is predicted with such an also contain discrete devices, they should a single or multiple ICs and interconnects. integrated solution. be auto-filtered when the simulation It also probably contains discrete compo- schematic is created so that they are not The Virtuoso System Design Platform nents required by the ICs to function. double-counted in the simulation. implementation flow provides the Similarly, the PCB contains several capability to drive IC and package packages and interconnects and discrete layout through a single schematic components. It is important to simulate editor. By having the same schematic the entire system together to capture the editor (Virtuoso Schematic Editor), the performance at high frequencies. Because IC designer is in a much better position the IC designer and the package designer to do system-level design in a common use different schematic entry tools, the environment with pre-layout system IC designer must re-capture the package simulations (IC and package together) and system schematic as a testbench around then drive the layout of the respective the IC schematic to do combined system domain. This flow also automates much simulations. Earlier, such system analysis of the package-level library development had been largely a manual effort with process by generating die footprints to be error-prone stitching of package models used in SiP Layout. Advanced users can to the rest of the system schematic. To

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Virtuoso System Design There are primarily two flows in the Once your package or PCB is designed Platform Virtuoso System Design Platform, the using the implementation flow described implementation and the analysis flow. above, the analysis flow lets you import The Virtuoso System Design Platform flow The implementation flow allows you to PCB and package layout in the Virtuoso traces through the following products design schematics of packages in the environment as a schematic along with in the IC, package, PCB, and EM solver Virtuoso Schematic Editor before pushing the automatically stitched parasitic models domains: it to a package layout editor. It further of the components and traces early in the • Virtuoso Schematic Editor: For creating allows you to export die footprints and design cycle, and carry out a parasitic- the package schematic symbols from the Virtuoso Layout Suite aware system-level simulation. You can and use them to construct a package simulate such a system, identify critical • Virtuoso Layout Suite: For die export schematic. The bidirectional flow of performance metric deviation early, and • Cadence SiP Layout XL: For design and data dynamically propagates edits in the communicate required modifications to layout of multi-die packages schematic to SiP Layout and conversely. the package and PCB teams. • Sigrity EM solvers: For extracting Generating a BOM, visualizing design models of PCB and package differences in an intuitive manner, and looking at layout reports constitute some • Spectre Multi-Mode Simulation: For of the other key features of this flow. enabling system simulations

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Physical Package and PCB Design Implementation (Top-Down) Flow Allegro Analysis (Bottom-Up) Flow

Figure 3: The Virtuoso System Design Platform flow

Benefits • Creates a package or PCB parasitic- Features aware schematic that can be simulated By integrating the Virtuoso, Allegro, with the Virtuoso Analog Design Die export Sigrity, and Spectre platforms, the Environment including multi-technology The Virtuoso System Design Platform Virtuoso System Design Platform entails simulations. This is an essential provides a key feature to generate the following three key benefits: mechanism to realize complete system- footprint and symbol information from a • Updates the IC layout and package aware simulations. Virtuoso layout for use in constructing a layout design using the Virtuoso • Designs IC and package layout through package schematic and a package layout. Schematic Editor. Therefore, in addition the co-design die abstract flow This also allows simultaneous co-design to the IC layout, you can now design simultaneously. This minimizes design of the IC and package layout and helps the schematic for a package layout. The iterations and cuts down on very-late- minimize design iterations. Virtuoso Schematic Editor provides a stage floorplanning and design single schematic editor-driven IC and feasibility issues. package design.

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Schematic Symbol Preserved Logical Intent

IC Layout

Die Abstract

Figure 4: Die abstracts

Creating a project and assigning Editing in the SiP Layout and ences in a highly intuitive and graphical part table files back-annotating in the Virtuoso manner utilizing the Annotation Browser Schematic Editor assistant in the Virtuoso Schematic Editor. While creating a package schematic, it is imperative to efficiently select parts that During a design cycle, it is quite possible Generating a BOM report are supplied by a vendor. The part table that the layout engineer recommends A BOM report lists all the components file option lets you seamlessly select from changes that need to be matched in used in a design along with the part as many as a million parts from different the Virtuoso Schematic Editor. This numbers and values of the different vendors and assign them effectively on feature enables transferring information properties of each component. This is an the instances in your schematic. seamlessly to the Virtuoso Schematic extremely important input for an original Editor and ensures that the schematic and Transferring the schematic equipment manufacturer (OEM). The layout are always in sync. information to SiP Layout Virtuoso System Design Platform provides Design-differentiating layout vs. a user-friendly and highly customizable Once the schematic with all the parts is schematic check environment to generate all such reports. created, this feature enables the seamless transfer of the schematic information to Provides a signoff-quality LVS check the SiP Layout editor. Subsequently, you highlighting nets, components, and can place all the parts in the SiP Layout similar differences between the layout and editor and start creating routes and the schematic. It also flags design shorts, complete the finished package. unplaced components on the layout, and DRC checks. It reports all the differ-

Figure 5: Selecting a package-level part from the part table file in the implementation schematic

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Figure 6: Schematic driving package layout

Analysis Flow Features Binding the IC footprint to its Automatic creation of testbench underlying schematic or sub-circuit symbol for top-level system You can start utilizing the analysis flow model simulations once you have the design of a fully routed package. Once the parasitic-aware schematic is Creation of a testbench symbol is an created, the IC is imported as a simple easy, automatic, and seamless feature of Creating a parasitic-aware PCB/ footprint. The next important step is testbench generation and is an integral package schematic in Virtuoso to bind this footprint to the original IC part of the analysis flow. It reduces the Schematic Editor schematic symbol or sub-circuit. This is design time and creates compact and the same symbol that the IC designer Another key feature enables you to manageable testbenches for you to start has been using in the top-level IC simula- create a PCB or package schematic with an early evaluation and subsequent fix of tions. The Virtuoso System Design S-parameters and SPICE models of the the system. Platform provides an intelligent mapping traces and PCB or package components mechanism to create a 1:1 map between automatically stitched in, all using the Simulation layout vs. schematic the footprint terminals and the IC symbol Virtuoso Schematic Editor. check terminals. In cases where a schematic or a It is noteworthy to highlight the analysis schematic symbol is not present, it allows The simulation layout versus schematic flow ability to use a device mapping text binding to a sub-circuit model of the IC. check feature helps to flag any differ- file to automatically replace SMDs with ences between the created schematic and their corresponding vendor-specified the layout from which it was originally S-parameters and SPICE models while created. This feature is essential because creating the schematic. Previously, the very often a designer tends to tweak schematic creation with all the models in his top-level schematic to arrive at the place was a manual, tedious, and error- desired results. prone process.

Figure 7: Viewing LVS differences highlighted in the Annotation Browser www.cadence.com 5 Virtuoso System Design Platform

Specifications Platform/OS Cadence Services and Support

Third-party support • Linux for tools based on Virtuoso • Cadence application engineers can platform answer your technical questions by Allows seamless import of third-party • Linux, Windows for telephone, email, or Internet—they can vendor-supplied models of SMDs into the tools based on Allegro and Sigrity also provide technical assistance and parasitic-aware PCB/package schematic technologies custom training Design input • Cadence-certified instructors teach Tools that may be required to run more than 70 courses and bring • Design libraries including parasitic the Virtuoso System Design Platform models (SPICE and S-parameters) their real-world experience into the flow classroom • Virtuoso Layout Suite die • Virtuoso Schematic Editor XL • More than 25 Internet Learning • Allegro PCB/package layout • Virtuoso Layout Editor Series (iLS) online courses allow you the flexibility of training at your own • Sigrity models representing parasitic • Virtuoso Analog Design Environment models of the traces and components computer via the Internet • Spectre Multi-Mode Simulation, on the PCB/package • Cadence Online Support gives you Spectre RF Option • Device models of SMD’s SiP layout 24x7 online access to a knowledgebase • Allegro SiP and PCB layout editor of the latest solutions, technical • Virtuoso Schematic Editor schematic • Sigrity PowerSI®, Sigrity PowerSI 3D documentation, software downloads, • Parasitic-aware simulation schematic EM Extraction Option, and Sigrity and more • Footprint of dies designed in Virtuoso XtractIM™ technology • For more information, please visit Layout Suite www.cadence.com/support for support and www.cadence.com/training for training

Cadence software, hardware, and semiconductor IP enable electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work, and play. The company’s Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems. www.cadence.com

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