Cadence Design Systems, Inc

Total Page:16

File Type:pdf, Size:1020Kb

Cadence Design Systems, Inc Confidential Cadence Design Systems, Inc. February/March 2019 Safe Harbor Statement and Regulation G Safe Harbor Statement The following discussion contains forward looking statements, and our actual results may differ materially from those expectations discussed here. Additional information concerning factors that could cause such a difference can be found in our Form 10-Q for the quarter ended September 29, 2018, our Form 10-K for the year ended December 29, 2018, the company’s future filings with the Securities and Exchange Commission and the cautionary statements regarding forward-looking statements in our February 19, 2019 earnings press release for the quarter ended December 29, 2018. Regulation G In addition to financial results prepared in accordance with Generally Accepted Accounting Principles, or GAAP, this presentation will also contain certain non-GAAP financial measures. Cadence management believes that in addition to using GAAP results in evaluating our business, it can also be useful to measure results using certain non-GAAP financial measures. Investors and potential investors are encouraged to review the reconciliation of non-GAAP financial measures with their most direct comparable GAAP financial results, including those set forth in our February 19, 2019 press release and our CFO Commentary for the quarter ended December 29, 2018, both of which can be found in the quarterly earnings section of the investor relations portion of our website at cadence.com. 2 © 2019 Cadence Design Systems, Inc. All rights reserved. Cadence-at-a-glance • Leading provider of system design enablement (SDE) solutions – software, hardware, and IP • Mission critical technology for designing today’s electronic systems • Culture of innovation - more than 20 significant new products in last 3 years • Subscription software model with very high customer renewal rates and loyalty • Revenue: ~$2.14B • Headquarters in Silicon Valley ~7500 employees worldwide NASDAQ: CDNS; S&P 500 & Nasdaq 100 indexes 3 © 2019 Cadence Design Systems, Inc. All rights reserved. Financial summary 2018 2500 Revenue 2000 1 Revenue 1500 $2.14B 1000 ($ millions) 500 Non-GAAP 0 operating 2012 2013 2014 2015 2016 2017 2018 margin1 30% 1 $2.00 Non-GAAP EPS $1.75 Free $1.50 cash flow $1.25 $1.00 $543M $0.75 $0.50 $0.25 $0.00 2012 2013 2014 2015 2016 2017 2018 Notes: 1. Non-GAAP operating margin and non-GAAP EPS (excludes amortization of acquired intangibles, stock-based compensation, non-qualified deferred compensation expenses and certain non-recurring cash expenses. See quarterly earnings releases and CFO Commentary for reconciliations to GAAP measures. 4 © 2019 Cadence Design Systems, Inc. All rights reserved. Industry landscape . Cadence and its peers develop highly specialized software, hardware, and IP solutions for the automated design and verification of electronic products and SDE/EDA economics within systems the 2017 electronics framework . Our technology is critical to semiconductors, Applications and is increasingly deployed by a variety of systems companies Electronic Systems $1.50T Semi $445B SDE/EDA & IP $9.8B Source: The McClean Report, 2018, ESD Alliance Market Survey Service Q4 2017, Cadence analysis 5 © 2019 Cadence Design Systems, Inc. All rights reserved. Data-driven economy (DDE) drives growth opportunities Data Data Creation Storage Data Data Transmission Analytics 6 © 2019 Cadence Design Systems, Inc. All rights reserved. Key technology waves propel DDE Mobile Edge computing Machine learning Automotive Datacenter 7 © 2019 Cadence Design Systems, Inc. All rights reserved. System Design Enablement (SDE) strategy MOBILE DATACENTER EDGE COMPUTING AUTOMOTIVE AERO & DEFENSE AND MORE… SYSTEM INTEGRATION System analysis * HW-SW verification * Software applications SECURITY PACKAGE AND BOARD I PCB design * Package design * PCB and package analysis P CHIP (Core EDA) Design and implementation * IP/SoC verification * Software drivers Partnerships with Ecosystem Leaders 8 © 2019 Cadence Design Systems, Inc. All rights reserved. SDE – expanding beyond traditional EDA . Strategy takes end-product view and provide tools and content that enable system development . Core EDA at the heart of the SDE strategy − Deliver innovative, differentiated core products & flows − Tight partnerships with top customers and key ecosystem players . Provide comprehensive printed circuit board and IC package design solutions . Offer focused and differentiated IP portfolio . Expand to system level through solutions for HW/SW integration, software development and system analysis . Gear solutions to specific vertical markets 9 © 2019 Cadence Design Systems, Inc. All rights reserved. Innovation – engine of growth More than 20 significant new products in past 3 years Tensilica 112G SerDes USB Type-C Vision C5 IP IP DSP Legato Cadence Legato™ Virtuoso® Memory Cloud Reliability RF Solution Solution Tensilica® Pegasus Liberate™ 2018 TSMC VDE Vision Verification Allegro Pulse Trio Q6 DSP System Tensilica Tensilica OrCAD® Tensilica Vision P5 DNA 100 Capture Cloud HiFi 3z DSP DSP Genus™ Protium S1 Next-Gen Conformal Synthesis Prototyping Virtuoso ADE Smart LEC Solution Platform Innovus™ Joules™ Tensilica Virtuoso Implementation RTL Power Fusion G3 System Design System Solution DSP Platform Indago™ Modus™ Xcelium Allegro PCB 2015 - 2017 Debug DFT Software Parallel DesignTrue Platform Solution Simulator Tensilica® Next Gen CCIX VIP Stratus™ HLS Vision P6 Jasper Gold and DIP DSP Palladium® Z1 Tensilica Enterprise JasperGold Fusion DSP Emulation RTL Signoff Platform 10 © 2019 Cadence Design Systems, Inc. All rights reserved. Recurring revenue model High visibility software revenue stream . ~90% of total revenue recognized over time . Backlog: $2.8B (Q4’18) Revenue Revenue growth 600 . 10% (2018/2017) 500 400 300 ($ millions) 200 100 0 2012 2013 2014 2015 2016 2017 2018 11 © 2019 Cadence Design Systems, Inc. All rights reserved. Diversified business across products and regions Verification Americas 12% 8% Digital 24% Asia Analog 9% 19% PCB/Pkg EMEA 45% IP Japan 26% 29% 28% Revenue mix for 2018 12 © 2019 Cadence Design Systems, Inc. All rights reserved. Driving profitable growth Strong operating profitability: . Focus on growth and disciplined ROI-centric resource allocation . Non-GAAP operating margin 30%1 (2018) Non-GAAP Operating Margin1 35% 30% 25% 20% 15% 10% 5% 0% 2012 2013 2014 2015 2016 2017 2018 Notes: 1. Non-GAAP operating margin and non-GAAP EPS (excludes amortization of acquired intangibles, stock-based compensation, non-qualified deferred compensation expenses and certain non-recurring cash expenses. See quarterly earnings releases and CFO Commentary for reconciliations to GAAP measures. 13 © 2019 Cadence Design Systems, Inc. All rights reserved. Cash flow, capital structure and uses of cash Free cash flow Free cash flow generation 600 500 . $543M (2018) 400 ($ millions) ($ 300 Capital structure (Q4‘18) 200 . Cash: $533M 100 . LT Debt: $450M 0 2012 2013 2014 2015 2016 2017 2018 . Credit facility: $350M ($100M drawn) Stock repurchase 1200 Capital allocation 1000 . Internal investment 800 . M&A millions) ($ 600 . Repurchase stock 400 200 0 2012 2013 2014 2015 2016 2017 2018 14 © 2019 Cadence Design Systems, Inc. All rights reserved. In summary . Mission critical solutions for designing semiconductors and electronic systems . Data-driven economy and supporting technology waves drive growth . Culture of innovation creates the products for growth . Growth, focus and discipline drive financial performance 15 © 2019 Cadence Design Systems, Inc. All rights reserved. © 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners..
Recommended publications
  • Cadence SPB / Orcad 17.4 System Requirements
    A Parallel Systems Technical Note Cadence SPB / OrCAD 17.4 System Requirements Supported Operating Systems Windows 10 (64-bit) Professional, including Dark Theme mode Windows Server 2012 (All Service Packs) Windows Server 2012 R2 Windows Server 2016 Note: Cadence Allegro and OrCAD products do not support Windows 10 Starter and Home Basic. In addition, Windows Server support does not include support for Windows Remote Desktop. Windows RT and Tablets/Phones, including Windows 10 Phone, are not supported. Note: 64-bit Windows require 64-bit Flex software dongle drivers if using dongle-based licensing. Recommended Hardware Intel® Core™ i7 4.30 GHz or AMD Ryzen™ 7 4.30 GHz with at least 4 cores Note: Faster processors are preferred. 16 GB RAM 50 GB free disk space (SSD drive is recommended) 1920 x 1200 display resolution with true color (at least 32bit colour) A dedicated graphics card supporting OpenGL, minimum 2GB (with additional support for DX11 for 3D Canvas) Dual monitors (For physical design) Broadband Internet connection for some service Ethernet port/card (for network communications and security hostID) Three-button Microsoft-compatible mouse Supported MATLAB Version R2019A-64Bit (For the PSpice-MATLAB interface) Microsoft SharePoint for Allegro Pulse Cadence® Allegro® Pulse supports an interface to Microsoft SharePoint. Following are the requirements for SharePoint: • Windows Server 2012 (64-bit) • SharePoint Foundation 2013 • Microsoft SQL Server 2012 (64-bit) • Following 64-bit browsers: • Microsoft® Internet Explorer® 11.0 on windows • Mozilla Firefox 52.0 ESR on Windows • Mozilla Firefox 52.0 on Linux • Google Chrome 58.0 on Windows Using Spaces in File and Directory Names Support for spaces in file and directory names applies only to Windows.
    [Show full text]
  • GS40 0.11-Μm CMOS Standard Cell/Gate Array
    GS40 0.11-µm CMOS Standard Cell/Gate Array Version 1.0 January 29, 2001 Copyright Texas Instruments Incorporated, 2001 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the materials, methods, techniques, or apparatus described herein are the exclusive property of Texas Instruments. No disclosure of information or drawings shall be made to any other person or organization without the prior consent of Texas Instruments. IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this war- ranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (“Critical Applications”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WAR- RANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
    [Show full text]
  • Designcon 2016 Needs and Capabilities for Modeling Of
    DesignCon 2016 Needs and Capabilities for Modeling of Capacitor Derating Panel discussion Brad Brim, Cadence Design Systems Istvan Novak, Oracle Tim Michalka, Qualcomm Technologies Wilmer Companioni, KEMET Electronics Shoji Tsubota, Murata Manufacturing Sam Chitwood, Cadence Design Systems Abstract Capacitors vary with temperature, bias voltage and age; a phenomenon typically referred to as derating. Libraries of SPICE or S-parameter models are provided by component manufacturers for non-derated components - new capacitors at a specific temperature and bias. Detailed derating data and related methodologies are often considered manufacturer-proprietary. Some manufacturers provide software to generate and display derated models while others specify general derating behavior in data sheets. OEMs have expressed a desire for more detailed and automated power integrity analyses to consider derating effects. Representatives from component manufacturers, OEMs and EDA will discuss these analysis needs and the electrical models required to support such. Audience participation is strongly encouraged to help judge the breadth of industry need in this area and help influence future contributions. TITLE Needs and Capabilities for Modeling of Capacitor Derating Moderator: Image Brad Brim (Cadence) Participants: Istvan Novak (Oracle) Tim Michalka (Qualcomm) Wilmer Companioni (KEMET) Shoji Tsubota (Murata) Sam Chitwood (Cadence) Needs and Capabilities for Modeling of Capacitor Derating Brad Brim (Cadence) 1 Moderator Brad Brim Product Engineering Architect, Cadence Design Systems [email protected] Brad has been in the EDA industry for more than 25 years. His graduate studies and initial commercial contributions were in the area of electromagnetic simulation and passive component modeling for circuit simulation. Some of the products he has worked on include: Momentum, ADS, HFSS, PowerSI and OptimizePI.
    [Show full text]
  • GS30 Product Overview
    GS30 0.15-µm CMOS Standard Cell/Gate Array Version 1.0 February, 2001 Copyright Texas Instruments Incorporated, 2001 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the materials, methods, techniques, or apparatus described herein are the exclusive property of Texas Instruments. No disclosure of information or drawings shall be made to any other person or organization without the prior consent of Texas Instruments. IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this war- ranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (“Critical Applications”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WAR- RANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
    [Show full text]
  • Cadence Design Systems, Inc. 2020 Proxy Statement
    NOTICE OF 2020 ANNUAL MEETING OF STOCKHOLDERS The 2020 Annual Meeting of Stockholders of CADENCE DESIGN SYSTEMS, INC., a Delaware corporation, will be held as follows: When: Where: April 30, 2020 Cadence San Jose Campus 1:00 p.m. Pacific Time 2655 Seely Avenue, Building 10 San Jose, California 95134 Items of Business: The purpose of the 2020 Annual Meeting of Stockholders is to consider and take action on the following: 1. To elect the nine directors named in the proxy statement to serve until the 2021 Annual Meeting of Stockholders and until their successors are elected and qualified, or until the directors’ earlier death, resignation or removal. 2. To approve the amendment of the Omnibus Equity Incentive Plan. 3. To vote on an advisory resolution to approve named executive officer compensation. 4. To ratify the selection of PricewaterhouseCoopers LLP as the independent registered public accounting firm of Cadence for its fiscal year ending January 2, 2021. 5. To vote on a stockholder proposal regarding special stockholder meetings, if properly presented at the meeting. 6. To transact such other business as may properly come before the meeting or any adjournment or postponement thereof. These items of business are more fully described in the proxy statement accompanying this notice. Record Date: Holders of Cadence Design Systems, Inc. common stock at the close of business on March 2, 2020 are entitled to notice of and to vote at the 2020 Annual Meeting of Stockholders and any adjournment or postponement thereof. How to Vote: Your vote is important to us. Please cast your vote promptly via the internet, telephone or mail.
    [Show full text]
  • Cadence Design Systems, Inc. Incoming Letter Dated December 21, 2018
    UNITED STATES SECURITIES AND EXCHANGE COMMISSION WASHINGTON, D .C. 20549 DIVISION OF CORPORATION FINANCE February 27, 2019 John P. Kelsh Sidley Austin LLP [email protected] Re: Cadence Design Systems, Inc. Incoming letter dated December 21, 2018 Dear Mr. Kelsh: This letter is in response to your correspondence dated December 21, 2018 and February 12, 2019 concerning the shareholder proposal (the “Proposal”) submitted to Cadence Design Systems, Inc. (the “Company”) by John Chevedden (the “Proponent”) for inclusion in the Company’s proxy materials for its upcoming annual meeting of security holders. We also have received correspondence from the Proponent dated December 27, 2018, January 25, 2019 and February 24, 2019. Copies of all of the correspondence on which this response is based will be made available on our website at http://www.sec.gov/divisions/corpfin/cf-noaction/14a-8.shtml. For your reference, a brief discussion of the Division’s informal procedures regarding shareholder proposals is also available at the same website address. Sincerely, M. Hughes Bates Special Counsel Enclosure cc: John Chevedden *** *** FISMA & OMB Memorandum M-07-16 February 27, 2019 Response of the Office of Chief Counsel Division of Corporation Finance Re: Cadence Design Systems, Inc. Incoming letter dated December 21, 2018 The Proposal requests that the board take each step necessary so that each voting requirement in the Company’s charter and bylaws (that is explicit or implicit due to default to state law) that calls for a greater than simple majority vote be eliminated and replaced by a requirement for a majority of the votes cast for and against applicable proposals, or a simple majority in compliance with applicable laws.
    [Show full text]
  • EDA Software Support
    EDA Software Support ® January 1998, ver. 7 Introduction Seamless design flow and high-quality integration of third party EDA tools are essential to the continued success of programmable logic devices (PLDs). Thus, Altera has established the Altera Commitment to Cooperative Engineering Solutions (ACCESSSM) program. Through the ACCESS program, Altera and key EDA vendors jointly develop and market next-generation high-level design tools and methodologies. Altera provides EDA partners with critical technical information and assistance, and ACCESS partners dedicate resources to ensure the best quality design results for Altera architectures. The ACCESS program provides a total solution that allows designers to generate and verify multiple design revisions in a single day, greatly reducing the product development cycle. Altera has been a leader in support of industry standards, such as EDIF, VHDL, Verilog HDL, VITAL, and the library of parameterized modules (LPM). Altera has also made a commitment to support current ACCESS partner design flows. f For more information on software support provided by Altera, see the MAX+PLUS II Programmable Logic Development System & Software Data Sheet in this data book. This document identifies the type of product(s) available from each ACCESS partner, i.e., design entry, compilation/synthesis, and simulation/verification. These products either support Altera devices directly or provide an interface to the MAX+PLUS II development software. In addition, the MAX+PLUS® II software contains the necessary interfaces and libraries to support many EDA tools. Altera recommends contacting EDA software manufacturers directly for details on product features, specific device support, and product availability. Table 1 lists third-party tool support for Altera devices.
    [Show full text]
  • Legal Notice
    Altera Digital Library September 1996 P-CD-ADL-01 Legal Notice This CD contains documentation and other information related to products and services of Altera Corporation (“Altera”) which is provided as a courtesy to Altera’s customers and potential customers. By copying or using any information contained on this CD, you agree to be bound by the terms and conditions described in this Legal Notice. The documentation, software, and other materials contained on this CD are owned and copyrighted by Altera and its licensors. Copyright © 1994, 1995, 1996 Altera Corporation, 2610 Orchard Parkway, San Jose, California 95134, USA and its licensors. All rights reserved. You are licensed to download and copy documentation and other information from this CD provided you agree to the following terms and conditions: (1) You may use the materials for informational purposes only. (2) You may not alter or modify the materials in any way. (3) You may not use any graphics separate from any accompanying text. (4) You may distribute copies of the documentation available on this CD only to customers and potential customers of Altera products. However, you may not charge them for such use. Any other distribution to third parties is prohibited unless you obtain the prior written consent of Altera. (5) You may not use the materials in any way that may be adverse to Altera’s interests. (6) All copies of materials that you copy from this CD must include a copy of this Legal Notice. Altera, MAX, MAX+PLUS, FLEX, FLEX 10K, FLEX 8000, FLEX 8000A, MAX 9000, MAX 7000,
    [Show full text]
  • Cadence Design Systems, Inc
    Cadence Design Systems, Inc. 2011 Annual Report Cadence is the global technology leader in software, hardware, IP, and services for electronic design automation (EDA) that is leading the transformation of the industry. By delivering crucial design technology for creating, integrating, and optimizing designs, Cadence enables customers to realize silicon chips, systems-on-chip devices, and complete systems at lower costs with higher quality. Lip-Bu Tan President and Chief Executive Offi cer DEAR SHAREHOLDERS: Last year I indicated that Cadence had turned the corner and was poised for success in 2011. I am proud to report that the Cadence team executed well in 2011 and achieved excellent results. Revenue grew 23% to $1.15 billion, operating profi tability signifi cantly improved, and operating cash fl ow increased 21% to $240 million. Growth was driven by expanded adoption of our existing products, introduction of exciting new products, and successful collaboration with industry leaders that demonstrated the increasing power of our strategy and technology. We continue to gain momentum, and I look forward to Cadence achieving even more success in 2012. This is an exciting time to be in the SoC Realization today is based on selecting leading fabless semiconductor companies, electronics industry. Dynamic markets like and integrating components of intellectual foundries, and IP providers. A great those for mobile devices, video, and cloud property (IP). In this area, Cadence offers example was the collaboration between computing are experiencing rapid growth. differentiated, high-performance IP for Cadence and the leading IP company and An explosion in the number of devices that memory, storage, and connectivity – the leading foundry on the fi rst run “apps” such as smart phones and serving the high-growth mobile, video, 20-nanometer test chip for a new tablet computers is driving an application- and network markets, in particular.
    [Show full text]
  • Pax U.S. Sustainable Economy Fund USD 3/31/2021 Port. Ending Market
    Pax U.S. Sustainable Economy Fund USD 6/30/2021 Port. Ending Market Value Portfolio Weight Apple Inc. 15,530,305.28 5.3 Microsoft Corporation 14,041,830.60 4.8 Alphabet Inc. Class A 10,121,219.55 3.4 NVIDIA Corporation 9,590,798.70 3.3 Johnson & Johnson 5,934,923.24 2.0 Thermo Fisher Scientific Inc. 5,795,351.36 2.0 Verizon Communications Inc. 5,558,848.36 1.9 Zoetis, Inc. Class A 5,444,693.76 1.9 Lam Research Corporation 5,088,474.00 1.7 Home Depot, Inc. 4,922,386.04 1.7 Allstate Corporation 4,825,888.68 1.6 Waste Management, Inc. 4,781,954.30 1.6 HCA Healthcare Inc 4,744,683.00 1.6 American Water Works Company, Inc. 4,447,575.28 1.5 MetLife, Inc. 4,297,110.30 1.5 Linde plc 4,189,637.20 1.4 Texas Instruments Incorporated 4,116,566.10 1.4 Mastercard Incorporated Class A 3,986,417.71 1.4 CBRE Group, Inc. Class A 3,818,242.74 1.3 Alphabet Inc. Class C 3,646,695.60 1.2 Unum Group 3,561,502.00 1.2 ViacomCBS Inc. Class B 3,376,078.40 1.2 Intel Corporation 3,364,301.78 1.1 Applied Materials, Inc. 3,234,331.20 1.1 Eli Lilly and Company 3,148,325.84 1.1 HubSpot, Inc. 3,110,559.36 1.1 PepsiCo, Inc. 3,073,638.48 1.0 Procter & Gamble Company 2,941,878.79 1.0 United Parcel Service, Inc.
    [Show full text]
  • Virtuoso System Design Platform Unified “System-Aware” Platform for IC and Package Design
    Virtuoso System Design Platform Unified “system-aware” platform for IC and package design The Cadence® Virtuoso® System Design Platform is a holistic, system-based solution that provides the functionality to drive simulation and LVS-clean layout of ICs and packages from a single schematic. There are two key flows: implementation and analysis. The implementation flow is used to create an IC package schematic in Virtuoso Schematic Editor and then transfer the schematic data to Cadence SiP Layout to layout the physical design. In addition, this flow offers the capability to generate and verify library parts, output a bill of materials (BOM), and perform layout versus schematic (LVS) checking. The analysis flow is used to extract and simulate any portion of the system (IC-package-PCB) regardless of the layout design status. Moreover, this flow offers the capability to automatically generate schematics for the PCB and IC package layouts, bind the instances of the IC package to the IC schematic or models, and build testbenches to simulate the system using the Virtuoso ADE Product Suite plus Spectre® Multi-Mode Simulation interface. Cadence Sigrity™ models extracted from the PCB and IC package layouts get automatically stitched into the generated schematic. Seamless package/board-level layout parasitic back-annotation flow Virtuoso “Chip” View Virtuoso Schematic Sigrity Extracted Representing System-Level Design Cadence SiP Layout Interconnect Model HPJ VSS Single source schematic automates package-level LVS RST RX1 KEY SP TX1 Allegro GaN Constraints
    [Show full text]
  • Cadence Design Systems, Inc
    CADENCE ANNUAL REPORT 2003 FROM BEGINNING TO END, MAKING IT POSSIBLE >> CORPORATE REGIONAL CADENCE DESIGN SYSTEMS, INC. HEADQUARTERS HEADQUARTERS >> CADENCE DESIGN SYSTEMS, INC. ASIA/PACIFIC EUROPE JAPAN 2655 Seely Avenue The Gateway, Tower II Bagshot Road 3-17-6 Shin-Yokohama, San Jose, California 95134 25 Canton Road Bracknell, Berkshire RG12 0PH Kouhoku-ku, Yokohama 408.943.1234 Suites 03–07, 23A United Kingdom Kanagawa 222-0033 www.cadence.com Tsimshatsui, Kowloon Phone: +44.1344.360333 Japan Hong Kong Fax: +44.1344.302837 Phone: +81.45.475.6330 Phone: +852.2377.7111 Fax: +81.45.475.6331 Fax: +852.2377.2802 2003 ANNUAL REPORT AND FORM 10 -K Cadence is the largest supplier of electronic design technologies, methodology services, and design services. Cadence solutions are used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With approximately 4,800 employees and 2003 revenues of approximately $1.1 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, Calif., and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products, and services is available at www.cadence.com. STOCKHOLDER INFORMATION INDEPENDENT PUBLIC ACCOUNTANTS FORM 10-K INVESTOR RELATIONS KPMG LLP Restated Restated A copy of the Company’s Form 10-K, as filed with For further information on our Company, please SELECTED FINANCIAL DATA 2003 2002 2001 500 East Middlefield Road the Securities and Exchange Commission for the contact Cadence Investor Relations in writing at: Mountain View, CA 94043 year ended January 3, 2004, is available without (In thousands except per share amounts) Cadence Design Systems, Inc.
    [Show full text]