FINAL COM’L: -12/15/20 IND: -18/24 Advanced MACH120-12/15/20 Micro High-Density EE CMOS Programmable Logic Devices DISTINCTIVE CHARACTERISTICS 68 Pins 56 Inputs 48 Macrocells 48 Outputs 12 ns tPD Commercial 48 Flip-flops; 4 clock choices 18 ns tPD Industrial 4 “PAL26V12” blocks 77 MHz fCNT Commercial Pin-compatible with MACH220 and MACH221 GENERAL DESCRIPTION The MACH120 is a member of AMD’s high-performance The MACH120 macrocell provides either registered or EE CMOS MACH 1 family. This device has approxi- combinatorial outputs with programmable polarity. If a mately five times the logic macrocell capability of the registered configuration is chosen, the register can be popular PAL22V10 without loss of speed. configured as D-type or T-type to help reduce the number of product terms. The register type decision The MACH120 consists of four PAL blocks intercon- can be made by the designer or by the software. All nected by a programmable switch matrix. The switch macrocells can be connected to an I/O cell. If a buried matrix connects the PAL blocks to each other and to all macrocell is desired, the internal feedback path from the input pins, providing a high degree of connectivity macrocell can be used, which frees up the I/O pin for use between the fully-connected PAL blocks. This allows as an input. designs to be placed and routed efficiently. Publication# 14129 Rev. I Amendment /0 Issue Date: April 1995 AMD BLOCK DIAGRAM I2 – I3, I/O0 – I/O11 I/O12 – I/O23 I6 – I7 12 12 I/O Cells I/O Cells 12 12 4 Macrocells Macrocells OE OE 52 x 54 52 x 54 4 AND Logic Array AND Logic Array and and Logic Allocator Logic Allocator 26 26 Switch Matrix 26 26 52 x 54 52 x 54 AND Logic Array AND Logic Array 4 and and Logic Allocator Logic Allocator OE OE 4 Macrocells Macrocells 12 12 I/O Cells I/O Cells 12 12 I/O36 – I/O47 I/O24 – I/O35 CLK0/I0, CLK1/I1, CLK2/I4, CLK3/I5 14129I-1 2 MACH120-12/15/20 AMD CONNECTION DIAGRAMS Top View PLCC 4 5 0 47 3 2 1 44 43 46 45 42 6 CC I/O I/O I/O V I/O GND I/O I/O I/O GND I/O I/O I/O I/O I/O GND I/O 9 8 7 6 5 4 3 2 1 6867666564636261 I/O7 10 60 I/O41 I/O8 11 59 I/O40 I/O9 12 58 I/O39 I/O10 13 57 I/O38 I/O11 14 56 I/O37 CLK0/I0 15 55 I/O36 CLK1/I1 16 54 I7 I2 17 53 GND VCC 18 52 VCC GND 19 51 I6 I3 20 50 CLK3/I5 I/O12 21 49 CLK2/I4 I/O13 22 48 I/O35 I/O14 23 47 I/O34 I/O15 24 46 I/O33 I/O16 25 45 I/O32 I/O17 26 44 I/O31 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 29 27 25 18 19 20 21 22 28 30 24 26 23 VCC GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 14129I-2 Note: Pin-compatible with MACH220 and MACH221. PIN DESIGNATIONS * These pins (16, 17, 20, 23, 26) must be connected to ground for normal operation. CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output VCC = Supply Voltage MACH120-12/15/20 3 AMD ORDERING INFORMATION Commercial Products AMD programmable logic products for commercial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: MACH120 -12 J C FAMILY TYPE OPTIONAL PROCESSING MACH = Macro Array CMOS High-Speed Blank = Standard Processing OPERATING CONDITIONS DEVICE NUMBER C = Commercial (0°C to +70°C) 120 = 48 Macrocells, 68 Pins SPEED PACKAGE TYPE -12 = 12 ns tPD J = 68-Pin Plastic Leaded Chip Carrier (PL 068) -15 = 15 ns tPD -20 = 20 ns tPD Valid Combinations Valid Combinations The Valid Combinations table lists configurations MACH120-12 planned to be supported in volume for this device. MACH120-15 JC Consult the local AMD sales office to confirm availability MACH120-20 of specific valid combinations and to check on newly released combinations. 4 MACH120-12/15/20 (Com’l) AMD ORDERING INFORMATION Industrial Products AMD programmable logic products for industrial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: MACH120 -18 J I FAMILY TYPE OPTIONAL PROCESSING MACH = Macro Array CMOS High-Speed Blank = Standard Processing OPERATING CONDITIONS DEVICE NUMBER I = Industrial (–40°C to +85°C) 120 = 48 Macrocells, 68 Pins SPEED PACKAGE TYPE -18 = 18 ns tPD J = 68-Pin Plastic Leaded Chip Carrier (PL 068) -24 = 24 ns tPD Valid Combinations Valid Combinations The Valid Combinations table lists configurations MACH120-18 JI planned to be supported in volume for this device. MACH120-24 Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. MACH120-18/24 (Ind) 5 AMD FUNCTIONAL DESCRIPTION Table 1 illustrates which product term clusters are The MACH120 consists of four PAL blocks connected available to each macrocell within a PAL block. Refer to by a switch matrix. There are 48 I/O pins and 4 Figure 1 for cluster and macrocell numbers. dedicated input pins feeding the switch matrix. These Table 1. Logic Allocation signals are distributed to the four PAL blocks for efficient design implementation. There are 4 clock pins that can Available also be used as dedicated inputs. Output Macrocell Clusters M0 C0, C1 The PAL Blocks M1 C0, C1, C2 Each PAL block in the MACH120 (Figure 1) contains a M2 C1, C2, C3 48-product-term logic array, a logic allocator, 12 macro- M3 C2, C3, C4 cells and 12 I/O cells. The switch matrix feeds each PAL block with 26 inputs. This makes the PAL block look M4 C3, C4, C5 effectively like an independent “PAL26V12”. M5 C4, C5, C6 There are four additional output enable product terms in M6 C5, C6, C7 each PAL block. For purposes of output enable, the 12 M7 C6, C7, C8 I/O cells are divided into 2 banks of 6 macrocells. Each M8 C7, C8, C9 bank is allocated two of the output enable product terms. M9 C8, C9, C10 An asynchronous reset product term and an asynchro- M10 C9, C10, C11 nous preset product term are provided for flip-flop M11 C10, C11 initialization. All flip-flops within the PAL block are initialized together. The Macrocell The MACH120 macrocells can be configured as either The Switch Matrix registered or combinatorial, with programmable polar- The MACH120 switch matrix is fed by the inputs and ity. The macrocell provides internal feedback whether feedback signals from the PAL blocks. Each PAL block configured as registered or combinatorial. The flip-flops provides 12 internal feedback signals and 12 I/O can be configured as D-type or T-type, allowing for feedback signals. The switch matrix distributes these product-term optimization. signals back to the PAL blocks in an efficient manner The flip-flops can individually select one of four global that also provides for high performance. The design clock pins, which are also available as logic inputs. The software automatically configures the switch matrix registers are clocked on the LOW-to-HIGH transition of when fitting a design into the device. the clock signal. The flip-flops can also be asyn- chronously initialized with the common asynchronous The Product-Term Array reset and preset product terms. The MACH120 product-term array consists of 48 product terms for logic use, and 6 special-purpose The I/O Cell product terms. Four of the special-purpose product The I/O cell in the MACH120 consists of a three-state terms provide programmable output enable, one pro- output buffer. The three-state buffer can be configured vides asynchronous reset, and one provides asynchro- in one of three ways: always enabled, always disabled, nous preset. Two of the output enable product terms are or controlled by a product term. If product term control is used for the first six I/O cells; the other two control the chosen, one of two product terms may be used to last six macrocells. provide the control. The two product terms that are available are common to six I/O cells. Within each PAL The Logic Allocator block, two product terms are available for selection by The logic allocator in the MACH120 takes the 48 logic the first six three-state outputs; two other product terms product terms and allocates them to the 12 macrocells are available for selection by the last six three-state as needed. Each macrocell can be driven by up to 12 outputs. product terms. The design software automatically These choices make it possible to use the macrocell as configures the logic allocator when fitting the design into an output, an input, a bidirectional pin, or a three-state the device. output for use in driving a bus. 6 MACH120-12/15/20 AMD 0 4 8 12 16 20 24 2832 36 40 43 47 51 Output Enable Output Enable Asynchronous Reset Asynchronous Preset I/O Cell I/O Output Macro M0 Cell I/O Cell I/O Output Macro M1 Cell I/O Cell I/O Output M Macro 2 Cell 0 C0 I/O Cell I/O C1 Output M Macro 3 Cell C2 I/O Cell I/O C3 Output M Macro 4 Cell C4 I/O C Cell I/O Switch 5 Output M Macro Matrix 5 Cell C6 I/O C7 Cell I/O Output M Macro 6 Cell C8 Logic Allocator C I/O 9 Cell I/O Output M7 Macro C10 Cell C 11 I/O 47 Cell I/O Output M8 Macro Cell I/O Cell I/O Output M9 Macro Cell I/O Cell I/O Output M10 Macro Cell I/O Cell I/O Output M11 Macro Cell Output Enable Output Enable 0 4 8 12 16 20 24 2832 36 40 43 47 51 CLK 4 12 12 14129I-3 Figure 1.