Cadence Systemc Design and Verification
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Cadence SystemC Design and Verification NMI FPGA Network Meeting Jan 21, 2015 The High Level Synthesis Opportunity… • Raising Abstraction Improves Design & Verification – Optimizes Power, Area and Timing for Front End & Back End Tools – Moves Verification and Debug up to where it is more efficient – Greatly Improves Design Reuse/Retargeting • HLS is Proven on Wide Variety of Cutting-Edge Designs – Hand-RTL Quality for: Datapath, Control and Mixed Designs – Common for designs over 30M gates and >1GHz • HLS Provides Significant Competitive Advantages – Leading Semiconductor Companies are Changing their Design Methodologies for Productivity and Performance – Reduces Costs and Provides Fastest Path to Verified Silicon 2 © 2015 Cadence Design Systems, Inc.. What is High Level Synthesis (HLS) • High Abstraction SystemC describes What How functionality without micro-arch or High-Level implementation details SystemC Constraints TLM • This SystemC is always golden, and is the primary functional verification target Cadence “Area/Power” − Less code to write/debug/maintain HLS “Performance” • HLS is used to explore various RTL Compiler Or Tech implementations FPGA synthesis Lib − Explore and trade-off area, timing, power, pipelining, clocks, tech nodes, etc. RTL • Outputs functionally equivalent RTL (or Scripts, gates) plus simulation models/wrappers Wrappers − Fits into existing flows 3 © 2015 Cadence Design Systems, Inc.. Cadence HLS targeting FPGA SystemC • Integrated with Xilinx/Altera logic synthesis tools (since 2008) − Supports all end devices Design − Provides accurate timing/area constraints C-to-Silicon Compiler estimates API to Altera/Xilinx logic synth Area/Timing Estimates • Flexible scheduling to meet QoR RTL needs • Utilization vs max clock speed • Supports DSP48 blocks FPGA synthesis • Outputs standard RTL to be synthesized by Quartus/Vivado XST/POF 4 © 2015 Cadence Design Systems, Inc.. How does HLS improve productivity • Untimed SystemC is more abstract than RTL This eliminates: – Breaking down logic into clock cycles – Manual creation of the FSM Functionality – Explicit memory management – Explicit register management Architecture User – And more…. Manages Constraints • HLS automates all low-level RTL requirements Schedule of operations HLS FSM encoding Area reduction Automatically "We don't want our engineers Manages writing Verilog, we want them Timing Clock gating inventing concepts and transferring them into silicon and software Pipeline balance Consistent RTL style using automated processes.” Yoshihito Kondo – GM, Sony Corporation Sharing components in EDA Graffiti, July 2009 5 © 2015 Cadence Design Systems, Inc.. Parallel Design and Verification RTL design With RTL flows, the verification cannot start RTL RTL coding until the design is ready, * flow RTL verification many months after the start of the project time to completion SystemC design * With HLS verification can productivity SystemC verification HLS improvement start at the same time as flow the design RTL verification time to completion time * = time of first test vectors running SystemC model stays golden – HLS ensures its always in sync with RTL Parallel design and verification yields large productivity improvement! 6 © 2015 Cadence Design Systems, Inc.. High-level synthesis is not same as software... • Algorithm may be the same, but the implementation has different needs – Interface specification and verification – Data organization, flow, and storage • Software models do not have enough information for aggressive HW – Software can assume infinite storage with equal (fast) access time, but Hardware must trade off storage size vs. access time • SystemC required if QoR and predictable RTL closure is important – Similar RTL-style block partitioning, but leverages higher abstraction 7 © 2015 Cadence Design Systems, Inc.. SystemC enables System Design . ANSI C provides syntax for Computation − Functions and arithmetic expressions SystemC − Verify the math fast with no timing “system-level” − Great for pure algorithms C++ . C++ adds Object-Orientation ANSI C − Classes, objects, and templates “function - − Great for managing complexity level” . SystemC adds System-Level constructs − Structure: hierarchy, modules and ports − Concurrency: processes − Communication protocols: transaction-level queues, signals, events and waits − Precision: fixed-point & bit accurate data types − Great for hardware design and verification High Level Synthesis 8 © 2015 Cadence Design Systems, Inc.. Cadence synthesizable SystemC IP Pre-verified building blocks accelerate design and verification Category Available IP Blocks Fixed point Data types Complex Floating point Computational math FIFOs Building blocks Line buffers Interface IP Generator CDCs Memories Generic Point-to-point channels communication with put()/get() APIs Simple bus Configurable AXI3 bus interfaces AXI4-Lite, AXI4 Memory IP Generator Can be created by users CellMath Floating-Point IP Custom interfaces Design services available 9 © 2015 Cadence Design Systems, Inc.. High-level verification With SystemC Verify algorithms, interfaces, synchronization IP Blocks Design Blocks AXI 4 Synchronization Configuration Channel Register AXI Slave Interface Decoder and Registers C D C Error Diffusion 32-bit Unpack Filter Zoom pix-24 pix-3 Pack 32-bit Dual Port Line Buffer Line Buffer Adapter 24-bit pixels 24-bit pixels 5x5 2x2 Feedback IMG Accelerator RAM 10 © 2015 Cadence Design Systems, Inc.. High-level synthesis applications DSP IP Graphics processing Video processing Control Image processing Wireless signal processing Security Error correction Automotive Wireless infrastructure Mixed Ethernet Datapath Microcontroller Memory I/F control Printer control Cache controller DVD/CD Controller 11 © 2015 Cadence Design Systems, Inc.. Cadence High-Level Synthesis Interface IP Generator SystemC IDE Synthesizable Behavioral Models IP Datapath Control Flow Automation & Integration Memory IP Generator CadenceCadence Floating Point IP Technology HLS Library HLS RTL Compiler Directives Inside Results Visualization Power Performance Area Optimized RTL Combined strengths of Cynthesizer and CtoS Worlds most proven HLS technology 12 © 2015 Cadence Design Systems, Inc.. Summary: Why use high-level synthesis? SystemC RTL in 10 days FPGA retargeting in vs. manual RTL in 3 months 1-2 days vs. 2-3 weeks (manual) I/F controller IP Motion-detection IP 10x+ productivity increase (mW) 20% better quality of results 5x-10x faster, better verification 13 © 2015 Cadence Design Systems, Inc.. © 2015 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Cynthesizer, Incisive, Encounter, Conformal, and the Cadence logo are trademarks or registered trademarks of Cadence Design Systems, Inc. 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