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CA3140, CA3140A ®

Data Sheet July 11, 2005 FN957.10

4.5MHz, BiMOS Operational with Features MOSFET Input/Bipolar Output • MOSFET Input Stage The CA3140A and CA3140 are operational - Very High (ZIN) -1.5TΩ (Typ) that combine the advantages of high - Very Low Input Current (Il) -10pA (Typ) at ±15V PMOS with high voltage bipolar transistors on a - Wide Common Mode Input Voltage Range (VlCR) - Can be single monolithic chip. Swung 0.5V Below Negative Supply Voltage Rail - Output Swing Complements Input Common Mode The CA3140A and CA3140 BiMOS operational amplifiers Range feature gate protected MOSFET (PMOS) transistors in the input circuit to provide very high input impedance, very low • Directly Replaces Industry Type 741 in Most Applications input current, and high speed performance. The CA3140A • Pb-Free Plus Anneal Available (RoHS Compliant) and CA3140 operate at supply voltage from 4V to 36V (either single or dual supply). These operational amplifiers Applications are internally phase compensated to achieve stable • Ground-Referenced Single Supply Amplifiers in operation in unity follower operation, and additionally, Automobile and Portable Instrumentation have access terminal for a supplementary external if additional frequency roll-off is desired. Terminals are also • Sample and Hold Amplifiers provided for use in applications requiring input offset voltage • Long Duration Timers/ nulling. The use of PMOS field effect transistors in the input (µseconds-Minutes-Hours) stage results in common mode input voltage capability down • Photocurrent Instrumentation to 0.5V below the negative supply terminal, an important attribute for single supply applications. The output stage • Peak Detectors uses bipolar transistors and includes built-in protection • Active Filters against damage from load terminal short circuiting to either supply rail or to ground. • • Interface in 5V TTL Systems and Other Low The CA3140A and CA3140 are intended for operation at supply Supply Voltage Systems up to 36V (±18V). • All Standard Operational Amplifier Applications • Function Generators • Tone Controls • Power Supplies • Portable Instruments • Intrusion Alarm Systems Pinout CA3140 (PDIP, SOIC) TOP VIEW

OFFSET 1 8 NULL STROBE

2 7 INV. INPUT - V+ NON-INV. + 3 6 OUTPUT INPUT OFFSET V- 4 5 NULL

1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Harris Corporation 1998, Copyright Intersil Americas Inc. 2002, 2004, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. CA3140, CA3140A

Ordering Information

PART NUMBER TEMP. PKG. (BRAND) RANGE (°C) PACKAGE DWG. #

CA3140AE -55 to 125 8 Ld PDIP E8.3 CA3140AEZ* -55 to 125 8 Ld PDIP E8.3 (See Note) (Pb-free)

CA3140AM -55 to 125 8 Ld SOIC M8.15 (3140A)

CA3140AM96 -55 to 125 8 Ld SOIC Tape and Reel (3140A) CA3140AMZ -55 to 125 8 Ld SOIC M8.15 (3140A) (See Note) (Pb-free)

CA3140AMZ96 -55 to 125 8 Ld SOIC Tape and Reel (3140A) (See Note) (Pb-free)

CA3140E -55 to 125 8 Ld PDIP E8.3

CA3140EZ* -55 to 125 8 Ld PDIP E8.3 (See Note) (Pb-free)

CA3140M -55 to 125 8 Ld SOIC M8.15 (3140)

CA3140M96 -55 to 125 8 Ld SOIC Tape and Reel (3140)

CA3140MZ -55 to 125 8 Ld SOIC M8.15 (3140) (See Note) (Pb-free) CA3140MZ96 -55 to 125 8 Ld SOIC Tape and Reel (3140) (See Note) (Pb-free)

*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.

NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD- 020.

2 FN957.10 July 11, 2005 CA3140, CA3140A

Absolute Maximum Ratings Thermal Information o o DC Supply Voltage (Between V+ and V- Terminals) ...... 36V Thermal Resistance (Typical, Note 1) θJA ( C/W) θJC ( C/W) Differential Mode Input Voltage ...... 8V PDIP Package*...... 115 N/A DC Input Voltage ...... (V+ +8V) To (V- -0.5V) SOIC Package ...... 165 N/A Input Terminal Current ...... 1mA Maximum Junction Temperature (Plastic Package) ...... 150oC Output Short Circuit Duration∞ (Note 2) ...... Indefinite Maximum Storage Temperature Range...... -65oC to 150oC Maximum Lead Temperature (Soldering 10s) ...... 300oC Operating Conditions (SOIC - Lead Tips Only) Temperature Range ...... -55oC to 125oC *Pb-free PDIPs can be used for through hole wave solder process- ing only. They are not intended for use in Reflow solder processing applications. CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES:

1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details 2. Short circuit may be applied to ground or to either supply.

o Electrical Specifications VSUPPLY = ±15V, TA = 25 C TYPICAL VALUES

PARAMETER SYMBOL TEST CONDITIONS CA3140 CA3140A UNITS

Input Offset Voltage Adjustment Resistor Typical Value of Resistor 4.7 18 kΩ Between Terminals 4 and 5 or 4 and 1 to Adjust Max VIO

Input Resistance RI 1.5 1.5 TΩ

Input CI 44pF

Output Resistance RO 60 60 Ω

Equivalent Wideband Input Voltage eN BW = 140kHz, RS = 1MΩ 48 48 µV (See Figure 27)

Equivalent Input Noise Voltage (See Figure 35) eN RS = 100Ω f = 1kHz 40 40 nV/√Hz f = 10kHz 12 12 nV/√Hz

Short Circuit Current to Opposite Supply IOM+ Source 40 40 mA

IOM-Sink1818mA

Gain-Bandwidth Product, (See Figures 6, 30) fT 4.5 4.5 MHz Slew Rate, (See Figure 31) SR 9 9 V/µs

Sink Current From Terminal 8 To Terminal 4 to 220 220 µA Swing Output Low

Transient Response (See Figure 28) tr RL = 2kΩ Rise Time 0.08 0.08 µs C = 100pF OSL Overshoot 10 10 %

Settling Time at 10VP-P, (See Figure 5) tS RL = 2kΩ To 1mV 4.5 4.5 µs C = 100pF L 1.4 1.4 s Voltage Follower To 10mV µ

o Electrical Specifications For Equipment Design, at VSUPPLY = ±15V, TA = 25 C, Unless Otherwise Specified CA3140 CA3140A

PARAMETER SYMBOL MIN TYP MAX MIN TYP MAX UNITS

Input Offset Voltage |VIO|- 5 15- 2 5mV

Input Offset Current |IIO| - 0.5 30 - 0.5 20 pA

Input Current II - 10 50 - 10 40 pA

3 FN957.10 July 11, 2005 CA3140, CA3140A

o Electrical Specifications For Equipment Design, at VSUPPLY = ±15V, TA = 25 C, Unless Otherwise Specified (Continued) CA3140 CA3140A PARAMETER SYMBOL MIN TYP MAX MIN TYP MAX UNITS

Large Signal Voltage Gain (Note 3) AOL 20 100 - 20 100 - kV/V (See Figures 6, 29) 86 100 - 86 100 - dB

Common Mode Rejection Ratio CMRR - 32 320 - 32 320 µV/V (See Figure 34) 70 90 - 70 90 - dB

Common Mode Input Voltage Range (See Figure 8) VICR -15 -15.5 to +12.5 11 -15 -15.5 to +12.5 12 V Power-Supply Rejection Ratio, PSRR - 100 150 - 100 150 µV/V ∆V /∆V (See Figure 36) IO S 76 80 - 76 80 - dB

Max Output Voltage (Note 4) VOM+ +12 13 - +12 13 - V (See Figures 2, 8) VOM- -14 -14.4 - -14 -14.4 - V Supply Current (See Figure 32) I+ - 4 6 - 4 6 mA

Device Dissipation PD - 120 180 - 120 180 mW o Input Offset Voltage Temperature Drift ∆VIO/∆T- 8 - - 6 -µV/ C NOTES:

3. At VO = 26VP-P, +12V, -14V and RL = 2kΩ. 4. At RL = 2kΩ.

o Electrical Specifications For Design Guidance At V+ = 5V, V- = 0V, TA = 25 C TYPICAL VALUES PARAMETER SYMBOL CA3140 CA3140A UNITS

Input Offset Voltage |VIO|5 2mV

Input Offset Current |IIO|0.10.1pA

Input Current II 22pA

Input Resistance RI 11TΩ

Large Signal Voltage Gain (See Figures 6, 29) AOL 100 100 kV/V 100 100 dB Common Mode Rejection Ratio CMRR 32 32 µV/V 90 90 dB

Common Mode Input Voltage Range (See Figure 8) VICR -0.5 -0.5 V 2.6 2.6 V Rejection Ratio PSRR 100 100 µV/V ∆V /∆V IO S 80 80 dB

Maximum Output Voltage (See Figures 2, 8) VOM+3 3 V

VOM- 0.13 0.13 V

Maximum Output Current: Source IOM+1010mA I Sink OM-1 1mA Slew Rate (See Figure 31) SR 7 7 V/µs

Gain-Bandwidth Product (See Figure 30) fT 3.7 3.7 MHz Supply Current (See Figure 32) I+ 1.6 1.6 mA

Device Dissipation PD 88mW Sink Current from Terminal 8 to Terminal 4 to Swing Output Low 200 200 µA

4 FN957.10 July 11, 2005 CA3140, CA3140A

Block Diagram

2mA 4mA 7 V+ BIAS CIRCUIT CURRENT SOURCES AND REGULATOR

200µA2001.6mAµA 2µA2mA + 3 A ≈ INPUT A ≈ 10 A ≈ 1 6 OUTPUT - 10,000 2 C1

12pF 4 V-

5 1 8 STROBE OFFSET NULL

Schematic Diagram

BIAS CIRCUIT INPUT STAGE SECOND STAGE OUTPUT STAGE DYNAMIC CURRENT SINK

7 V+ D 1 D7 R13 5K Q3 R Q20 Q Q 9 1 2 50Ω

D8 R10 Q4 1K Q6 Q5 R14 R 20K Q19 R11 12 12K Q7 20Ω

Q21 Q17 R1 R 8K Q8 8 1K Q18 6 OUTPUT D 2 D3 D4

D5

INVERTING 2 INPUT - Q9 Q10 + NON-INVERTING 3 INPUT C1 R2 R3 500Ω 500Ω 12pF Q Q 14 Q15 16 Q13 Q11 Q12 D6

R4 R5 R6 R7 500Ω 500Ω 50Ω 30Ω

5 1 8 4 OFFSET NULL STROBE V- NOTE: All resistance values are in ohms.

5 FN957.10 July 11, 2005 CA3140, CA3140A

Application Information When the CA3140 is operating such that output Terminal 6 is sinking current to the V- bus, Q is the current Circuit Description 16 sinking element. Transistor Q16 is mirror connected to D6, R7, As shown in the block diagram, the input terminals may be with current fed by way of Q21, R12, and Q20. Transistor Q20, in operated down to 0.5V below the negative supply rail. Two turn, is biased by current flow through R13, zener D8, and R14. class A amplifier stages provide the voltage gain, and a The dynamic current sink is controlled by voltage level sensing. unique class AB amplifier stage provides the current gain For purposes of explanation, it is assumed that output Terminal necessary to drive low-impedance loads. 6 is quiescently established at the potential midpoint between A circuit provides control of cascoded constant current the V+ and V- supply rails. When output current sinking mode flow circuits in the first and second stages. The CA3140 operation is required, the collector potential of transistor Q13 is includes an on chip phase compensating capacitor that is driven below its quiescent level, thereby causing Q17, Q18 to sufficient for the unity gain voltage follower configuration. decrease the output voltage at Terminal 6. Thus, the gate terminal of PMOS transistor Q is displaced toward the V- bus, Input Stage 21 thereby reducing the channel resistance of Q21. As a The schematic diagram consists of a differential input stage consequence, there is an incremental increase in current flow using PMOS field-effect transistors (Q , Q ) working into a 9 10 through Q20, R12, Q21, D6, R7, and the base of Q16. As a mirror pair of bipolar transistors (Q , Q ) functioning as load 11 12 result, Q16 sinks current from Terminal 6 in direct response to resistors together with resistors R through R . The mirror pair 2 5 the incremental change in output voltage caused by Q18. This transistors also function as a differential-to-single-ended sink current flows regardless of load; any excess current is converter to provide base current drive to the second stage internally supplied by the emitter-follower Q18. Short circuit bipolar transistor (Q ). Offset nulling, when desired, can be 13 protection of the output circuit is provided by Q19, which is effected with a 10kΩ connected across driven into conduction by the high voltage drop developed Terminals 1 and 5 and with its slider arm connected to Terminal across R11 under output short circuit conditions. Under these 4. Cascode-connected bipolar transistors Q , Q are the 2 5 conditions, the collector of Q19 diverts current from Q4 so as to constant current source for the input stage. The base biasing reduce the base current drive from Q17, thereby limiting current circuit for the constant current source is described flow in Q18 to the short circuited load terminal. subsequently. The small diodes D3, D4, D5 provide gate oxide protection against high voltage transients, e.g., static electricity. Bias Circuit Quiescent current in all stages (except the dynamic current Second Stage sink) of the CA3140 is dependent upon bias current flow in R . Most of the voltage gain in the CA3140 is provided by the 1 The function of the bias circuit is to establish and maintain second amplifier stage, consisting of bipolar transistor Q 13 constant current flow through D , Q , Q and D . D is a diode and its cascode connected load resistance provided by 1 6 8 2 1 connected transistor mirror connected in parallel with the base bipolar transistors Q , Q . On-chip phase compensation, 3 4 emitter junctions of Q , Q , and Q . D may be considered as a sufficient for a majority of the applications is provided by C . 1 2 3 1 1 current sampling diode that senses the emitter current of Q Additional Miller-Effect compensation (roll off) can be 6 and automatically adjusts the base current of Q (via Q ) to accomplished, when desired, by simply connecting a small 6 1 maintain a constant current through Q , Q , D . The base capacitor between Terminals 1 and 8. Terminal 8 is also 6 8 2 currents in Q , Q are also determined by constant current flow used to strobe the output stage into quiescence. When 2 3 D . Furthermore, current in diode connected transistor Q terminal 8 is tied to the negative supply rail (Terminal 4) by 1 2 establishes the currents in transistors Q and Q . mechanical or electrical means, the output Terminal 6 14 15 swings low, i.e., approximately to Terminal 4 potential. Typical Applications Output Stage Wide dynamic range of input and output characteristics with The CA3140 Series circuits employ a broad band output stage the most desirable high input impedance characteristics is that can sink loads to the negative supply to complement the achieved in the CA3140 by the use of an unique design based capability of the PMOS input stage when operating near the upon the PMOS Bipolar process. Input common mode voltage negative rail. Quiescent current in the emitter-follower cascade range and output swing capabilities are complementary, circuit (Q17, Q18) is established by transistors (Q14, Q15) allowing operation with the single supply down to 4V. whose base currents are “mirrored” to current flowing through The wide dynamic range of these parameters also means diode D in the bias circuit section. When the CA3140 is 2 that this device is suitable for many single supply operating such that output Terminal 6 is sourcing current, applications, such as, for example, where one input is driven transistor Q functions as an emitter-follower to source current 18 below the potential of Terminal 4 and the phase sense of the from the V+ bus (Terminal 7), via D , R , and R . Under these 7 9 11 output signal must be maintained – a most important conditions, the collector potential of Q is sufficiently high to 13 consideration in applications. permit the necessary flow of base current to emitter follower Q17 which, in turn, drives Q18.

6 FN957.10 July 11, 2005 CA3140, CA3140A

Output Circuit Considerations level shifting circuitry usually associated with the 741 series Excellent interfacing with TTL circuitry is easily achieved with of operational amplifiers. a single 6.2V zener diode connected to Terminal 8 as shown Figure 4 shows some typical configurations. Note that a in Figure 1. This connection assures that the maximum series resistor, RL, is used in both cases to limit the drive output signal swing will not go more positive than the zener available to the driven device. Moreover, it is recommended voltage minus two base-to-emitter voltage drops within the that a series diode and shunt diode be used at the thyristor CA3140. These voltages are independent of the operating input to prevent large negative transient surges that can supply voltage. appear at the gate of thyristors, from damaging the integrated circuit. V+ 5V TO 36V Offset Voltage Nulling 7 LOGIC SUPPLY 8 2 6.2V 5V The input offset voltage can be nulled by connecting a 10kΩ potentiometer between Terminals 1 and 5 and returning its CA3140 6 TYPICAL wiper arm to terminal 4, see Figure 3A. This technique, TTL GATE 3 ≈5V however, gives more adjustment range than required and 4 therefore, a considerable portion of the potentiometer rotation is not fully utilized. Typical values of series resistors (R) that may be placed at either end of the potentiometer, see Figure 3B, to optimize its utilization range are given in FIGURE 1. ZENER CLAMPING DIODE CONNECTED TO TERMINALS 8 AND 4 TO LIMIT CA3140 OUTPUT the Electrical Specifications table. SWING TO TTL LEVELS An alternate system is shown in Figure 3C. This circuit uses only one additional resistor of approximately the value ) 1000 SUPPLY VOLTAGE (V-) = 0V 16 o shown in the table. For , in which the TA = 25 C , Q resistance does not drop to 0Ω at either end of rotation, a 15 value of resistance 10% lower than the values shown in the SUPPLY VOLTAGE (V+) = +5V 100 +15V table should be used. +30V Low Voltage Operation Operation at total supply voltages as low as 4V is possible 10 with the CA3140. A current regulator based upon the PMOS threshold voltage maintains reasonable constant operating

SATURATION VOLTAGE (mV) VOLTAGE SATURATION current and hence consistent performance down to these lower voltages.

OUTPUT STAGE TRANSISTOR (Q OUTPUT STAGE 1 0.01 0.1 1.0 10 The low voltage limitation occurs when the upper extreme of the LOAD (SINKING) CURRENT (mA) input common mode voltage range extends down to the voltage FIGURE 2. VOLTAGE ACROSS OUTPUT TRANSISTORS (Q15 at Terminal 4. This limit is reached at a total supply voltage just AND Q16) vs LOAD CURRENT below 4V. The output voltage range also begins to extend down to the negative supply rail, but is slightly higher than that of the Figure 2 shows output current sinking capabilities of the input. Figure 8 shows these characteristics and shows that with CA3140 at various supply voltages. Output voltage swing to 2V dual supplies, the lower extreme of the input common mode the negative supply rail permits this device to operate both voltage range is below ground potential. power transistors and thyristors directly without the need for

V+ V+ V+ 2 7 2 7 2 7 CA3140 6 CA3140 6 CA3140 6 3 4 3 4 5 3 4 5 1 5 1 R R 1 10kΩ 10kΩ 10kΩ R V- V- V- FIGURE 3A. BASIC FIGURE 3B. IMPROVED RESOLUTION FIGURE 3C. SIMPLER IMPROVED RESOLUTION FIGURE 3. THREE OFFSET VOLTAGE NULLING METHODS

7 FN957.10 July 11, 2005 CA3140, CA3140A

RS V+ +HV 7 LOAD LOAD 2 30V NO LOAD MT2 CA3140 6 120VAC 7 R 2 L 3 CA3140 6 4 MT R 1 3 L 4

FIGURE 4. METHODS OF UTILIZING THE VCE(SAT) SINKING CURRENT CAPABILITY OF THE CA3140 SERIES

FOLLOWER +15V 7 0.1µF 3 SIMULATED 10kΩ LOAD CA3140 6

2 100pF 2kΩ 4 0.1µF LOAD RESISTANCE (RL) = 2kΩ -15V LOAD CAPACITANCE (CL) = 100pF 2kΩ

SUPPLY VOLTAGE: VS = ±15V o TA = 25 C 0.05µF 10 1mV 1mV INVERTING 8 5kΩ 10mV 10mV 6 +15V 4 2 7 0.1µF FOLLOWER 2 SIMULATED 0 5kΩ INVERTING LOAD -2 CA3140 6 200Ω -4 3 100pF 2kΩ INPUT VOLTAGE (V) VOLTAGE INPUT 4 -6 1mV 1mV 0.1µF 4.99kΩ 5.11kΩ -8 10mV 10mV -15V -10 0.1 1.0 10 SETTLING POINT SETTLING TIME (µs) D1 D2 1N914 1N914

FIGURE 5A. WAVEFORM FIGURE 5B. TEST CIRCUITS FIGURE 5. SETTLING TIME vs INPUT VOLTAGE

Bandwidth and Slew Rate The exceptionally fast settling time characteristics are largely For those cases where bandwidth reduction is desired, for due to the high combination of high gain and wide bandwidth example, broadband noise reduction, an external capacitor of the CA3140; as shown in Figure 6. connected between Terminals 1 and 8 can reduce the open Input Circuit Considerations loop -3dB bandwidth. The slew rate will, however, also be As mentioned previously, the amplifier inputs can be driven proportionally reduced by using this additional capacitor. below the Terminal 4 potential, but a series current limiting Thus, a 20% reduction in bandwidth by this technique will resistor is recommended to limit the maximum input terminal also reduce the slew rate by about 20%. current to less than 1mA to prevent damage to the input Figure 5 shows the typical settling time required to reach protection circuitry. 1mV or 10mV of the final value for various levels of large Moreover, some current limiting resistance should be signal inputs for the voltage follower and inverting unity gain provided between the inverting input and the output when amplifiers.

8 FN957.10 July 11, 2005 CA3140, CA3140A the CA3140 is used as a unity gain voltage follower. This input offset voltage) due to the application of large resistance prevents the possibility of extremely large input differential input voltages that are sustained over long signal transients from forcing a signal through the input periods at elevated temperatures. protection network and directly driving the internal constant Both applied voltage and temperature accelerate these current source which could result in positive via the changes. The process is reversible and offset voltage shifts of output terminal. A 3.9kΩ resistor is sufficient. the opposite polarity reverse the offset. Figure 9 shows the The typical input current is on the order of 10pA when the typical offset voltage change as a function of various stress inputs are centered at nominal device dissipation. As the voltages at the maximum rating of 125oC (for metal can); at output supplies load current, device dissipation will increase, lower temperatures (metal can and plastic), for example, at raising the chip temperature and resulting in increased input 85oC, this change in voltage is considerably less. In typical current. Figure 7 shows typical input terminal current versus linear applications, where the differential voltage is small and ambient temperature for the CA3140. symmetrical, these incremental changes are of about the same magnitude as those encountered in an operational It is well known that MOSFET devices can exhibit slight amplifier employing a bipolar transistor input stage. changes in characteristics (for example, small changes in

-75 10K SUPPLY VOLTAGE: VS = ±15V SUPPLY VOLTAGE: VS = ±15V o -90 ) T = 25 C A RL = 2kΩ,

dB -105

( 100 φOL CL = 0pF -120 1K AIN G 80 -135 (DEGREES) E

G -150 OPEN LOOP PHASE LOOP OPEN

LTA 60 100 O

P V RL = 2kΩ, 40 CL = 100pF OO

INPUT CURRENT (pA) 10

PEN L PEN 20 O

0 1 2 3 4 5 6 7 8 1 10 10 10 10 10 10 10 10 -60 -40 -20 0 20 40 60 80 100 120 140 FREQUENCY (Hz) TEMPERATURE (oC)

FIGURE 6. OPEN LOOP VOLTAGE GAIN AND PHASE vs FIGURE 7. INPUT CURRENT vs TEMPERATURE FREQUENCY S

N RL = ∞ O I

S 0 1.5

UR o C o +VICR AT TA = 125 C -V AT T = 125 C -0.5 +V AT T = 125oC 1.0 ICR A o OUT A o +VICR AT TA = 25 C -V AT T = 25 C E EX o ICR A +VOUT AT TA = 25 C G -1.0 +V AT T = -55oC 0.5 o ICR A o -VOUT FOR -VICR AT TA = -55 C +VOUT AT TA = -55 C o o LTA TA = -55 C to 125 C O -1.5 0

-2.0 -0.5 UTPUT V O FROM TERMINAL 4 (V-) TERMINAL 4 FROM FROM TERMINALFROM 7 (V+) -2.5 -1.0

-3.0 -1.5 INPUT AND INPUT AND OUTPUT VOLTAGE EXCURSIONS INPUT AND OUTPUT VOLTAGE 0 5 10 15 20 25 0 5 10 15 20 25 SUPPLY VOLTAGE (V+, V-) SUPPLY VOLTAGE (V+, V-)

FIGURE 8. OUTPUT VOLTAGE SWING CAPABILITY AND COMMON MODE INPUT VOLTAGE RANGE vs SUPPLY VOLTAGE

9 FN957.10 July 11, 2005 CA3140, CA3140A

7 placed across the input to the CA3080A to give a logarithmic o TA = 125 C analog indication of the function generator’s frequency. 6 FOR METAL CAN PACKAGES DIFFERENTIAL DC VOLTAGE Analog frequency readout is readily accomplished by the (ACROSS TERMINALS 2 AND 3) = 2V 5 means described above because the output current of the OUTPUT STAGE TOGGLED CA3080A varies approximately one decade for each 60mV 4 change in the applied voltage, VABC (voltage between Terminals 5 and 4 of the CA3080A of the function generator). 3 Therefore, six decades represent 360mV change in VABC. 2 DIFFERENTIAL DC VOLTAGE Now, only the reference voltage must be established to set

OFFSET VOLTAGE SHIFT (mV) SHIFT VOLTAGE OFFSET (ACROSS TERMINALS 2 AND 3) = 0V 1 the lower limit on the meter. The three remaining transistors OUTPUT VOLTAGE = V+ / 2 from the CA3086 Array used in the sweep generator are 0 used for this reference voltage. In , this reference 0 500 1000 1500 2000 2500 3000 3500 4000 4500 generator arrangement tends to track ambient temperature TIME (HOURS) variations, and thus compensates for the effects of the FIGURE 9. TYPICAL INCREMENTAL OFFSET VOLTAGE normal negative temperature coefficient of the CA3080A SHIFT vs OPERATING LIFE VABC terminal voltage. Super Sweep Function Generator Another output voltage from the reference generator is used A function generator having a wide tuning range is shown in to insure temperature tracking of the lower end of the Figure 10. The 1,000,000/1 adjustment range is Frequency Adjustment Potentiometer. A large series accomplished by a single variable potentiometer or by an resistance simulates a current source, assuring similar auxiliary sweeping signal. The CA3140 functions as a non- temperature coefficients at both ends of the Frequency inverting readout amplifier of the triangular signal developed Adjustment Control. across the integrating capacitor network connected to the output of the CA3080A current source. To calibrate this circuit, set the Frequency Adjustment Potentiometer at its low end. Then adjust the Minimum Buffered triangular output signals are then applied to a Frequency Calibration Control for the lowest frequency. To second CA3080 functioning as a high speed hysteresis establish the upper frequency limit, set the Frequency switch. Output from the switch is returned directly back to the Adjustment Potentiometer to its upper end and then adjust input of the CA3080A current source, thereby, completing the Maximum Frequency Calibration Control for the the loop maximum frequency. Because there is interaction among The triangular output level is determined by the four 1N914 these controls, repetition of the adjustment procedure may level limiting diodes of the second CA3080 and the resistor be necessary. Two adjustments are used for the meter. The divider network connected to Terminal No. 2 (input) of the meter sensitivity control sets the meter scale width of each CA3080. These diodes establish the input trip level to this decade, while the meter position control adjusts the pointer switching stage and, therefore, indirectly determine the on the scale with negligible effect on the sensitivity amplitude of the output triangle. adjustment. Thus, the meter sensitivity adjustment control 1 calibrates the meter so that it deflects /6 of full scale for Compensation for propagation delays around the entire loop each decade change in frequency. is provided by one adjustment on the input of the CA3080. This adjustment, which provides for a constant generator Sine Wave Shaper amplitude output, is most easily made while the generator is The circuit shown in Figure 12 uses a CA3140 as a voltage sweeping. High frequency ramp linearity is adjusted by the follower in combination with diodes from the CA3019 Array single 7pF to 60pF capacitor in the output of the CA3080A. to convert the triangular signal from the function generator to a sine-wave output signal having typically less than 2% THD. It must be emphasized that only the CA3080A is The basic zero crossing slope is established by the 10kΩ characterized for maximum output linearity in the current potentiometer connected between Terminals 2 and 6 of the generator function. CA3140 and the 9.1kΩ resistor and 10kΩ potentiometer Meter Driver and from Terminal 2 to ground. Two break points are established Figure 11 shows the CA3140 connected as a meter driver by diodes D1 through D4. Positive feedback via D5 and D6 and buffer amplifier. Low driving impedance is required of establishes the zero slope at the maximum and minimum the CA3080A current source to assure smooth operation of levels of the sine wave. This technique is necessary because the Frequency Adjustment Control. This low-driving the voltage follower configuration approaches unity gain impedance requirement is easily met by using a CA3140 rather than the zero gain required to shape the sine wave at connected as a voltage follower. Moreover, a meter may be the two extremes.

10 FN957.10 July 11, 2005 CA3140, CA3140A

CENTERING -15V 10kΩ +15V HIGH 7.5kΩ +15V +15V FREQUENCY LEVEL 62kΩ 10kΩ 360Ω 0.1 910kΩ 7 7-60pF 3 + 7 µF 15kΩ 5 EXTERNAL 360Ω CA3080A 6 3 + 7 51 OUTPUT 2 - 7-60 CA3140 6 2 - 4 pF pF 2 - 11kΩ CA3080 6 5 10kΩ 11kΩ + 2MΩ HIGH 4 3 4 2.7kΩ SYMMETRY -15V FREQ. 0.1 EXTERNAL -15V +15V SHAPE -15V µF -15V OUTPUT 2kΩ 13kΩ TO OUTPUT 100kΩ AMPLIFIER FROM BUFFER METER FREQUENCY DRIVER (OPTIONAL) ADJUSTMENT 5.1kΩ TO 39kΩ 120Ω 10kΩ SINE WAVE SHAPER 1N914 -15V +15V OUTPUT AMPLIFIER THIS NETWORK IS USED WHEN THE OPTIONAL BUFFER CIRCUIT IS NOT USED

FIGURE 10A. CIRCUIT

FREQUENCY ADJUSTMENT Top Trace: Output at junction of 2.7Ω and 51Ω resistors; 5V/Div., 500ms/Div. +15V METER DRIVER Center Trace: External output of triangular function generator; POWER AND BUFFER 2V/Div., 500ms/Div. SUPPLY ±15V AMPLIFIER M Bottom Trace: Output of “Log” generator; 10V/Div., 500ms/Div. -15V

FIGURE 10B. FIGURE FUNCTION GENERATOR SWEEPING FUNCTION GENERATOR

WIDEBAND LINE DRIVER SINE WAVE SHAPER 51Ω

GATE DC LEVEL SWEEP FINE SWEEP ADJUST RATE GENERATOR OFF INT. EXTERNAL COARSE V- EXT. INPUT RATE

1V/Div., 1s/Div. SWEEP Three tone test signals, highest frequency ≥0.5MHz. Note the slight LENGTH asymmetry at the three second/cycle signal. This asymmetry is due to V- slightly different positive and negative integration from the CA3080A and from the PC board and component leakages at the 100pA level. FIGURE 10C. FUNCTION GENERATOR WITH FIXED FIGURE 10D. INTERCONNECTIONS FREQUENCIES FIGURE 10. FUNCTION GENERATOR

11 FN957.10 July 11, 2005 CA3140, CA3140A

FREQUENCY 500kΩ CALIBRATION MAXIMUM 620kΩ FREQUENCY 7 ADJUSTMENT 51kΩ +15V -15V 3 TO CA3080A 10kΩ + OF FUNCTION CA3080A 0.1µF CA3140 6 GENERATOR SWEEP IN (FIGURE 10) 7 5.6kΩ 3MΩ - 3 + 2 4.7kΩ 4 7.5kΩ 5.1kΩ 4 5 CA3140 6 TO 2 - SUBSTRATE 2k +15V METER 4 WIDEBAND Ω 0.1 F 620Ω µ SENSITIVITY OF CA3019 OUTPUT 12kΩ 0.1µF AMPLIFIER ADJUSTMENT 1kΩ 7 FREQUENCY 2.4kΩ -15V 10kΩ 200µA CALIBRATION M +15V R3 10kΩ MINIMUM METER EXTERNAL 2.5 100 1MΩ kΩ 11 OUTPUT kΩ D1 D4 9 9.1kΩ 510Ω -15V 510Ω 6 5 8 2 R1 8 10 14 10kΩ 2kΩ 430Ω D3 D6 D2 6 12 9 1 METER R2 7 POSITION 3.6kΩ 13 1kΩ ADJUSTMENT 3 4 3 D5 /5 OF CA3086 CA3019 -15V DIODE ARRAY

FIGURE 11. METER DRIVER AND BUFFER AMPLIFIER FIGURE 12. SINE WAVE SHAPER

750kΩ

“LOG” 100kΩ SAWTOOTH 18MΩ

1N914 100kΩ FINE 1MΩ RATE 22MΩ

1N914 SAWTOOTH 8.2kΩ SYMMETRY +15V SAWTOOTH AND 0.47µF RAMP LOW LEVEL SET (-14.5V) 0.047µF COARSE 50kΩ RATE 4700pF

470pF 75kΩ 51kΩ +15V SAWTOOTH 0.1 µF “LOG” 7 +15V +15V 2 - TRIANGLE 36kΩ 7 CA3140 6 3 - 10kΩ GATE + CA3140 6 PULSE 3 4 100kΩ 30kΩ + OUTPUT 0.1 TO OUTPUT 2 4 µF 50kΩ AMPLIFIER -15V -15V LOG RATE 10kΩ ADJUST EXTERNAL OUTPUT 43kΩ 10kΩ TO FUNCTION GENERATOR “SWEEP IN” SWEEP WIDTH -15V 7 +15V 3 + CA3140 6 2 - 4 51kΩ 6.8kΩ 91kΩ 10kΩ 5 LOGVIO 1 TRIANGLE 25kΩ 5 1 3.9Ω TRANSISTORS SAWTOOTH 4 2 FROM CA3086 -15V ARRAY 100Ω “LOG” 390Ω 3

FIGURE 13. SWEEPING GENERATOR

12 FN957.10 July 11, 2005 CA3140, CA3140A

This circuit can be adjusted most easily with a analyzer, but a good first approximation can be made by comparing the output signal with that of a sine wave VOLTAGE generator. The initial slope is adjusted with the potentiometer REFERENCE ADJUSTMENT VOLTAGE 7 R , followed by an adjustment of R . The final slope is 3 + 1 2 REGULATED established by adjusting R3, thereby adding additional INPUT CA3140 6 OUTPUT 2 - segments that are contributed by these diodes. Because 4 there is some interaction among these controls, repetition of the adjustment procedure may be necessary. Sweeping Generator

Figure 13 shows a sweeping generator. Three CA3140s are FIGURE 15. BASIC SINGLE SUPPLY SHOWING VOLTAGE FOLLOWER CONFIGURATION used in this circuit. One CA3140 is used as an integrator, a second device is used as a hysteresis switch that determines Essentially, the regulators, shown in Figures 16 and 17, are the starting and stopping points of the sweep. A third connected as non inverting power operational amplifiers with a CA3140 is used as a logarithmic shaping network for the log gain of 3.2. An 8V reference input yields a maximum output function. Rates and slopes, as well as sawtooth, triangle, voltage slightly greater than 25V. As a voltage follower, when and logarithmic sweeps are generated by this circuit. the reference input goes to 0V the output will be 0V. Because the offset voltage is also multiplied by the 3.2 gain factor, a Wideband Output Amplifier potentiometer is needed to null the offset voltage. Figure 14 shows a high slew rate, wideband amplifier Series pass transistors with high I levels will also suitable for use as a 50Ω transmission line driver. This CBO prevent the output voltage from reaching zero because there circuit, when used in conjunction with the function generator is a finite voltage drop (V ) across the output of the and sine wave shaper circuits shown in Figures 10 and 12 CESAT CA3140 (see Figure 2). This saturation voltage level may provides 18V output open circuited, or 9V output P-P P-P indeed set the lowest voltage obtainable. when terminated in 50Ω. The slew rate required of this amplifier is 28V/µs (18VP-P x π x 0.5MHz). The high impedance presented by Terminal 8 is +15V advantageous in effecting current limiting. Thus, only a small + 50µF 2.2 SIGNAL signal transistor is required for the current-limit sensing - 25V kΩ 2N3053 LEVEL amplifier. Resistive decoupling is provided for this transistor ADJUSTMENT to minimize damage to it or the CA3140 in the event of 2.5kΩ + 7 2.7Ω OUT 3 1N914 51Ω unusual input or output transients on the supply rail. CA3140 6 200Ω 1N914 2.7Ω 2W 2 - 4 Figures 16 and 17, show circuits in which a D2201 high speed 8 1 - 50µF diode is used for the current sensor. This diode was chosen + 25V 2.2 OUTPUT 2N4037 kΩ for its slightly higher forward voltage drop characteristic, thus DC LEVEL +15V 2.4pF ADJUSTMENT 2pF giving greater sensitivity. It must be emphasized that heat 3kΩ -15V sinking of this diode is essential to minimize variation of the -15V current trip point due to internal heating of the diode. That is, 1.8kΩ NOMINAL BANDWIDTH = 10MHz 200Ω tr = 35ns 1A at 1V forward drop represents one watt which can result in significant regenerative changes in the current trip point as the diode temperature rises. Placing the small signal reference FIGURE 14. WIDEBAND OUTPUT AMPLIFIER amplifier in the proximity of the current sensing diode also Power Supplies helps minimize the variability in the trip level due to the negative temperature coefficient of the diode. In spite of those High input impedance, common mode capability down to the limitations, the current limiting point can easily be adjusted negative supply and high output drive current capability are over the range from 10mA to 1A with a single adjustment key factors in the design of wide range output voltage potentiometer. If the temperature stability of the current supplies that use a single input voltage to provide a limiting system is a serious consideration, the more usual regulated output voltage that can be adjusted from current sampling resistor type of circuitry should be employed. essentially 0V to 24V. A power (in a metal can with heatsink), Unlike many regulator systems using comparators having a is used as the series pass element for the conventional bipolar transistor input stage, a high impedance reference current limiting system, Figure 16, because high power from a single supply can be used in Darlington dissipation will be encountered at low output connection with the CA3140 (see Figure 15). voltage and high currents.

13 FN957.10 July 11, 2005 CA3140, CA3140A

A small heat sink VERSAWATT transistor is used as the regulation also remains constant. Line regulation is 0.1% per series pass element in the fold back current system, Figure volt. Hum and noise voltage is less than 200µV as read with a 17, since dissipation levels will only approach 10W. In this meter having a 10MHz bandwidth. system, the D2201 diode is used for current sampling. Figure 18A shows the turn ON and turn OFF characteristics Foldback is provided by the 3kΩ and 100kΩ divider network of both regulators. The slow turn on rise is due to the slow connected to the base of the current sensing transistor. rate of rise of the reference voltage. Figure 18B shows the Both regulators provide better than 0.02% load regulation. transient response of the regulator with the switching of a Because there is constant at all voltage settings, the 20Ω load at 20V output.

OUTPUT 0V TO 25V 2N6385 CURRENT “FOLDBACK” CURRENT ⇒ 25V AT 1A POWER DARLINGTON LIMITING LIMITER OUTPUT “FOLDS BACK” ADJUST 2N5294 0.1 ⇒ 24V D2201 TO 40mA D2201 AT 1A +30V 2 3 +30V 3 2 1kΩ 200Ω 75Ω 1kΩ 1kΩ 1 1 100kΩ 3kΩ 1kΩ 3kΩ 2 100kΩ 2N2102 2N2102 3 1kΩ 100Ω 1kΩ 8 1 8 7 56pF 180kΩ 56pF 180kΩ 7 2 2 1kΩ 1kΩ 6 CA3140 82kΩ 6 CA3140 82kΩ + 5 + 2.7kΩ 10µF 3 2.7kΩ 10µF 5 3 - 1 - 1 100kΩ 4 100kΩ 4 INPUT INPUT VOLTAGE VOLTAGE + + ADJUST 250 F + ADJUST + 2.2kΩ 5µF 50kΩ µ 2.2kΩ 250µF - - - 5µF 50kΩ - 100kΩ 100kΩ 10 11 1 2 14 10 11 1 2 14 12 12 9 3 0.01µF 9 3 0.01µF 8 7 5 13 8 7 5 13

6 4 CA3086 6 4 CA3086 1kΩ 1kΩ 62kΩ 62kΩ HUM AND NOISE OUTPUT <200µVRMS LOAD REGULATION HUM AND NOISE OUTPUT <200µVRMS LOAD REGULATION (MEASUREMENT BANDWIDTH ~10MHz) (NO LOAD TO FULL LOAD) (MEASUREMENT BANDWIDTH ~10MHz) (NO LOAD TO FULL LOAD) LINE REGULATION 0.1%/V <0.02% LINE REGULATION 0.1%/V <0.02% FIGURE 16. REGULATED POWER SUPPLY FIGURE 17. REGULATED POWER SUPPLY WITH “FOLDBACK” CURRENT LIMITING

Top Trace: Output Voltage; 5V/Div., 1s/Div. 200mV/Div., 5µs/Div. Bottom Trace: Collector of load switching transistor, load = 1A; 5V/Div., 5µs/Div. FIGURE 18A. SUPPLY TURN-ON AND TURNOFF CHARACTERISTICS FIGURE 18B. TRANSIENT RESPONSE FIGURE 18. WAVEFORMS OF DYNAMIC CHARACTERISTICS OF POWER SUPPLY CURRENTS SHOWN IN FIGURES 16 AND 17

14 FN957.10 July 11, 2005 CA3140, CA3140A

Tone Control Circuits Bass treble boost and cut are ±15dB at 100Hz and 10kHz, High slew rate, wide bandwidth, high output voltage respectively. Full peak-to-peak output is available up to at capability and high input impedance are all characteristics least 20kHz due to the high slew rate of the CA3140. The required of tone control amplifiers. Two tone control circuits amplifier gain is 3dB down from its “flat” position at 70kHz. that exploit these characteristics of the CA3140 are shown in Figure 19 shows another with similar Figures 19 and 20. boost and cut specifications. The wideband gain of this The first circuit, shown in Figure 20, is the Baxandall tone circuit is equal to the ultimate boost or cut plus one, which in control circuit which provides unity gain at midband and this case is a gain of eleven. For 20dB boost and cut, the uses standard linear potentiometers. The high input input loading of this circuit is essentially equal to the value of impedance of the CA3140 makes possible the use of low- the resistance from Terminal No. 3 to ground. A detailed cost, low-value, small size , as well as reduced analysis of this circuit is given in “An IC Operational load of the driving stage. Amplifier (OTA) With Power Capability” by L. Kaplan and H. Wittlinger, IEEE Transactions on Broadcast and Television Receivers, Vol. BTR-18, No. 3, August, 1972.

FOR SINGLE SUPPLY +30V NOTES: 2.2M Ω 5. 20dB Flat Position Gain.

7 6. ±15dB Bass and Treble Boost and Cut 0.005µF 0.1µF 3 + at 100Hz and 10kHz, respectively. 5.1 CA3140 6 7. 25VP-P output at 20kHz. MΩ 2 - 8. -3dB at 24kHz from 1kHz reference. 4

FOR DUAL SUPPLIES BOOST TREBLE CUT 200kΩ +15V 0.012µF0.001(LINEAR) µF

0.1 100 7 2.2MΩ 18kΩ 100pF 0.005µF 0.1µF µF pF 3 + CA3140 6 5.1MΩ 2 - 4 0.1µF 0.022µF 0.0022µF 2µF -15V - + 10kΩ 1MΩ 100kΩ TONE CONTROL NETWORK CCW (LOG) BOOST BASS CUT TONE CONTROL NETWORK

FIGURE 19. TONE CONTROL CIRCUIT USING CA3130 SERIES (20dB MIDBAND GAIN)

FOR SINGLE SUPPLY

BOOST BASS CUT (LINEAR) 0.047µF 240kΩ 5MΩ 240kΩ FOR DUAL SUPPLIES 2.2MΩ +32V 750 750 +15V pF pF 7 0.1 µF 7 3 + 0.1µF 3 + 0.1 2.2 CA3140 6 CA3140 6 µF MΩ 0.047µF 2 - TONE CONTROL 2.2MΩ 2 - NETWORK 4 4 0.1µF 20pF ΝΟΤΕΣ: -15V 9. ±15dB Bass and Treble Boost and Cut at 100Hz and 10kHz, Respectively. 51kΩ 5MΩ 51kΩ (LINEAR) 10. 25VP-P Output at 20kHz. BOOST TREBLE CUT 11. -3dB at 70kHz from 1kHz Reference. TONE CONTROL NETWORK 12. 0dB Flat Position Gain. FIGURE 20. BAXANDALL TONE CONTROL CIRCUIT USING CA3140 SERIES

15 FN957.10 July 11, 2005 CA3140, CA3140A

Wien Bridge Oscillator OUTPUT 19VP-P TO 22VP-P Another application of the CA3140 that makes excellent use +15V THD <0.3% of its high input impedance, high slew rate, and high voltage R2 C 1000pF 7 qualities is the Wien Bridge sine wave oscillator. A basic Wien 2 0.1µF 3 + CA3109 8 9 Bridge oscillator is shown in Figure 21. When R1 = R2 = R DIODE CA3140 6 ARRAY and C = C = C, the frequency equation reduces to the SUBSTRATE 1 2 R1 C1 2 - 1000 OF CA3019 1 familiar f = 1/(2πRC) and the gain required for , 4 6 2 pF 0.1µF AOSC is equal to 3. Note that if C2 is increased by a factor of 7 3 four and R2 is reduced by a factor of four, the gain required 0.1µF -15V for oscillation becomes 1.5, thus permitting a potentially 7.5kΩ 5 4 higher operating frequency closer to the gain bandwidth R1 = R2 = R product of the CA3140. 50Hz, R = 3.3MΩ 3.6kΩ C2 R2 100Hz, R = 1.6MΩ NOTES: 1 f = ------1kHz, R = 160MΩ 500Ω 2π R1C1R2C2 10kHz, R = 16MΩ + 30kHz, R = 5.1MΩ OUTPUT C1 R2 - AOSC = 1 ++------FIGURE 22. CIRCUIT USING C2 R1 RF CA3140

C Simple Sample-and-Hold System 1 R1 RF RS ACL = 1 + ------RS Figure 23 shows a very simple sample-and-hold system using the CA3140 as the readout amplifier for the storage capacitor. The CA3080A serves as both input buffer amplifier FIGURE 21. BASIC WIEN BRIDGE OSCILLATOR CIRCUIT and low feed-through transmission switch (see Note 13). USING AN OPERATIONAL AMPLIFIER System offset nulling is accomplished with the CA3140 via its offset nulling terminals. A typical simulated load of 2kΩ Oscillator stabilization takes on many forms. It must be and 30pF is shown in the schematic. precisely set, otherwise the amplitude will either diminish or reach some form of limiting with high levels of distortion. The 30kΩ 0 SAMPLE element, RS, is commonly replaced with some variable STROBE -15 HOLD resistance element. Thus, through some control means, the 1N914 value of RS is adjusted to maintain constant oscillator output. A FET channel resistance, a thermistor, a lamp bulb, or other +15V device whose resistance increases as the output amplitude 1N914 +15V 5 0.1µF 3.5kΩ is increased are a few of the elements often utilized. 2kΩ 7 INPUT 3 + 7 Figure 22 shows another means of stabilizing the oscillator CA3080A 6 3 + 2 - CA3140 6 with a zener diode shunting the feedback resistor (R of 4 F 2 - 4 0.1 Figure 21). As the output signal amplitude increases, the 1 µF 0.1µF 5 zener diode impedance decreases resulting in more 2kΩ -15V 100kΩ feedback with consequent reduction in gain; thus stabilizing 2kΩ -15V the amplitude of the output signal. Furthermore, this 200pF C1 combination of a monolithic zener diode and bridge rectifier 200pF 400Ω 2kΩ circuit tends to provide a zero temperature coefficient for this 0.1µF regulating system. Because this bridge rectifier system has 30pF SIMULATED LOAD no time constant, i.e., thermal time constant for the lamp NOT REQUIRED bulb, and RC time constant for filters often used in detector networks, there is no lower frequency limit. For example, with FIGURE 23. SAMPLE AND HOLD CIRCUIT 1µF polycarbonate capacitors and 22MΩ for the frequency determining network, the operating frequency is 0.007Hz. In this circuit, the storage compensation capacitance (C1) is only 200pF. Larger value capacitors provide longer “hold” As the frequency is increased, the output amplitude must be periods but with slower slew rates. The slew rate is: reduced to prevent the output signal from becoming slew- dv I ------==---- 0.5mA⁄ 200pF =2.5V ⁄ µs rate limited. An output frequency of 180kHz will reach a slew dt C rate of approximately 9V/µs when its amplitude is 16VP-P. NOTE: 13. AN6668 “Applications of the CA3080 and CA 3080A High Performance Operational Transconductance Amplifiers”.

16 FN957.10 July 11, 2005 CA3140, CA3140A

Pulse “droop” during the hold interval is 170pA/200pF which is Current Amplifier 0.85µV/µs; (i.e., 170pA/200pF). In this case, 170pA represents The low input terminal current needed to drive the CA3140 the typical current of the CA3080A when strobed off. If makes it ideal for use in current amplifier applications such C1 were increased to 2000pF, the “hold-droop” rate will as the one shown in Figure 25 (see Note 14). In this circuit, decrease to 0.085µV/µs, but the slew rate would decrease to low current is supplied at the input potential as the power 0.25V/µs. The parallel diode network connected between supply to load resistor RL. This load current is increased by Terminal 3 of the CA3080A and Terminal 6 of the CA3140 the multiplication factor R2/R1, when the load current is prevents large input signal feedthrough across the input monitored by the power supply meter M. Thus, if the load terminals of the CA3080A to the 200pF storage capacitor when current is 100nA, with values shown, the load current the CA3080A is strobed off. Figure 24 shows dynamic presented to the supply will be 100µA; a much easier current characteristic waveforms of this sample-and-hold system. to measure in many systems.

R1

10kΩ +15V

R I x 2 L R 0.1µF 1 7 3 + R2 M CA3140 6 I 2 - 0.1µF 10MΩ L 4 POWER 1 5 SUPPLY RL 100kΩ

Top Trace: Output; 50mV/Div., 200ns/Div. Bottom Trace: Input; 50mV/Div., 200ns/Div. 4.3kΩ -15V

FIGURE 25. BASIC CURRENT AMPLIFIER FOR LOW CURRENT MEASUREMENT SYSTEMS

Note that the input and output voltages are transferred at the same potential and only the output current is multiplied by the scale factor. The dotted components show a method of decoupling the circuit from the effects of high output load capacitance and the potential oscillation in this situation. Essentially, the Top Trace: Output Signal; 5V/Div, 2µs/Div. necessary high frequency feedback is provided by the Center Trace: Difference of Input and Output Signals through capacitor with the dotted series resistor providing load Tektronix Amplifier 7A13; 5mV/Div., 2µs/Div. decoupling. Bottom Trace: Input Signal; 5V/Div., 2µs/Div. LARGE SIGNAL RESPONSE AND SETTLING TIME Full Wave Rectifier Figure 26 shows a single supply, absolute value, ideal full- wave rectifier with associated waveforms. During positive excursions, the input signal is fed through the feedback network directly to the output. Simultaneously, the positive excursion of the input signal also drives the output terminal (No. 6) of the inverting amplifier in a negative going excursion such that the 1N914 diode effectively disconnects the amplifier from the signal path. During a negative going excursion of the input signal, the CA3140 functions as a normal inverting amplifier with a gain equal to -R2/R1. When the equality of the two equations shown in Figure 26 is SAMPLING RESPONSE satisfied, the full wave output is symmetrical.

Top Trace: Output; 100mV/Div., 500ns/Div. NOTE: Bottom Trace: Input; 20V/Div., 500ns/Div. 14. “Operational Amplifiers Design and Applications”, J. G. Graeme, FIGURE 24. SAMPLE AND HOLD SYSTEM DYNAMIC McGraw-Hill Book Company, page 308, “Negative Immittance CHARACTERISTICS WAVEFORMS Converter Circuits”.

17 FN957.10 July 11, 2005 CA3140, CA3140A

R2 +15V

5kΩ +15V 0.1µF 10kΩ 7 SIMULATED 0.1µF R1 INPUT 3 + LOAD 2 - 7 10kΩ CA3140 6 CA3140 6 2 - 1N914 100pF 2kΩ 3 + 4 4 5 10kΩ 1 8 R 3 PEAK 0.1µF ADJUST -15V 100kΩ 10kΩ BW (-3dB) = 4.5MHz OFFSET SR = 9V/µs ADJUST 2kΩ

R2 R3 GAIN ===------X ------0.05µF R1 R1R2 + R3 2 FIGURE 28A. TEST CIRCUIT XX+ R = ------R 3 1X– 1 5kΩ R FOR X== 0.5 ------2- 10k Ω R1 0.75 R ==10kΩ------15kΩ 3 0.5

20VP-P Input BW (-3dB) = 290kHz, DC Output (Avg) = 3.2V

OUTPUT 0 Top Trace: Output; 50mV/Div., 200ns/Div. Bottom Trace: Input; 50mV/Div., 200ns/Div. INPUT FIGURE 28B. SMALL SIGNAL RESPONSE 0

FIGURE 26. SINGLE SUPPLY, ABSOLUTE VALUE, IDEAL FULL WAVE RECTIFIER WITH ASSOCIATED WAVEFORMS

+15V

0.01µF RS 7 3 + NOISE VOLTAGE 1MΩ CA3140 6 OUTPUT 2 - 4 (Measurement made with Tektronix 7A13 .) 30.1kΩ 0.01µF -15V Top Trace: Output Signal; 5V/Div., 5µs/Div. Center Trace: Difference Signal; 5mV/Div., 5µs/Div. BW (-3dB) = 140kHz 1kΩ Bottom Trace: Input Signal; 5V/Div., 5µs/Div. TOTAL NOISE VOLTAGE (REFERRED TO INPUT) = 48µV (TYP) FIGURE 28C. INPUT-OUTPUT DIFFERENCE SIGNAL SHOWING SETTLING TIME FIGURE 27. TEST CIRCUIT AMPLIFIER (30dB GAIN) USED FOR WIDEBAND NOISE MEASUREMENT FIGURE 28. SPLIT SUPPLY VOLTAGE FOLLOWER TEST CIRCUIT AND ASSOCIATED WAVEFORMS

18 FN957.10 July 11, 2005 CA3140, CA3140A

Typical Performance Curves

20 RL = 2kΩ RL = 2kΩ CL = 100pF

o 10 TA = -55 C o 25oC 25 C 125 o 125oC o 125 C TA = -55 C 100

75

50

25 (MHz) PRODUCT BANDWIDTH GAIN

OPEN-LOOP VOLTAGE GAIN (dB) GAIN VOLTAGE OPEN-LOOP 0 1 0 5 10 15 20 25 0 5 10 15 20 25 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V)

FIGURE 29. OPEN-LOOP VOLTAGE GAIN vs SUPPLY FIGURE 30. GAIN BANDWIDTH PRODUCT vs SUPPLY VOLTAGE AND TEMPERATURE VOLTAGE AND TEMPERATURE

R = RL = 2kΩ L ∞ CL = 100pF 7

6 o TA = -55 C o o 25 C 5 25 C 125oC o o 20 TA = -55 C 4 125 C

s) 15 3 µ

10 2

5 1 QUIESCENT SUPPLY CURRENT (mA) QUIESCENT SUPPLY SLEW RATE (V/ SLEW RATE 0 0 0 510152025 0 5 10 15 20 25 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V)

FIGURE 31. SLEW RATE vs SUPPLY VOLTAGE AND FIGURE 32. QUIESCENT SUPPLY CURRENT vs SUPPLY TEMPERATURE VOLTAGE AND TEMPERATURE

120 SUPPLY VOLTAGE: VS = ±15V SUPPLY VOLTAGE: VS = ±15V o o TA = 25 C TA = 25 C 25 100 ) P-P 20 80

15 60

10 40 OUTPUT SWING (V

5 20 COMMON-MODE REJECTION RATIO (dB) RATIO REJECTION COMMON-MODE 0 0 10K 100K 1M 4M 101 102 103 104 105 106 107 FREQUENCY (Hz) FREQUENCY (Hz)

FIGURE 33. MAXIMUM OUTPUT VOLTAGE SWING vs FIGURE 34. COMMON MODE REJECTION RATIO vs FREQUENCY FREQUENCY

19 FN957.10 July 11, 2005 CA3140, CA3140A

Typical Performance Curves (Continued)

1000 SUPPLY VOLTAGE: VS = ±15V SUPPLY VOLTAGE: VS = ±15V o Hz) o TA = 25 C √ TA = 25 C 100

+PSRR 100 80

60

10 40 -PSRR

20 POWER SUPPLY REJECTION RATIO (PSRR) = ∆VIO/∆VS EQUIVALENT INPUT NOISE VOLTAGE (nV/ INPUT NOISE VOLTAGE EQUIVALENT 1 (dB) RATIO REJECTION SUPPLY POWER 0 1101 102 103 104 105 101 102 103 104 105 106 107 FREQUENCY (Hz) FREQUENCY (Hz)

FIGURE 35. EQUIVALENT INPUT NOISE VOLTAGE vs FIGURE 36. POWER SUPPLY REJECTION RATIO vs FREQUENCY FREQUENCY

20 FN957.10 July 11, 2005 CA3140, CA3140A

Metallization Mask Layout

0 10 20 30 40 50 60 65 61 60

50

40

58-66 30 (1.473-1.676)

20

10

0 4-10 (0.102-0.254) 62-70 (1.575-1.778)

Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch).

The photographs and dimensions represent a chip when it is part of the wafer. When the wafer is cut into chips, the cleavage angles are 57o instead of 90ο with respect to the face of the chip. Therefore, the isolated chip is actually 7 mils (0.17mm) larger in both dimensions.

21 FN957.10 July 11, 2005 CA3140, CA3140A

Dual-In-Line Plastic Packages (PDIP)

N E8.3 (JEDEC MS-001-BA ISSUE D) 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX INCHES MILLIMETERS AREA 12 3 N/2 SYMBOL MIN MAX MIN MAX NOTES -B- A - 0.210 - 5.33 4 -A- D E A1 0.015 - 0.39 - 4 BASE A2 0.115 0.195 2.93 4.95 - PLANE A2 A -C- B 0.014 0.022 0.356 0.558 - SEATING PLANE L CL B1 0.045 0.070 1.15 1.77 8, 10 D1 A e C 0.008 0.014 0.204 0.355 - D1 1 A B1 e eC C D 0.355 0.400 9.01 10.16 5 B eB D1 0.005 - 0.13 - 5 0.010 (0.25)M C A BS E 0.300 0.325 7.62 8.25 6 NOTES: E1 0.240 0.280 6.10 7.11 5 1. Controlling Dimensions: INCH. In case of conflict between e 0.100 BSC 2.54 BSC - English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. eA 0.300 BSC 7.62 BSC 6 3. Symbols are defined in the “MO Series Symbol List” in Section eB - 0.430 - 10.92 7 2.2 of Publication No. 95. L 0.115 0.150 2.93 3.81 4 4. Dimensions A, A1 and L are measured with the package seated N8 89 in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protru- Rev. 0 12/93 sions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E andeA are measured with the leads constrained to be per- pendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads uncon- strained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).

22 FN957.10 July 11, 2005 CA3140, CA3140A

Small Outline Plastic Packages (SOIC)

(JEDEC MS-012-AA ISSUE C) N M8.15 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC INDEX AREA H 0.25(0.010)M B M PACKAGE E INCHES MILLIMETERS -B- SYMBOL MIN MAX MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - 123 L A1 0.0040 0.0098 0.10 0.25 -

SEATING PLANE B 0.013 0.020 0.33 0.51 9

-A- C 0.0075 0.0098 0.19 0.25 - D A h x 45o D 0.1890 0.1968 4.80 5.00 3

-C- E 0.1497 0.1574 3.80 4.00 4 µα e 0.050 BSC 1.27 BSC - e A1 C H 0.2284 0.2440 5.80 6.20 - B 0.10(0.004) h 0.0099 0.0196 0.25 0.50 5 0.25(0.010)M C A M BS L 0.016 0.050 0.40 1.27 6 N8 87 NOTES: o o o o 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of α 0 8 0 8 - Publication Number 95. Rev. 0 12/93 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.

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23 FN957.10 July 11, 2005