1.5A, 24V, 17Mhz Power Operational Amplifier Datasheet (Rev. E)

OPA564

www.ti.com SBOS372E –OCTOBER 2008–REVISED JANUARY 2011 1.5A, 24V, 17MHz POWER OPERATIONAL AMPLIFIER Check for Samples: OPA564

1FEATURES

23• HIGH OUTPUT CURRENT: 1.5A DESCRIPTION • WIDE POWER-SUPPLY RANGE: The OPA564 is a low-cost, high-current operational – Single Supply: +7V to +24V amplifier that is ideal for driving up to 1.5A into reactive loads. The high slew rate provides 1.3MHz – Dual Supply: ±3.5V to ±12V full-power bandwidth and excellent linearity. These • LARGE OUTPUT SWING: 20VPP at 1.5A monolithic integrated circuits provide high reliability in • FULLY PROTECTED: demanding powerline communications and motor control applications. – THERMAL SHUTDOWN – ADJUSTABLE CURRENT LIMIT The OPA564 operates from a single supply of 7V to 24V, or dual power supplies of ±3.5V to ±12V. In • DIAGNOSTIC FLAGS: single-supply operation, the input common-mode – OVER-CURRENT range extends to the negative supply. At maximum – THERMAL SHUTDOWN output current, a wide output swing provides a 20VPP (I = 1.5A) capability with a nominal 24V supply. • OUTPUT ENABLE/SHUTDOWN CONTROL OUT • HIGH SPEED: The OPA564 is internally protected against over-temperature conditions and current overloads. It – GAIN-BANDWIDTH PRODUCT: 17MHz is designed to provide an accurate, user-selected – FULL-POWER BANDWIDTH AT 10VPP: current limit. Two flag outputs are provided; one 1.3MHz indicates current limit and the second shows a – SLEW RATE: 40V/ms thermal over-temperature condition. It also has an Enable/Shutdown pin that can be forced low to shut • DIODE FOR JUNCTION TEMPERATURE down the output, effectively disconnecting the load. MONITORING The OPA564 is housed in a thermally-enhanced, • HSOP-20 PowerPAD™ PACKAGE surface-mount PowerPAD™ package (HSOP-20) with (Bottom- and Top-Side Thermal Pad Versions) the choice of the thermal pad on either the top side or the bottom side of the package. Operation for both APPLICATIONS versions is specified over the industrial temperature • POWERLINE COMMUNICATIONS range, –40°C to +85°C. • VALVE, ACTUATOR DRIVER OPA564 RELATED PRODUCTS • VCOM DRIVER • MOTOR DRIVER FEATURES DEVICE Zerø-Drift PGA with 2-Channel Input PGA112 • AUDIO POWER AMPLIFIER Mux and SPI • POWER-SUPPLY OUTPUT AMPLIFIER Zerø-Drift Operational Amplifier, OPA365 • TEST EQUIPMENT AMPLIFIER 50MHz, RRI/O, Single-Supply Quad Operational Amplifier, JFET • TRANSDUCER EXCITATION TL074 • LASER DIODE DRIVER Input , Low Noise Power Operational Amplifier, 1.2A, OPA561 • GENERAL-PURPOSE LINEAR POWER 15V, 17MHz, 50V/ms BOOSTER

1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PowerPAD is a trademark of Texas Instruments, Inc.

3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. © 2008–2011, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. OPA564

SBOS372E –OCTOBER 2008–REVISED JANUARY 2011 www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PACKAGE/ORDERING INFORMATION(1) PACKAGE PRODUCT PACKAGE-LEAD DESIGNATOR PACKAGE MARKING HSOP-20 (PowerPAD on bottom) DWP OPA564 OPA564 HSOP-20 (PowerPAD on top) DWD OPA564

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com.

ABSOLUTE MAXIMUM RATINGS(1) Over operating free-air temperature range (unless otherwise noted). OPA564 UNIT

Supply Voltage, VS = (V+) – (V–) +26 V Voltage(2) (V–)–0.4 to (V+)+0.4 V Signal Input Current Through ESD Diodes(2) ±10 mA Terminals Maximum Differential Voltage Across Inputs(3) 0.5 V Signal Output Voltage (V–)–0.4 to (V+)+0.4 V Terminals Current(4) ±10 mA Output Short-Circuit(5) Continuous

Operating Junction Temperature, TJ –40 to +125 °C

Storage Temperature, TA –55 to +150 °C

Junction Temperature, TJ +150 °C Human Body Model (HBM) 4000 V ESD Ratings Charged Device Model (CDM) 1000 V Machine Model (MM) 200 V

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. (2) Input terminals are diode-clamped to the power-supply rails. Signals that can swing more than 0.4V beyond the supply rails should be current limited to 10mA or less. (3) Refer to Figure 43 for information on input protection. See Input Protection section. (4) Output terminals are diode-clamped to the power-supply rails. Input signals forcing the output terminal more than 0.4V beyond the supply rails should be current limited to 10mA or less. (5) Short-circuit to ground within SOA. See Power Dissipation and Safe Operating Area for more information.

www.ti.com SBOS372E –OCTOBER 2008–REVISED JANUARY 2011 ELECTRICAL CHARACTERISTICS

Boldface limits apply over the specified temperature range: TA = –40°C to +85°C. At TCASE = +25°C, VS = ±12V, RLOAD = 20kΩ to GND, RSET = 7.5kΩ, and E/S pin enabled, unless otherwise noted. OPA564 PARAMETERS CONDITIONS MIN TYP MAX UNIT OFFSET VOLTAGE

Input Offset Voltage VOS VCM = 0V ±2 ±20 mV

vs Temperature dVOS/dT ±10 mV/°C

vs Power Supply PSRR VCM = 0V, VS = ±3.5V to ±13V 10 150 mV/V INPUT BIAS CURRENT (1) Input Bias Current IB VCM = 0V 10 100 pA vs Temperature See Figure 10, Typical Characteristics (1) Input Offset Current IOS 10 100 pA NOISE

Input Voltage Noise Density en f = 1kHz 102.8 nV/√Hz f = 10kHz 20 nV/√Hz f = 100kHz 8 nV/√Hz

Input Current Noise In f = 1kHz 4 fA/√Hz INPUT VOLTAGE RANGE

Common-Mode Voltage Range: VCM Linear Operation (V–) (V+)–3 V

Common-Mode Rejection Ratio CMRR VCM = (V–) to (V+)–3V 70 80 dB vs Temperature See Figure 9, Typical Characteristics INPUT IMPEDANCE Differential 1012 || 16 Ω || pF Common-Mode 1012 || 9 Ω || pF OPEN-LOOP GAIN

Open-Loop Voltage Gain AOL VOUT = 20VPP, RLOAD = 1kΩ 80 108 dB

VOUT = 20VPP, RLOAD = 10Ω 93 dB FREQUENCY RESPONSE (1) Gain-Bandwidth Product GBW RLOAD = 5Ω 17 MHz Slew Rate SR G = 1, 10V Step 40 V/ms

Full Power Bandwidth G = +2, VOUT = 10VPP 1.3 MHz

Settling Time ±0.1% G = +1, 10V Step, CLOAD = 100pF 0.6 ms

±0.01% G = +1, 10V Step, CLOAD = 100pF 0.8 ms

Total Harmonic Distortion + Noise THD+N f = 1kHz, RLOAD = 5Ω, G = +1, VOUT = 5VP 0.003 % OUTPUT

Voltage Output: VOUT

Positive IOUT = 0.5A (V+)–1 (V+)–0.4 V

Negative IOUT = –0.5A (V–)+1 (V–)+0.3 V

Positive IOUT = 1.5A (V+)–2 (V+)–1.5 V

Negative IOUT = –1.5A (V–)+2 (V–)+1.1 V (1) See Typical Characteristics.

SBOS372E –OCTOBER 2008–REVISED JANUARY 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued)

Output Impedance, closed loop RO f = 100kHz 10 Ω

Output Impedance, open loop ZO G = +2, f = 100kHz See Figure 24, Typical Characteristics Output Current Limit Range(3) ±0.4 to ±2.0 A

1.2V I@ 20000 x Current Limit Equation ILIM LIM A 5000 + RSET (4) (5)

Solved for RSET (Current Limit) RSET ≅ (24k/ILIM) – 5kΩ Ω

Current Limit Accuracy ILIM = 1.5A 10 % (6) (7) Current Limit Overshoot VIN = 5V Pulse (200ns tr), G = +2 50 % Output Shut Down Output Impedance(8) 6 || 120 GΩ || pF

Capacitive Load Drive CLOAD See Figure 6, Typical Characteristics DIGITAL CONTROL

Enable/Shutdown Mode INPUT VDIG = +3.3V to +5.5V referenced to V–

VE/S High (output enabled) E/S Pin Open or Forced High (V–)+2 (V–)+VDIG V

VE/S Low (output shut down) E/S Pin Forced Low (V–) (V–)+0.8 V

IE/S High (output enabled) E/S Pin Indicates High 10 mA

IE/S Low (output shut down) E/S Pin Indicates Low 1 mA Output Shutdown Time 1 ms Output Enable Time 3 ms Current Limit Flag Output Normal Operation Sinking 10mA 0 (V–)+0.8 V

Current-Limited Sourcing 20mA (V–)+2 VDIG V Thermal Shutdown Normal Operation Sinking 200mA 0 (V–)+0.8 V (9) Thermally Shutdown Sourcing 200mA (V–)+2 VDIG V +140 to Junction Temperature at Shutdown(10) °C +157 Hysteresis(10) 15 to 19 °C

TSENSE Diode Ideality Factor h 1.033

(2) Under safe operating conditions. See Power Dissipation and Safe Operating Area for safe operating area (SOA) information. (3) Minimum current limit is 0.4A. See Adjustable Current Limit in the Applications section. (4) Quiescent current increases when the current limit is increased (see Typical Characteristics). (5) RSET (current limit) can range from 55kΩ (IOUT = 400mA) to 10kΩ (IOUT = 1.6A typ). See Adjustable Current Limit in the Applications section. (6) See Typical Characteristics. (7) Transient load transition time must be ≥ 200ns. (8) See Enable/Shutdown (E/S) Pin in the Applications section. (9) When sourcing, the VDIG supply must be able to supply the current. (10) Characterized, but not production tested.

www.ti.com SBOS372E –OCTOBER 2008–REVISED JANUARY 2011 ELECTRICAL CHARACTERISTICS (continued)

Specified Voltage Range VS ±12 V Operating Voltage Range 7 24 V (12) Quiescent Current IQ IOUT = 0 39 50 mA Over Temperature 50 mA

Quiescent Current in Shutdown Mode IQSD 5 mA

Specified Voltage for Digital VDIG (V–) + 3.0 (V–) + 5.5 V

Digital Quiescent Current IDIG VDIG = 5V 43 100 mA TEMPERATURE RANGE Specified Range –40 +85 °C Operating Range –40 +125(13) °C Thermal Resistance

HSOP-20 DWP PowerPAD (Pad Down) qJA High K Board 33 °C/W

qJC 50 °C/W

qJP 1.83 °C/W

qJB 22 °C/W (14) HSOP-20 DWD PowerPAD (Pad Up) qJA High K Board 45.5 °C/W

qJC 6.3 °C/W

qJB 22 °C/W (11) Power-supply sequencing requirements must be observed. See Power Supplies section for more information. (12) Quiescent current increases when the current limit is increased (see Typical Characteristics). (13) The OPA564 typically goes into thermal shutdown at a junction temperature above +140°C. (14) Thermal modeling of the DWD-20 package was done based on a 1-inch AAVID Thermalloy heatsink (Thermalloy part no. 65810).

SBOS372E –OCTOBER 2008–REVISED JANUARY 2011 www.ti.com PIN CONFIGURATIONS

OPA564AIDWP OPA564AIDWD HSOP-20 HSOP-20 PowerPAD on Bottom PowerPAD on Top

V- 1 20 V- V- 1 20 V-

V+ 2 19 V+PWR V+PWR 2 19 V+

TFLAG 3 18 V+PWR V+PWR 3 18 TFLAG

E/S 4 17 V+PWR V+PWR 4 17 E/S PowerPAD(1) (2) +IN 5 16 V V 5 PowerPAD 16 +IN HeatSink OUT OUT HeatSink - (Locatedon (Locatedon - IN 6 15 VOUT V 6 15 IN bottomside) OUT topside) - - VDIG 7 14 V PWR V PWR 7 14 VDIG - - IFLAG 8 13 V PWR V PWR 8 13 IFLAG

ISET 9 12 TSENSE TSENSE 9 12 ISET

V- 10 11 V- V- 10 11 V-

(1)PowerPADisinternallyconnectedtoV- , (2)PowerPADisinternallyconnectedtoV- . Soldering the PowerPAD to the PCB is always required, even with applications that havelowpowerdissipation.

PIN DESCRIPTIONS

OPA564AIDWP OPA564AIDWD (PAD DOWN) (PAD UP) PIN NO. PIN NO. NAME DESCRIPTION 1, 10, 11, 20 1, 10, 11, 20 V– –Supply for Amplifier, PWR Out, and Metal PowerPAD 2 19 V+ +Supply for Signal Amplifier Thermal Over Temperature Flag; flag is high when alarmed and device has 3 18 T FLAG gone into thermal shutdown. 4 17 E/S Enable/Shutdown Output Stage; take E/S low to shut down output 5 16 +IN Noninverting Op Amp Input 6 15 –IN Inverting Op Amp Input +Supply for Digital Flag and E/S (referenced to V–). 7 14 VDIG Valid Range is (V–) + 3.0V ≤ VDIG ≤ (V–) + 5.5V.

8 13 IFLAG Current Limit Flag; Active High

9 12 ISET Current Limit Set (see Applications Section)

12 9 TSENSE Temperature Sense Pin for use with TMP411 13, 14 7, 8 V– PWR –Supply for Power Output Stage

15, 16 5, 6 VOUT Output Voltage; RO is high impedance when shut down 17, 18, 19 3, 4, 2 V+ PWR +Supply for Power Output Stage

www.ti.com SBOS372E –OCTOBER 2008–REVISED JANUARY 2011 FUNCTIONAL PIN DIAGRAM

Current Current Thermal Limit Thermal Limit V+ VDIG Flag Flag Enable/Shutdown V+ VDIG Flag Flag Enable/Shutdown (2) (19) (19) (2) (17, 18) (3, 4)

(7) (14) (6) (15) -IN (3) -IN (18) (8) (13) (4) (17) (15, 16) (5, 6) OPA564AIDWP OPA564AIDWD VOUT VOUT

(12) (9) (9) (12) (5) (16) +IN +IN T T Current SENSE Current SENSE Limit Limit (1, 10, 11, 20) Set (1, 10, 11, 20) Set (13, 14) (7, 8)

RSET RSET V- V-

SBOS372E –OCTOBER 2008–REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS

At TCASE = +25°C, VS = ±12V, RLOAD = 20kΩ to GND, RSET = 7.5kΩ, and E/S pin enabled, unless otherwise noted. QUIESCENT CURRENT vs SUPPLY VOLTAGE OUTPUT VOLTAGE SWING vs OUTPUT CURRENT 50 14 R = 7.5kW 12 SET 48 ± 10 VS = 12V 46 8 44 6 4 42 W RSET = 7.5k 2 ± 40 0 VS = 3.5V -2 38 R = 40kW SET -4 +125° C

36 (V) Output Voltage -6 +25° C

Quiescent Current (mA) W -8 - ° 34 RSET = 100k 40 C - ± 10 VS = 12V 32 - 12 1ms Current Pulses 30 -14 68 10 12 14 16 18 20 22 24 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 Supply Voltage (V) Output Current (A) Figure 1. Figure 2.

LARGE−SIGNAL STEP RESPONSE, NO LOAD LARGE−SIGNAL STEP RESPONSE

Unloaded 5W Load G=+1 G=+1

VIN =9V PP VIN =9V PP

2V/div 2V/div

Input Input Output Output

Time(250ns/div) Time(250ns/div) Figure 3. Figure 4.

SMALL−SIGNAL STEP RESPONSE SMALL−SIGNAL OVERSHOOT vs LOAD CAPACITANCE 60 ± VS = 12V G=+1 50

G=- 1 40 VOUT 30 G=- 10

10mV/div VIN Overshoot(%) 20 G=+10

RLOAD = NoLoad G=- 1 10

CLOAD =0pF 0 Time(250ns/div) 10 100 1k 10k 100k Capacitance(pF) Figure 5. Figure 6.

www.ti.com SBOS372E –OCTOBER 2008–REVISED JANUARY 2011 TYPICAL CHARACTERISTICS (continued)

At TCASE = +25°C, VS = ±12V, RLOAD = 20kΩ to GND, RSET = 7.5kΩ, and E/S pin enabled, unless otherwise noted.

IQ vs TEMPERATURE OFFSET VOLTAGE vs TEMPERATURE 50 20 W RSET = 7.5k 15 45 10 40 5

35 0

-5 30

OffsetVoltage(mV) -10

Quiescent Current (mA) 25 -15

20 -20 -75 -50 -25 0 25 50 75 100 125 -75 -50 -25 0 25 50 75 100 125 Temperature (° C) Temperature(° C) Figure 7. Figure 8.

AOL, PSRR, AND CMRR vs TEMPERATURE IB vs TEMPERATURE 2200 300 2000 250

m 1800 200 1600 150 1400 100 CMRR PSRR 1200 50 1000 0 800 -50 IOS AOL 600 IB- -100 400

InputBiasCurrent(pA) -150 200 -200 0 IB+ -250 -200 RejectionRatio,Open-LoopGain(- V/V) 300 -75 -50 -25 0 25 50 75 100 125 Common-ModeRejectionRatio,Power-Supply -75 -50 -25 0 25 50 75 100 125 Temperature(° C) Temperature(° C) Figure 9. Figure 10.

IQ, SHUTDOWN vs TEMPERATURE IDIG vs TEMPERATURE 2.0 100

80 1.5

m 60 1.0 40

0.5 DigitalCurrent( A) 20

QuiescentCurrent,Shutdown(mA) 0 0 -75 -50 -25 0 25 50 75 100 125 -75 -50 -25 0 25 50 75 100 125 Temperature(° C) Temperature(° C) Figure 11. Figure 12.

SBOS372E –OCTOBER 2008–REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued)

At TCASE = +25°C, VS = ±12V, RLOAD = 20kΩ to GND, RSET = 7.5kΩ, and E/S pin enabled, unless otherwise noted. COMMON-MODE REJECTION RATIO AND GAIN AND PHASE vs FREQUENCY POWER-SUPPLY REJECTION RATIO vs FREQUENCY 120 0 100 ± VS = 12V W 100 RLOAD =1k 80 -45 CMRR 80 Phase ) Phase( 60 -PSRR 60 -90

° +PSRR

Gain(dB) Gain 40 40 -135 CMRR,PSRR(dB) 20 20 ± VS = 12V 0 -180 0 10 100 1k 10k 100k 1M 10M 40M 10 100 1k10k 100k Frequency(Hz) Frequency(Hz) Figure 13. Figure 14.

OUTPUT VOLTAGE SWING vs FREQUENCY OUTPUT VOLTAGE SWING vs FREQUENCY 15.0 25

12.5 20

PP PP W 10.0 100 15 7.5 W 10 10 10W 5.0

OutputVoltage(V ) 100W OutputVoltage(V ) 5 2.5 ± ± VS = 12V VS = 12V G=+1 G=+1 0 0 10k 100k 1M 10M 100M 10k 100k 1M 10M 100M Frequency(Hz) Frequency(Hz) Figure 15. Figure 16.

TOTAL HARMONIC DISTORTION + NOISE vs AMPLITUDE TOTAL HARMONIC DISTORTION + NOISE vs AMPLITUDE 1 1

0.1 0.1 W RLOAD =5 W RLOAD =5 0.01 0.01 W R = RLOAD =10 LOAD 10W 0.001 0.001 V =± 12V W R = V =± 12V S RLOAD =60 LOAD S f=1kHz NoLoad f=1kHz W RLOAD = RLOAD =60 TotalHarmonicDistortion+Noise(%) G=+1 TotalHarmonicDistortion+Noise(%) G=- 10 NoLoad 0.0001 0.0001 0.01 0.1 1 10 100 0.01 0.1 1 10 100

VOUT Amplitude(V P ) VOUT Amplitude(V P ) Figure 17. Figure 18.

www.ti.com SBOS372E –OCTOBER 2008–REVISED JANUARY 2011 TYPICAL CHARACTERISTICS (continued)

At TCASE = +25°C, VS = ±12V, RLOAD = 20kΩ to GND, RSET = 7.5kΩ, and E/S pin enabled, unless otherwise noted. TOTAL HARMONIC DISTORTION + NOISE vs AMPLITUDE TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 1 1 R = G=+10 LOAD V =8V 10W OUT P W RLOAD = 5 0.1 0.1 W RLOAD =5

R = 10W 0.01 0.01 LOAD

W RLOAD = 60 0.001 0.001 ± VS = 12V W RLOAD =60 R = f=1kHz LOAD NoLoad R = NoLoad

TotalHarmonicDistortion+Noise(%) G=+10 TotalHarmonicDistortion+Noise(%) LOAD 0.0001 0.0001 0.01 0.1 1 10 100 10 100 1k 10k 100k

VOUT Amplitude(V P ) Frequency(Hz) Figure 19. Figure 20.

TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 1 1 G=- 10 G=+1

VOUT =8V P VOUT =5V P

0.1 0.1 W RLOAD = 5 W RLOAD = 5 0.01 0.01 W R = RLOAD = 10 LOAD W W RLOAD = 60 60 W 0.001 RLOAD = 10 RLOAD = 0.001 NoLoad RLOAD = NoLoad

TotalHarmonicDistortion+Noise(%) TotalHarmonicDistortion+Noise(%) 0.0001 0.0001 10 100 1k 10k 100k 10 100 1k 10k 100k Frequency(Hz) Frequency(Hz) Figure 21. Figure 22.

INPUT VOLTAGE SPECTRAL NOISE AND CURRENT NOISE vs FREQUENCY OPEN-LOOP OUTPUT IMPEDANCE (No Load) 1k 1k 10k ± VS = 12V IOUT =0Adc

CurrentNoise ) CurrentNoise(fA/ 1k Hz VoltageNoise Ö 100 100

100 Ö

Impedance( ) 10 10 Hz 10

VoltageNoise(nV/ )

1 1 1 10 100 1k 10k 100k 1 10 100 1k 10k 100k 1M 10M 100M Frequency(Hz) Frequency(Hz) Figure 23. Figure 24.

SBOS372E –OCTOBER 2008–REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued)

At TCASE = +25°C, VS = ±12V, RLOAD = 20kΩ to GND, RSET = 7.5kΩ, and E/S pin enabled, unless otherwise noted. INPUT BIAS CURRENT vs CLOSED-LOOP OUTPUT IMPEDANCE (No Load) COMMON-MODE VOLTAGE 10k 50 IOUT =0Adc Gain=1V/V 1k 40

100 30

10 20

Impedance( ) 1 10

InputBiasCurrent(pA) 0.1 0

0.01 -10 10 100 1k 10k 100k 1M 10M 100M -12 -10 -8 -6 -4 -2 0 2 4 6 8 10

Frequency(Hz) Common-ModeVoltage(VCM ) Figure 25. Figure 26.

ENABLE RESPONSE RLOAD = 100Ω SHUTDOWN TIME (INVERTING CONFIGURATION)

W VOUT RF =10k 0V W RLOAD =100 CH1: - VOUT = 6V 0V RLOAD =100W ,G=+1 VIN =1V VOUT

2V/div

1V/div

E/S E/S

- CH2: V 0V Time(500m s/div) Time(100ns/div) Figure 27. Figure 28.

ENABLE TIME (INVERTING CONFIGURATION) CURRENT LIMIT PERCENT ERROR vs RSET 60 Mean 0V 50 Mean +3s V OUT 40 Mean- 3 s 30 20 10

2V/div 0 -10 RF =10kW Current Limit Error (%) -20 E/S RLOAD =100W V- VOUT =- 6V -30 -40 Time(1m s/div) 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k W R()SET Figure 29. Figure 30.

www.ti.com SBOS372E –OCTOBER 2008–REVISED JANUARY 2011 TYPICAL CHARACTERISTICS (continued)

At TCASE = +25°C, VS = ±12V, RLOAD = 20kΩ to GND, RSET = 7.5kΩ, and E/S pin enabled, unless otherwise noted.

OUTPUT CURRENT LIMIT vs RSET OUTPUT CURRENT LIMIT vs RSET (SOURCING CURRENT) (SINKING CURRENT) 1.8 1.8

1.6 1.6

1.4 1.4

1.2 1.2

1.0 1.0

0.8 0.8

0.6 0.6 Mean Mean Output Current Limit (A) 0.4 Mean- 3 s Output Current Limit (A) 0.4 Mean- 3 s s s 0.2 Mean +3 0.2 Mean +3 Calculated Value Calculated Value 0 0 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k W W R()SET R()SET Figure 31. Figure 32.

QUIESCENT CURRENT INCREASE vs RSET OFFSET VOLTAGE PRODUCTION DISTRIBUTION 5

2 Population

I Increase (mA)

5k 15k 25k35k 45k 55k 65k 75k 0

7.2 7.2

1.8 1.8

9.0 9.0

5.4 5.4

3.6 3.6

16.2 16.2

10.8 10.8

18.0 18.0

14.4 14.4

12.6 12.6

- W - R()SET OffsetVoltage(mV) Figure 33. Figure 34.

SBOS372E –OCTOBER 2008–REVISED JANUARY 2011 www.ti.com APPLICATION INFORMATION

Sequencing of power supplies must assure that the BASIC CONFIGURATION digital supply voltage (VDIG) be applied before the Figure 35 shows the OPA564 connected as a basic supply voltage to prevent damage to the OPA564. noninverting amplifier. However, the OPA564 can be Figure 36 shows acceptable versus unacceptable used in virtually any op amp configuration. power-supply sequencing. Power-supply terminals should be bypassed with low series impedance capacitors. The technique of using VSUPPLY ceramic and tantalum capacitors in parallel is recommended. Power-supply wiring should have low series impedance.

SeeNote1

Voltage(V) V V+ DIGITAL 47m F

(3) VDIG 0.1m F Time(s)

(1) (A) Sequencenotallowed

OPA564 VO

VIN ISET VSUPPLY (1) RSET

(2) E/S 0.1m F

47m F Voltage(V) VDIGITAL

V-

Time(s) (1) RSET sets the current limit value from 0.4A to 1.5A. (B) Sequenceallowed (2) E/S pin forced low shuts down the output.

(3) VDIG must not exceed (V–) + 5.5V; see Figure 56 for examples of generating a signal for VDIG. Figure 35. Basic Noninverting Amplifier VSUPPLY

POWER SUPPLIES The OPA564 operates with excellent performance

from single (+7V to +24V) or dual (±3.5V to ±12V) Voltage(V) V analog supplies and a digital supply of +3.3V to DIGITAL +5.5V (referenced to the V– pin). Note that the analog power-supply voltages do not need to be symmetrical, as long as the total voltage remains below 24V. For example, the positive supply could be Time(s) set to 14V with the negative supply at –10V. Most (C) Sequenceallowed behaviors remain constant across the operating voltage range. Parameters that vary significantly with (1) The power-supply sequence illustrated in (A) is not allowed. operating voltage are shown in the Typical This power-supply sequence causes damage to the device. Characteristics. Figure 36. Power-Supply Sequencing

www.ti.com SBOS372E –OCTOBER 2008–REVISED JANUARY 2011 ADJUSTABLE CURRENT LIMIT Setting the Current Limit

The OPA564 provides over-current protection to the Leaving the ISET pin unconnected damages the load through its accurate, user-adjustable current limit device. Connecting ISET directly to V– is not (ISET pin). The current limit value, ILIM, can be set from recommended because it programs the current limit 0.4A to 1.5A by controlling the current through the far beyond the 1.5A capability of the device and ISET pin. Setting the current limit does not require causes excess power dissipation. The minimum special power resistors. The output current does not recommended value for RSET is 7.5kΩ, which flow through the ISET pin. programs the maximum current limit to approximately 1.9A. The maximum value for RSET is 55kΩ, which A simple resistor to the negative rail is sufficient for a programs the minimum current limit to approximately general, coarse limit of the output current. Figure 30 0.4A. The simplest method for adjusting the current exhibits the percent of error in the transfer function limit (ILIM) uses a resistor or potentiometer connected between ISET and IOUT versus the current limit set between the ISET pin and V–, according to Equation 1. resistor, RSET; Figure 31 and Figure 32 show how this error translates to variation in IOUT versus RSET. The If ILIM has been defined, RSET can be solved by dotted line represents the ideal output current setting rearranging Equation 1 into Equation 3: which is determined by the following equation: 24kW R @ - 5kW 1.2V SET I I@ 20000 x LIM LIM 5000 + R (3) SET (1) RSET in combination with a 5kΩ internal resistor The mismatch errors between the current limit set determines the magnitude of a small current that sets mirror and the output stage are primarily a result of the desired output current limit. variations in the ~1.2V bandgap reference, an internal Figure 37 shows a simplified schematic of the 5kΩ resistor, the mismatch between the current limit OPA564 current limit architecture. and the output stage mirror, and the tolerance and temperature coefficient of the RSET resistor referenced to the negative rail. Additionally, an increase in junction temperature can induce added mismatch in accuracy between the ISET and IOUT mirror. See Figure 53 for a method that can be used 1.2V to dynamically change the current limit setting using a Bandgap simple, zero drift current source. This approach £ simplifies the current limit equation to the following: IIOUT LIM @ ´ ILIM 20,000 ISET (2)

The current into the ISET pin is determined by the 5kW 1.2V NPN current source. Therefore, the errors contributed I @ ´ 20k LIM ()R + 5kW by the internal 1.2V bandgap reference and the 5kΩ OPA564 CL I resistor mismatch are eliminated, thus improving the SET overall accuracy of the transfer function. In this case, (1) RSET 1nF the primary source of error in ISET is the RSET resistor (optional, for noisy tolerance and the beta of the NPN transistor. environments) It is important to note that the primary intent of the V- current limit on the OPA564 is coarse protection of (1) At power-on, this capacitor is not charged. Therefore, the the output stage; therefore, the user should exercise OPA564 is programmed for maximum output current. Capacitor caution when attempting to control the output current values > 1nF are not recommended. by dynamically toggling the current limit setting. Predictable performance is better achieved by Figure 37. Adjustable Current Limit controlling the output voltage through the feedback loop of the OPA564.

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ENABLE/SHUTDOWN (E/S) PIN logic signal and the OPA564 shutdown pin are referenced to the same potential. In this configuration, The output of the OPA564 shuts down when the E/S the logic pin and the OPA564 enable can simply be pin is forced low. For normal operation (output connected together. Shutdown occurs for voltage enabled), the E/S pin must be pulled high (at least 2V levels of less than 0.8V. The OPA564 is enabled at above V–). To enable the OPA564 permanently, the logic levels greater than 2V. In dual-supply operation, E/S pin can be left unconnected. The E/S pin has an the logic pin remains referenced to a logic ground. internal 100kΩ pull-up resistor. When the output is However, the shutdown pin of the OPA564 continues shut down, the output impedance of the OPA564 is to be referenced to V–. 6GΩ || 120pF. The output shutdown output voltage versus output current is shown in Figure 42. Although Thus, in a dual-supply system, to shut down the the output is high-impedance when shut down, there OPA564 the voltage level of the logic signal must be is still a path through the feedback network into the level-shifted by some means. One way to shift the input stage to ground; see Figure 43. To prevent logic signal voltage level is by using an optocoupler, damage to the OPA564, ensure that the voltage as Figure 38 shows. across the input terminals +IN and –IN does not exceed 0.5V, and that the current flowing through the (a) +5V (b) HCTorTTLIn input terminals does not exceed 10mA when V+ operated beyond the supply rails, V– and V+. Refer to the Input Protection section.

Input Protection OPA564 E/S Electrostatic discharge (ESD) protection followed by (1) back-to-back diodes and input resistors (see Figure 43) are used for input protection on the OPA564. Exceeding the turn-on threshold of these diodes, as in a pulse condition, can cause current to 4N38 flow through the input protection diodes because of Optocoupler the finite slew rate of the amplifier. If the input current V- is not limited, the back-to-back diodes and the input devices can be destroyed. Sources of high input (a)HCTor (b) current can also cause subtle damage to the TTLIn amplifier. Although the unit may still be functional, important parameters such as input offset voltage, (1) Optional; may be required to limit leakage current of drift, and noise may shift. optocoupler at high temperatures. When using the OPA564 as a unity-gain buffer Figure 38. Shutdown Configuration for Dual (follower), as an inverting amplifier, or in shutdown Supplies (Using Optocoupler) mode, the input voltage between the input terminals (+IN and –IN) must be limited so that the voltage To shut down the output, the E/S pin is pulled low, no does not exceed 0.5V. This condition must be greater than 0.8V above V–. This function can be maintained across the entire common-mode range used to conserve power during idle periods. To return from V– to V+. If the inputs are taken above either the output to an enabled state, the E/S pin should be supply rail, the current must be limited to 10mA pulled to at least 2.0V above V–. Figure 27 shows the through the ESD protection diodes. During excursions typical enable and shutdown response times. It past the rails, it is still necessary to limit the voltage should be noted that the E/S pin does not affect the across the input terminals. If necessary, external internal thermal shutdown. back-to-back diodes should be added between +IN When the OPA564 will be used in applications where and –IN to maintain the 0.5V requirement between these connections. the device shuts down, special care should be taken with respect to input protection. Consider the Output Shutdown following two examples. The shutdown pin (E/S) is referenced to the negative supply (V–). Therefore, shutdown operation is slightly different in single-supply and dual-supply applications. In single-supply operation, V– typically equals common ground. Therefore, the shutdown

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Figure 39 shows the amplifier in a follower When the device shuts down in this situation, the load configuration. The load is connected midway between pulls VOUT to ground. Little or no current then flows the supplies, V+ and V–. through the input of the OPA564.

V+

W -IN 1.6k

V+

100W V- VOUT I1 I V+ 2 6GW 120pF V- +IN 1.6kW

V-

Figure 39. Shutdown Equivalent Circuit with Load Connected Midway Between Supplies

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Now consider Figure 40. Here, the load is connected This current flow produces a voltage across the to V–. When the device shuts down, current flows inputs which is much greater than 0.5V, which from the positive input +IN through the first 1.6kΩ damages the OPA564. A similar problem would occur resistor through an input protection diode, then if the load is connected to the positive supply. through the second 1.6kΩ resistor, and finally through the 100Ω resistor to V–.

CAUTION This configuration damages the device.

V+

W -IN 1.6k

V+

100W V- VOUT I1 I V+ 2 6GW 120pF V- +IN 1.6kW

V-

Figure 40. Shutdown Equivalent Circuit with Load Connected to V–: Voltage Across Inputs During DIsable Exceeds Input Requirements

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The solution is to place external protection diodes across the OPA564 input. Figure 41 illustrates this configuration.

NOTE This configuration protects the input during shutdown.

V+

External protection diodes W required; use Skyworks -IN 1.6k Solutions Inc. # SMS3922-004LF or equivalent V+

100W V- VOUT I1 I V+ 2 6GW 120pF V- +IN 1.6kW

V-

Figure 41. Shutdown Equivalent Circuit with Load Connected to V–: Protected Input Configuration

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Ensuring Microcontroller Compatibility within the optocoupler. A high logic level causes the Not all microcontrollers output the same logic state OPA564 to be enabled, and a low logic level shuts after power-up or reset. 8051-type microcontrollers, the OPA564 down. In the configuration of for example, output logic high levels while other Figure 38(b), with the logic signal applied on the models power up with logic low levels after reset. In anode side, a high level causes the OPA564 to shut the configuration of Figure 38(a), the shutdown signal down, and a low level enables the op amp. is applied on the cathode side of the photodiode

OUTPUTSHUTDOWNOUTPUTVOLTAGEvsOUTPUTCURRENT TestCircuit 500 ± VS = 12V 450 E/S =Low(OutputShutdown) 400

350 IOUT

300 OPA564 250 200 VOUT 150

OutputCurrent(pA) 100 50 0 -10 -8 -6 -4 -2 0 2 4 6 8 10 OutputVoltage(V)

Figure 42. Output Shutdown Output Impedance

V+

W -IN 1.6k External protection diodes as needed V+

V V- OUT R1 I1 I2 V+ 6GW 120pF V- W +IN 1.6k

V-

Figure 43. OPA564: Output Shutdown Equivalent Circuit (with External Feedback)

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CURRENT LIMIT FLAG Depending on load and signal conditions, the thermal protection circuit may cycle on and off. This cycling The OPA564 features a current limit flag (IFLAG) that limits the amplifier dissipation, but may have can be monitored to determine if the load current is undesirable effects on the load. Any tendency to operating within or exceeding the current limit set by activate the thermal protection circuit indicates the user. The output signal of IFLAG is compatible with excessive power dissipation or an inadequate standard CMOS logic and is referenced to the heatsink. For reliable, long-term, continuous negative supply pin (V–). A voltage level of + 0.8V or operation, with I at the maximum output of 1.5A, less with respect to V indicates that the amplifier is OUT – the junction temperature should be limited to +85°C operating within the limits set by the user. A voltage maximum. Figure 44 shows the maximum output level of +2.0V or greater with respect to V– indicates current versus junction temperature for dc and RMS that the OPA564 is operating above (exceeds) the signal outputs. To estimate the margin of safety in a current limit set by the user. See Setting the Current complete design (including heatsink), increase the Limit for proper current limit operation. ambient temperature until the thermal protection triggers. Use worst-case loading and signal OUTPUT STAGE COMPENSATION conditions. For good, long-term reliability, thermal The complex load impedances common in power op protection should trigger more than 35°C above the amp applications can cause output stage instability. maximum expected ambient condition of the For normal operation, output compensation circuitry is application. typically not required. However, if the OPA564 is The internal protection circuitry of the OPA564 was intended to be driven into current limit, an R/C designed to protect against overload conditions; it network (snubber) may be required. A snubber circuit was not intended to replace proper heatsinking. such as the one shown in Figure 54 may also Continuously running the OPA564 into thermal enhance stability when driving large capacitive loads shutdown degrades reliability. (greater than 1000pF) or inductive loads (for example, motors or loads separated from the MAXIMUMOUTPUTCURRENTvsJUNCTIONTEMPERATURE amplifier by long cables). Typically, 3Ω to 10Ω in series with 0.01mF to 0.1mF is adequate. Some 1.6 variations in circuit value may be required with certain 1.4 loads. 1.2

OUTPUT PROTECTION 1.0

The output structure of the OPA564 includes ESD OUT 0.8 diodes (see Figure 43). Voltage at the OPA564

MaxI0.6 (A) output must not be allowed to go more than 0.4V beyond either supply rail to avoid damaging the 0.4 MaxI (dc) device. Reactive and electromagnetic field 0.2 OUT (EMF)-generation loads can return load current to the MaxIOUT (RMS) 0 amplifier, causing the output voltage to exceed the - - power-supply voltage. This damaging condition can 50 25 0 25 50 75 100 125 ° be avoided with clamping diodes from the output TJ ( C) terminal to the power supplies, as Figure 54 and Figure 55 illustrate. Schottky rectifier diodes with a 3A Figure 44. Maximum Output Current vs Junction or greater continuous rating are recommended. Temperature

THERMAL PROTECTION USING TSENSE FOR MEASURING JUNCTION The OPA564 has thermal sensing circuitry that helps TEMPERATURE protect the amplifier from exceeding temperature limits. Power dissipated in the OPA564 causes the The OPA564 includes an internal diode for junction junction temperature to rise. Internal thermal temperature monitoring. The h-factor of this diode is shutdown circuitry disables the output when the die 1.033. Measuring the OPA564 junction temperature temperature reaches the thermal shutdown can be accomplished by connecting the TSENSE pin to temperature limit. The OPA564 output remains shut a remote-junction temperature sensor, such as the down until the die has cooled sufficiently; see the TMP411 (see Figure 57). Electrical Characteristics, Thermal Shutdown section.

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POWER DISSIPATION AND SAFE Once the heatsink area has been selected, OPERATING AREA worst-case load conditions should be tested to ensure proper thermal protection. Power dissipation depends on power supply, signal, and load conditions. For dc signals, power dissipation space is equal to the product of output current (IOUT) and the voltage across the conducting output transistor SAFEOPERATINGAREAATROOMTEMPERATURE [(V+) – V when sourcing; V – (V–) when OUT OUT 10.0 sinking]. Dissipation with ac signals is lower. Application Bulletin AB-039, Power Amplifier Stress and Power Handling Limitations (SBOA022, available for download from www.ti.com) explains how to calculate or measure power dissipation with unusual signals and loads. 1.0 Copper,Soldered Figure 45 shows the safe operating area at room with200LFMAirflow

temperature with various heatsinking efforts. Note OutputCurrent(A) that the safe output current decreases as (V+) – VOUT Copper,Soldered or VOUT – (V–) increases. Figure 46 shows the safe withoutForcedAir operating area at various temperatures with the 0.1 PowerPAD being soldered to a 2oz copper pad. 0 2 4 6 8 10 12 14 16 18 20 22 24 26 (V+)- V ,V -- (V )(V) The power that can be safely dissipated in the OUT OUT package is related to the ambient temperature and the heatsink design. The PowerPAD package was Figure 45. Safe Operating Area at Room specifically designed to provide excellent power Temperature dissipation, but board layout greatly influences the heat dissipation of the package. Refer to the Thermally-Enhanced PowerPAD Package section for SAFEOPERATINGAREAATVARIOUSAMBIENTTEMPERATURES further details. (PowerPADSoldered) 10.0 - ° TA = 40 C The relationship between thermal resistance and ° TA =0 C ° power dissipation can be expressed as: TA =+25 C ° TA =+85 C TJ = TA + TJA 1.0 ° TA =+125 C

TJA = PD × qJA Combining these equations produces: 0.1

OutputCurrent(A) TJ = TA + PD × qJA where: T = Junction temperature (°C) 0.01 J 0 2 4 6 8 10 12 14 16 18 20 22 24 26 (V+)- V ,V -- (V )(V) TA = Ambient temperature (°C) OUT OUT qJA = Junction-to-ambient thermal resistance (°C/W) PowerPAD soldered to a 2oz copper pad.

PD = Power dissipation (W) Figure 46. Safe Operating Area at Various To determine the required heatsink area, required Ambient Temperatures power dissipation should be calculated and the relationship between power dissipation and thermal resistance should be considered to minimize shutdown conditions and allow for proper long-term operation (junction temperature of +85°C or less).

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For applications with limited board size, refer to THERMALLY-ENHANCED PowerPAD Figure 47 for the approximate thermal resistance PACKAGE relative to heatsink area. Increasing heatsink area beyond 2in2 provides little improvement in thermal The OPA564 uses the HSOP-20 PowerPAD DWP and DWD packages, which are thermally-enhanced, resistance. To achieve the 33°C/W shown in the Electrical Characteristics, a 2oz copper plane size of standard size IC packages. These packages enhance 9in2 was used. The PowerPAD package is well-suited power dissipation capability significantly and can be for continuous power levels from 2W to 4W, easily mounted using standard printed circuit board depending on ambient temperature and heatsink (PCB) assembly techniques, and can be removed area. The addition of airflow also influences maximum and replaced using standard repair procedures. power dissipation, as Figure 48 illustrates. Higher The DWP PowerPAD package is designed so that power levels may be achieved in applications with a the leadframe die pad (or thermal pad) is exposed on low on/off duty cycle, such as remote meter reading. the bottom of the IC, as shown in Figure 49a; the DWD PowerPAD package has the exposed pad on THERMALRESISTANCEvsCIRCUITBOARDCOPPERAREA the top side of the package, as shown in Figure 49b. The thermal pad provides an extremely low thermal 45 resistance (qJC) path between the die and the exterior of the package. 40 ° PowerPAD packages with exposed pad down are

JA q designed to be soldered directly to the PCB, using 35 the PCB as a heatsink. Texas Instruments does not recommend the use of the of a PowerPAD package 30 without soldering it to the PCB because of the risk of OPA564 lower thermal performance and mechanical integrity. 25 SurfaceMountPackage In addition, through the use of thermal vias, the

ThermalResistance, ( C/W) 2ozcopper bottom-side thermal pad can be directly connected to a power plane or special heatsink structure designed 20 0 1 2 3 4 5 into the PCB. The PowerPAD should be at the same 2 CopperArea(inches ) voltage potential as V–. Soldering the bottom-side PowerPAD to the PCB is always required, even with applications that have low power dissipation. It Figure 47. Thermal Resistance vs Circuit Board provides the necessary thermal and mechanical Copper Area connection between the leadframe die and the PCB. Pad-up PowerPAD packages should have MAXIMUMPOWERDISSIPATIONvsTEMPERATURE appropriately designed heatsinks attached. Because 6 of the variation and flexible nature of this type of heat NoCopper sink, additional details should come from the specific 5 Copper,Soldered manufacturer of the heatsink. withoutForcedAir 4 Copper,Soldered with200LFMAirflow 3

PowerDissipationinPackage(W)

0 0 25 50 75 100 125 Temperature(° C)

Figure 48. Maximum Power Dissipation vs Temperature

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Leadframe (Copper Alloy)

IC (Silicon) Die Attach (Epoxy) Die External Heatspreader Pad

Die Thermal Attach Chip Paste

Power Transistor

Leadframe Die Pad Exposed at Base of the Package Board

Mold Compound (Epoxy)

(a) DWP PowerPAD cross-section view (b) DWD PowerPAD cross-section view

Figure 49. Cross-Section Views holes under the PowerPAD package should be Bottom-Side PowerPAD Assembly Process connected to the internal plane with a complete 1. The PowerPAD must be connected to the most connection around the entire circumference of the negative supply of the device, V–. plated through-hole. 2. Prepare the PCB with a top side etch pattern, as 7. The top-side solder mask should leave exposed shown in the attached thermal land pattern the terminals of the package and the thermal pad mechanical drawing. There should be etch for the area. The thermal pad area should leave the leads as well as etch for the thermal land. 13mil holes exposed. The larger 25mil holes 3. Place the recommended number of holes (or outside the thermal pad area should be covered thermal vias) in the area of the thermal pad, as with solder mask. seen in the attached thermal land pattern 8. Apply solder paste to the exposed thermal pad mechanical drawing. These holes should be area and all of the package terminals. 13mils (.013in, or 330.2mm) in diameter. They are 9. With these preparatory steps completed, the kept small so that solder wicking through the PowerPAD IC is simply placed in position and run holes is not a problem during reflow. through the solder reflow operation as any 4. It is recommended, but not required, to place a standard surface-mount component. This small number of the holes under the package and processing results in a part that is properly outside the thermal pad area. These holes installed. provide an additional heat path between the copper land and ground plane and are 25mils For detailed information on the PowerPAD package including thermal modeling considerations and repair (.025in, or 635mm) in diameter. They may be larger because they are not in the area to be procedures, see Technical Brief SLMA002, soldered, so wicking is not a problem. This PowerPAD Thermally Enhanced Package, available configuration is illustrated in the attached thermal at www.ti.com. land pattern mechanical drawing. 5. Connect all holes, including those within the thermal pad area and outside the pad area, to the internal plane that is at the same voltage potential as V–. 6. When connecting these holes to the internal plane, do not use the typical web or spoke via connection methodology (as Figure 50 shows). Web connections have a high thermal resistance SolidVia WeborSpokeVia connection that is useful for slowing the heat RECOMMENDED NOTRECOMMENDED transfer during soldering operations. This configuration makes the soldering of vias that have plane connections easier. However, in this Figure 50. Via Connection Methods application, low thermal resistance is desired for the most efficient heat transfer. Therefore, the

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R2 APPLICATIONS CIRCUITS 1kW The high output current and low supply of the OPA564 make it a good candidate for driving laser VDIG +5V 47mF diodes and thermoelectric coolers. Figure 51 shows an improved Howland current pump circuit.

0.1m F POWERLINE COMMUNICATION R1 20k W Powerline communication (PLC) applications require some form of signal transmission over an existing ac OPA564 VO I SET power line. A common technique used to couple these modulated signals to the line is through a signal R SET transformer. A power amplifier is often needed to provide adequate levels of current and voltage to drive the varying loads that exist on today’s 0.1m F powerlines. One such application is shown in

R Figure 52. The OPA564 is used to drive signals used 47m F 5 50mW in frequency modulation schemes such as FSK (Frequency-Shift Keying) or OFDM (Orthogonal -5V R4 R4 Frequency-Division Multiplexing) to transmit digital 20kW 1kW information over the powerline. The power output +1V/+1A capabilities of the OPA564 are needed to drive the current requirements of the transformer that is shown in the figure, coupled to the ac power line via a coupling capacitor. Circuit protection is often needed (1) See Figure 35 for an example of a basic noninverting amplifier or required to prevent excessive line voltages or with VDIG not exceeding 5.5V. current surges from damaging the active circuitry in the power amplifier and application circuitry. Figure 51. Improved Howland Current Pump

VDIG

(1) (1) C2 C3 + C R R R3 1 1 F S1 S3 0.1m F 47m F INPUT

(2) L1 C5 C6 OPA564

1/2 VS T1 1 6 E/S (3) D (1) (1) 1 S2 S4 SMBJ12CA or 3 4 (4) C4 SMBJ6.0CA R 4 10pF GND

(1) S1, S2, S3, and S4 are Schottky diodes. S1 and S2 are B350 or equivalent. S3 and S4 are BAV99T or equivalent.

(2) L1 should be small enough so that it does not interfere with the bandwidth of interest but large enough to suppress transients that could damage the OPA564.

(3) D1 is a transient suppression diode. For 24V supplies, use SMBJ12CA. For 12V supplies, use SMBJ6.0CA. Voltage rating of transient voltage suppressor should be half the supply rating or less.

(4) The minimum recommended value for R4 is 7.5kΩ. Figure 52. Powerline Communication Line Coupling

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PROGRAMMABLE POWER SUPPLY For more information on this circuit, see the Application Bulletin DC Motor Speed Controller: Figure 53 shows the OPA333 used to control ISET in Control a DC Motor without Tachometer Feedback order to adjust the current limit of the OPA564. (SBOA043), available for download at the TI web site. Figure 54 shows a basic motor speed driver but does Figure 56 shows two examples of generating the not include any control over the motor speed. For signal for V . Figure 56a uses an 1N4732A zener to applications where good control of the speed of the DIG bias the V to precisely 4.7V above V–. Figure 56b motor is desired, but the precision of a tachometer DIG uses a high-voltage subregulator to derive the VDIG control is not required, the circuit in Figure 55 voltage. Figure 58 illustrates a detailed powerline provides control by using feedback of the current communication circuit. consumption to adjust the motor drive.

R1 RF

V+

OPA564 VOUT

VIN R ISET F VIN (1 + ) +5V R1 RLOAD IOUT IOUT = £ ILIM RLOAD V-

IILIM@20,000 ´ SET OPA333 T1 2N2923 I + I @ LIM VSET SET C1 20,000 100mV 100pF I (0.4A to 1.5A) = 20m A to 75 m A V SET SET and R SET ISET VSET (0.4A to 1.5A) = 100mV to 375mV 5kW

Figure 53. Programmable Current Limit Option

Note(3) V+

C1 C2 (1) 0.1m F 47m F Z1 R1 R2 5kW 20kW (2) VIN S1 R2 V G= - = -4 DIG R1

OPA564 10W (2) (Non- S2 inductive) Motor 0.01m F C1 C2 0.1m F 47m F (1) V- Z2

Note(3)

(1) Z1, Z2 = zener diodes (IN5246 or equivalent). Select Z1 and Z2 diodes that are capable of the maximum anticipated surge current.

(2) S1, S2 = Schottky diodes (STPS1L40 or equivalent).

(3) C1 = high-frequency bypass capacitors; C2 = low-frequency bypass capacitors (minimum of 10mF for every 1A peak current) Figure 54. Motor Drive Circuit

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Note (4) +12V

C1 C2 (2) 0.1m F 47m F Z1

R1 R2 1kW 10kW

VIN

VDIG (3) S1

(1) OPA564

R3 5kW RM = 12W (3) RSET S2 RM C1 C2 0.1m F 47m F dc EMF (2) Motor -12V Z2

Note (4)

RS 1W

(1) IFLAG and TFLAG connections are not shown.

(2) Z1, Z2 = zener diodes (IN5246 or equivalent). Select Z1 and Z2 diodes that are capable of the maximum anticipated surge current.

(3) S1, S2 = Schottky diodes (STPS1L40 or equivalent).

(4) C1 = high-frequency bypass capacitors; C2 = low-frequency bypass capacitors (minimum of 10mF for every 1A peak current). Figure 55. DC Motor Speed Controller (without Tachometer)

IIN IOUT IN OUT 1 5 CI1 CI2 COUT V+ 1000m F 100nF 22m F R TLE4275-Q1 EXT 5kW 10kW IRO V DELAY RESET V V IN 4 2 OUT DIG 3 4.7V ID,c ID,d Zener GND 1N4732A CD VRD VD IGND V- 47nF

(a) (b)

Figure 56. Circuits for Generating VDIG

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V+

V DIG +5V

-IN VOUT OPA564 0.1m F +IN 10kW 10kW 10kW 10kW T SENSE 1 (typ) (typ) (typ) (typ) V- 50W V+ 2 8 D+ SCL 50pF TMP411 3 7 SMBus SDA D- Controller 6 ALERTTHERM2/ 4 THERM Over-Temperature GND Fault 5

Figure 57. Temperature Measurement Using TSENSE and TMP411

+3.3V

R46 10k

R47 10k +3.3V +3.3V 150pF R6 C1 C2 0.1uF C6 0.1uF 15k R48 R8 R7 C5 10k 30k 5 GND 2.67k 82pF GND C11 U1 5 R13 4 U2 R10 R14 6.8k 1 4 C9 R49 100nF 3 3.3k 1.47k 1 10k 3 OPA365 1.0uF R11

2 OPA365 C7 C8 30k 2 820pf 10nF GND TP1 1 GND Test Point TEST POINT J2 J3 SPISOMIA_GPIO17 1 TXRX 1 SPISIMOA_GPIO16 2 2 SPICLKA_GPIO18 3 TXDRVEN_GPIO32 3 +15V SPISTEA_GPIO19 4 4 +15V PWM2_GPIO02 GND 5 ADCIN 5 TXDRVEN_GPIO32 PWM1_GPIO00 R50 6 6 +3.3V LED GPIO20 7 7 10k GND C19 C18 8 8 JP5 LED GPIO21 10uF 0.1uF 1SMB5930 or equivalent JUMPER 9 9 P1 10 10 LED GPIO22 U4 11 11 +15V 12 12 1 R24 C17 1 20 D4 1 Test Point V- V- TXRX 1 2 Pad TEST POINT 12 HEADER GND 12 HEADER 10k 0.1uF 2 19 B350A-13-F V+ V+pwrSence Gnd 3 18 GND 10.0k TFLG V+pwr FREE PAD GND 4 17 C14 E/S V+pwr L1 1uH, 1.075A R16 TP8 R22 5 16 R20 Heat sink Pads +IN Vout 1 6 15 LB3218T1ROM P2 10.0k Test Point -IN Vout 0 ohm R45 TEST POINT 7 14 10 uF 2.49k VDIG V-pwr 0 ohm R19 8 13 D5 D1 IFLAG V-pwr C12 9 12 B350A-13-F or equivalent 1 ISET TSENSE Pad R4 1 10 11 Test Point V- V- 228 ohm TEST POINT FREE PAD GND LED +3.3V 2700pF TP3 R25 OPA564AIDWP 1 10k D2 Test Point +3.3V TEST POINT R17 R3 C13 0.1uF TP4 16.5k 228 ohm R18 C99 LED 12.0k 50pF GND 5 GND 1 Test Point D3 TEST POINT 4 U5 GND 21 Gnd R5 1 R21 22 35 TP2 Gnd Gnd 3 +3.3V 23 34 228 ohm 1.0 ohms Gnd Gnd LED 24 33 Gnd Gnd 25 32 OPA365 Gnd Gnd C15 26 31 2 Gnd Gnd 100nF C20 27 30 GND Gnd Gnd +3.3V 0.1uF 28 29 Gnd Gnd R23 GND GND Power Pad OPA564 10.0k C16 GND 0.1uF L3 D6 470uH R27 B350A-13-F GND C22 150 ohm 22nf GND C40 C21 L2 R26 330uH 150 ohm 10uF 1 33nf Test Point D7 TEST POINT B350A-13-F TP7

+3.3V C26 R34 0.1uF GND +3.3V 3.83k R35 C30 C29 GND 4.4k 82pf C25 0.1uF 82pf

5 GND

U6 5 R31 R28 4 U7 R32 R29 3.83k 15.4k 1 4 3 4.4k 4.4k 1 3 OPA365

2 OPA365 C23 470pf C24 2 GND 1500pf GND

1 Test Point TEST POINT TP5 TP6 1 Test Point TEST POINT +3.3V C36 SPISIMOA_GPIO16 0.1uF GND

GND U10 C37 +3.3V 1 10 0.1uF AVDD DVDD 2 9 R41 CH1 NOT CS SPISTEA_GPIO19 0.0 ohm 3 8 CH0/VCAL DIO SPISOMIA_GPIO17 4 7 Vref SCLK SPICLKA_GPIO18 5 6 ADCIN Vout GND PGA112

Figure 58. Detailed Powerline Communication Circuit

www.ti.com SBOS372E –OCTOBER 2008–REVISED JANUARY 2011

REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision D (November, 2010) to Revision E Page

• Changed RCL to RSET throughout document ...... 1 • Updated Absolute Maximum Ratings table, signal input terminals specifications; added new footnote ...... 2 • Deleted current through back-to-back input protection diodes specification; added maximum differential voltage across inputs specification ...... 2 • Changed footnote (4) in Absolute Maximum Ratings table ...... 2 • Revised conditions for Electrical Characteristics table ...... 3 • Revised conditions for Electrical Characteristics table ...... 4 • Updated current limit equation ...... 4

• Changed ideality factor value for TSENSE parameter ...... 4 • Changed footnote (5) in Electrical Characteristics table ...... 4 • Revised conditions for Electrical Characteristics table ...... 5

• Deleted condition statement for IQ and IQSD parameters in Electrical Characteristics table ...... 5

• Updated minimum value for VDIG parameter in Electrical Characteristics table ...... 5

• Changed description of VDIG pin operation ...... 6 • Updated condition statement for Typical Characteristics ...... 8 • Corrected y-axis values in Figure 1 ...... 8

• Revised Setting the Current Limit section to update maximum value for RSET ...... 15 • Revised ENABLE/SHUTDOWN Pin section ...... 16 • Added Input Protection section ...... 16 • Added Figure 39 ...... 17 • Added Figure 41 ...... 19 • Changed Figure 43 ...... 20 • Changed ideality factor value ...... 21 • Changed Figure 52 ...... 25 • Corrected signal indicators shown in Figure 53 ...... 26 • Updated footnote (1) to Figure 54 ...... 26 • Changed footnote (2) to Figure 54 ...... 26 • Changed footnote (2) to Figure 55 ...... 27 • Updated footnote (3) to Figure 55 ...... 27 • Revised Figure 58 ...... 28

Changes from Revision C (November, 2009) to Revision D Page

• Deleted references to HTSSOP-20 (PWP) package throughout document; this package version will not be manufactured ...... 1 • Removed HTSSOP-20 (PWP) package option and footnote (2) from Package/Ordering Information table ...... 2 • Deleted HTSSOP-20 PWP package thermal resistance information in Electrical Characteristics table ...... 5

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) OPA564AIDWD ACTIVE HSOP DWD 20 25 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA564

OPA564AIDWDR ACTIVE HSOP DWD 20 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA564

OPA564AIDWP ACTIVE SO PowerPAD DWP 20 25 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA564

OPA564AIDWPR ACTIVE SO PowerPAD DWP 20 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA564

(1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF OPA564 : • Automotive: OPA564-Q1

NOTE: Qualified Version Definitions: • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2 PACKAGE MATERIALS INFORMATION

www.ti.com 14-Feb-2019

TAPE AND REEL INFORMATION

*All dimensions are nominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1 (mm) OPA564AIDWDR HSOP DWD 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 OPA564AIDWPR SO DWP 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 Power PAD

Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION

www.ti.com 14-Feb-2019

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) OPA564AIDWDR HSOP DWD 20 2000 350.0 350.0 43.0 OPA564AIDWPR SO PowerPAD DWP 20 2000 350.0 350.0 43.0

Pack Materials-Page 2

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