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A High Gain CMOS Operational Amplifier with Negative Conductance Gain Enhancement Jie Yan and Randall L

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A High Gain CMOS Operational Amplifier with Negative Conductance Gain Enhancement Jie Yan and Randall L A High Gain CMOS Operational Amplifier With Negative Conductance Gain Enhancement Jie Yan and Randall L. Geiger Department of Electrical and Computer Engineering, Iowa State University, Ames, IA 5001 1, USA Abstract A fully differential CMOS operational amplifier using a negative conductance gain enhancement technique is presented. The amplifier was fabricated in an AMI 0.5 um CMOS process with an active area of 0.17 mm'. With a 3 Volts supply, a DC gain of more than 80dB was measured. - The gain exceeded 60 dB for a 240mV output swing. (4 (b) Fig. 1 Basic concept of negative conductance gain enhancement technique 1. Introduction The realization of high-gain amplifiers, with large Gain- Several researchers have proposed negative Bandwidth-Products (GB) in processes with decreasing impedance gain enhancement circuits. Allstot [2] used a supply voltages is becoming a challenging task. For two cross-drain-coupled differential pair to generate the negative decades, researchers have been enhancing amplifier gain by impedance. Gregorian suggests this approach can practically increasing the output impedance of a basic gain stage. This increase the gain by only a factor of 4 [3]. Nauta applied approach has proven effective for realizing high gain and negative resistance to a simple inverting transconductor in high GB with favorable power dissipation. Two approaches order to increase the DC gain of the transconductor [4], [5]. for output impedance enhancement are widely used. One uses Nauta reported a DC gain of 46dB with a 1OV power supply. cascoding and the second uses a regulated cascode approach In [6], positive feedback was applied to generate an effective [ 13. For low supply processes, these cascoded approaches are negative load conductance. Although a gain of 80dB was becoming unviable. A third approach, based upon negative reported with a 1OV supply voltage, the gain-bandwidth- transconductance compensation, has been discussed in the product was only 12MHz for a 5pF capacitor load. The literature. Although this latter approach offers potential for structure in [6] requires a high frequency differential gain the most gain enhancement, low power dissipation, low stage to achieve conductance cancellation. This gain stage voltage operation, and excellent high frequency performance, introduces internal nodes and thus limits the high-frequency the technique is seldom used commercially because of the response. high sensitivity of the gain to the negative transconductance These structures all share a common characteristic; a element inherent in existing negative transconductance negative transconductance is used to compensate for positive schemes. In this paper, we exploit a negative impedance gain output conductances. To achieve adequate gain enhancement, enhancement technique with an approach that significantly the negative transconductance must precisely compensate the reduces the gain variability to the compensating impedance. positive output conductance. The major drawback of using negative transconductance to compensate for the output 2. Negative Impedance Gain Enhancement conductance is the difficulty in accurately matching these The basic concept of gain enhancement by negative unlike terms over process and temperature. This drawback impedance compensation is shown in Fig.1 (a). Negative has limited the practical utilization of this approach. resistor R, is placed in parallel with the output impedance of A new negative impedance gain enhancement circuit the basic amplifier. It follows from the small signal was proposed that generates a negative conductance rather equivalent circuit of Fig. 1 (b) that the small signal gain of the than a negative transconductance [7]. The negative amplifier when driving a capacitive load CL is conductance circuit is added at the output of a simple one- stage amplifier to practically achieve substantial gain enhancement. Fig. 2 shows the concept of the proposed negative conductance gain enhancement technique. A PMOS -1 transistor M, is placed at the output of the basic amplifier. A IfR, =-, the DC gain becomes infinite. Since this gain low gain stage A is. connected between the gate and the g ds source of M,. Transistor M, is biased in the saturation region enhancement approach does not introduce additional internal and its gate-source voltage is AC shorted. Body effects are nodes, it does not adversely reduce the high-frequency eliminated if an n-well CMOS process is used. If the gain of response of the basic amplifier so wide bandwidth can be the low gain stage, A, is larger than 1, then a negative realized. conductance of ( l-A).gdSnparallels the output conductance of 19-4-1 0-7803-7250-6/02/$10.00 0 2002 IEEE IEEE 2002 CUSTOM INTEGRATED CIRCUITS CONFERENCE 337 the basic amplifier. The small signal gain of this circuit is common-mode feedback circuit (CMFB), a hias generator, given by the expression and the second stage. The amplifier was designed to have most of the DC gain contributed by the first s:tage while the - g1111 A "(S) = (2) second stage only provides a gain of 2 to 3. For a given gain, scL + gdsl + gds2 + gdsn (l - A) the output signal swing requirements of the first stage is From this expression it is apparent that the dc gain goes to reduced by a factor of 2 to 3 by adding the second stage. The infinity as (A-l)gdsnapproaches gdsl+gds2and that as (A-l)gds, overall amplifier thus can maintain a large overall voltage is increased, the open-loop pole crosses into the right half- gain over a wider output range [8]. plane when gdsl+gds2 = (A-l)gdsn . Fig. 4 shows the transistor-level schematic of the basic amplifier and the second stage. Fig. 5 shows the transistor- level schematic of the negative conductance generator. The low gain stage A is shown in Fig. 6. The 13ias generator provides biasing voltages VBpand VBN.The CMFB circuit I " provides VCM for transistor M6 to control the common-mode v,+p =p v,'41'~~L J voltage at the output of the basic amplifier. Their schematics are not shown in this paper. --- --- --?=.. (2) (b 1 T Fig. 2 A new negative impedance gain enhancement technique a) Basic amplifier, b) Basic amplifier with negative conductance gain enhancement. The proposed gain enhancement technique generates a negative conductance that is only a function of gds and is not related to g,. Therefore, negative gds can realistically match positive gd, terms and the matching requirements for achieving very high DC gain are less stringent than for the existing -gm gain enhancement schemes. Further, this circuit Fig. 4 Schematic of a) Basic amplifier, b) the second stage has the potential for precise digital control of a large dc gain by exploiting the property that there is a phase reversal as the pole crosses the origin in the open-loop transfer function that -r vy I r r can be detected. Since gds=hI,,, the negative conductance can be easily adjustable through the adjustment of the biasing current of transistor M,. 3. Implementation of Fully Differential CMOS Op Amp A prototype two-stage fully differential high gain amplifier was designed based on the proposed negative conductance gain enhancement technique to validate the fundamental performance characteristics of the negative V," v,, conductance gain enhancement technique. The block diagram Fig. 5 Schematic of negative conductance generator of the amplifier is shown in Fig. 3. 7- Vi+ Negative 1 -- Fig. 6 Schematic of low gain stage A Fig. 3 Block diagram of the fully differential amplifier The negative conductance generator generates a negative conductance which is proportional to the conductance of The amplifier consists of five elements, a basic amplifier transistors Mnl and Mn2. The negative conductance is (the first stage), a negative conductance generator (NG), a 338 19-4-2 adjustable by changing the control voltage Vctl thus change feedback resistors. The differential error signals Vi+and Vi. at the bias current of transistors Mnl and Mn2. the op amp input were amplified by an off-chip amplifier A half circuit of the basic amplifier useful for with gain of 185. The output signals V,, and V, were also determining the DC gain is shown in Fig.7. The DC gain is measured. The open-loop differential DC gain is given by the expression Vout - -grid (3) "=K - +gd.Q fgd,)+gds,+kgm,+(l-A)gd.sn (9) where k = "" (4) gd.sb + gm, Fig. 8 Scheme for measuring open-loop DC gain ------& - The die photo of the amplifier is shown in Fig. 9. The active area is 0.17 mm2. Fig. 7 The half circuit'of the basic amplifier From equation (4), if gdsb << g,, , k will be a small number and the g, term in the denominator of equation (3) can be ignored so the DC gain becomes %ut - -gml (5) "=K - (gd.\l +gd.Q +gd.~)+gd,,b+(l-A)gd.sn The relationship between ID2 and the control voltage V,,, is given by ID, =: nox 2 /J w5(Vctrl - V,,) (6) 2L5 Since gd.s zAzD (7) Fig. 9 Die photo of the amplifier only one value of Vcul will make the denominator of the gain expression (5) zero and Avdinfinite. The amplifier was tested with k1.5 V supply voltages. If ghb is comparable to g,, , the g, term in the denominator Fig. 10 shows the differential output signal (Math) and the of the gain expression (3) should be taken into account. Since amplified differential error signal (Ch3) for a control voltage g, = J2/Jcox (w L)lD (8) Vctrl of -0.75871 Volt. The differential error signal is in there are multiple values of Vcul that will make the phase with the differential output signal. The open-loop DC denominator of the gain of (3) zero and correspondingly Avd gain is 80.24dB. Fig. 11 shows differential output signal infinite.
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