A FULLY DIFFERENTIAL CMOS OPERATIONAL AMPLIFIER IMPLEMENTED WITH MOS GAIN BOOSTING TECHNIQUE by PING LO, B.S.E.E. A THESIS IN ELECTRICAL ENGINEERING Submitted to the Graduate Faculty of Texas Tech University in Partial Fulfillment of the Requirements for the Degree of MASTER OF SCIENCE IN ELECTRICAL ENGINEERING Approved Accepted May, 1996 I C^Cjk ACKNOWLEDGEMENTS I like to express my gratefulness to Professor Kwong Shu Chao, without whose thoughtful guidance and patience, the success of this work would never have been possible. I am also thankful to Professor Sunanda Mitra and Osamu Ishihara for their interest and advice in this work. I appreciate the support of my fellow students in the EE department, in particular, Ramesh M.C. for his circuit insight, and Stephen Bayne for his help in chip testing. Lastly, I would like to dedicate this thesis to my father, for his unprecedented love and support throughout my graduate studies. Without him, my study here would not have been possible. TABLE OF CONTENTS ACKNOWLEDGMENTS ii LISTOFTABLES v LIST OF FIGURES vi CHAPTER I. INTRODUCTION 1 1.1 Motivation 1 1.2 Structure of Thesis 3 II. OPERATIONAL AMPLIFIER DESIGN REVIEW 4 2.1 Performance Metrics 4 2.2 Differential Amplifiers 6 2.3 Operational Amplifier Toplogies 8 2.3.1 Multi-Stage Amplifier 8 2.3.2 Single Stage Amplifier 11 2.3.3 Gain Boosting Techniques 14 III. SUPER-MOST STRUCTURE 16 3.1 Overview of Current Mirror Structures 16 3.2 Principle of Super-MOST 19 3.3 Super-MOST Topologies 23 3.3.1 Topology 1 23 3.3.2 Topology 2 26 iii 3.4 Proposed New Structure 28 3.4.1 Circuit Analysis 30 3.4.2 Simulation Results 31 IV. DESIGN OF FULLY DIFFERENTIAL OPERATIONAL AMPLIFIER 38 4.1 Design considerations 39 4.2 Operational Amplifier Architecture 40 4.2.1 Comparisons of Single Stage and Two Stages Implementation 40 4.2.2 Comparisons of Single Ended and Differential Implementation 41 4.3 Circuit Description 42 4.3.1 Main Stage 42 4.3.2 Bias Circuit 48 4.3.3 Common Mode Feedback Circuit 49 4.4 Simulation Results 52 V. EXPERIMENTAL RESULTS 60 5.1 Description of Experimental Chip 60 5.2 Test Setup 61 5.3 Test Results 62 VI. CONCLUSION 69 REFERENCES 71 APPENDIX: MOSIS PROCESS PARAMETER 74 IV LIST OF TABLES 3.1 Dimensions of transistors in Super-MOST 33 4.1 Dimensions of transistors in the operational amplifier 58 4.2 Summary of fully differential operational amplifier performance 59 LIST OF FIGURES 2.1 Differential amplifier 6 2.2 AC equivalent model of the differential amplifier 8 2.3 Two-stage operational amplifier configuration 9 2.4 Telescopic cascode amplifier 12 2.5 Folded cascode operational amplifier 13 2.6 Mirrored cascode operational amplifier 13 2.7 Cascode Circuits 14 3.1 Cascode (a) transistors circuit, (b) small-signal equivalent circuit 17 3.2 Regulated cascode transistors 19 3.3 Simple Super-MOST structure 21 3.4 Modified Super-MOST structure 23 3.5 Super-MOST configuration 1 24 3.6 Super-MOST configuration 2 27 3.7 Proposed Super-MOST configuration 28 3.8 Symbols for (a) N-type, (b) P-type Super-MOST 29 3.9 Current-voltage characteristics of (a) a single n-transistor, (b) the N-type Super-MOST with KG-T ranging from-1.5 V to-1 V 34 3.10 Current-voltage characteristics of (a) a single p-transistor, (b) the P-type Super-MOST with KGS ranging from 1 V to 1.5 V 35 3.11 Simulation result of the current mirror using N-type Super-MOST with /,„ ranging from 40 (xA to 200 fxA 36 VI 3.12 Frequency response of the inverting amplifier 37 3.13 Output voltage swing of the inverting amplifier 37 4.1 Main stage of the fully differential operational amplifier 43 4.2 Equivalent circuit of the Super-MOST 44 4.3 Equivalent circuit for the input differential pair 45 4.4 Small signal equivalent half circuit of the main stage 47 4.5 Bias circuit 48 4.6 Simplified configuration of a fully differential switched capacitor network . 50 4.7 Common mode feedback circuit 51 4.8 Frequency reponse of the fully differential operational amplifier (a) magnitude plot, (b) phase plot 53 4.9 Step response of the fully differential operational amplifier with (a)±0.2V,(b)± 1.5 V input 54 4.10 Output voltage swing of the fully differential amplifier 55 4.11 Transient response with 5 mV sinusoidal input 56 4.12 Output response of an integrator implemented with the operational amplifier 57 4.13 Output response of a differentiator implemented with the operational amplifier 57 5.1 Layout of the experimental chip 64 5.2 Die photo of the experimental chip 65 5.3 Measured current-voltage characteristics of N-type Super-MOST 66 5.4 Measured current-voltage characteristics of P-type Super-MOST 66 vu 5.5 Input and output waveforms of the operational amplifier for (a) frequency of 2 kHz, and (b) frequency of 200 kHz 67 5.6 Input and output waveforms for frequency varied sinusoidal signal in the range of (a) hundred-ldlo-Hz, and (b) mega-Hz 68 vm CHAPTER I INTRODUCTION 1.1 Motivation CMOS technologies have rapidly improved over the past few years. To date, the size of transistor is shrunk to sub-micron and fabrication processes attain finesse, resulting in dramatic increases in the speed and density of integrated circuit devices. The result of this trend is the system on a chip, in which aU circuitry wiU be housed within a couple of square centimeter of die area, in particular for a large digital system. Compared with their analog counterparts, digital circuits are less susceptible to noise and more endurance to the supply and process variations, and allow easier design and test automation. These facts contribute to more digital circuits and less analog circuits being integrated within a chip. However, since naturally occurring signals are analog, in order to perform any digital signal processing (DSP), data conversion system is needed to digitize the signal at the input and reproduce the signal at the output. For example, applications such as high definition television (HDTV), compact disc players, CD ROM, and modems, as well as special systems such as medical imaging, speech processing, and radar employ data conversion systems for interfacing. As the demand for these high performance appUcations increases, the design of data conversion system becomes increasingly difficult. This is because a high speed and high accuracy analog circuit is not easy to attain, and tradeoff often has to be made. Furthermore, in the mixed signal system, analog portions 1 are susceptible to the coupling noise via power supply, substrate current and crosstalk of adjacent line during digital switching. As a result, mixed signal system designs become a challenging problem. In most of the data conversion systems, such as switched capacitor circuits [1], sigma-delta converters [2], pipeline A/D converters [3], [4], algorithmic A/D converters [5], [6], and sample-and-hold amplifiers [7], [8], operational ampUfiers form the basic building block. High gain and high unity gain frequency amplifiers are needed to meet the requirements for high performance systems. Satisfying both of these requirements, however, is difficult to achieve since high unity gain frequency calls for short channel devices which has low intrinsic gain. Therefore, gain enhancement techniques are necessary for designing a high gain and high unity gain frequency operational amplifier. This thesis investigates the gain boosting technique proposed by K.Bult and G. Geelen [9]. An improved cascode circuit that combines both high gain and high speed is developed. Using this cascode circuit, a high performance fully differential operational amplifier is designed. A prototype of the cascode circuit and operational ampUfier was fabricated in a 2 |im n-well CMOS technology. Simulation results indicate that the cascode circuit has at least 100 MQ output impedance, while the amplifier has an open loop gain of 98 dB and a unity gain frequency of 17 MHz for 10 pF load capacitor. 1.2 Structure of Thesis This thesis is outlined as follows. Chapter n analyzes a differential amplifier, which is the building block for an operational amplifier. Various operational amplifier topologies are also examined with emphasis on the speed and gain analysis. Some previous works are studied and their performance limitations are discussed. In chapter in, the problems associated with the conventional cascode circuits are identified and an improved version of cascode circuit, which is called Super-MOST, is introduced. Also presented is the principle and operation of the Super-MOST. Two previous designs using this principle are then described along with their drawbacks. A new topology is proposed that has superior performance over the two previous design. Chapter IV describes the design of the fuUy differential operational amplifier. The reasons of choosing the topology are explained. Also, a common mode feedback stage is presented that is employed to control the output bias point. Chapter V shows the experimental results from a prototype chip which includes the Super-MOST and the operational amplifier. In chapter VI, the summary of this research and the suggestions for future work are presented. CHAPTER II OPERATIONAL AMPLIHER DESIGN REVIEW This chapter presents an overview of some of previous CMOS operational amplifier configurations, but stand alone designs are not addressed. Since this research is focused on designing an operational amplifier that can be used as a building block for analog signal processing system, the primary emphasis in this chapter is placed on the factors affecting the gain and speed of an operational amplifier.