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CMOS Operational Amplifiers 5. CMOS Operational Amplifiers Analog Design for CMOS VLSI Systems Franco Maloberti Basic op-amp The ideal operational amplifier is a voltage controlled voltage source with infinite gain, infinite input impedance and zero output impedance. The op-amp is always used in feedback configuration. Analog Design for CMOS VLSI Systems 5. CMOS Operational Amplifiers Franco Maloberti 1 Typical feedback configuration Z4 Z1 + Z2 Z2 V0 = V2 V1 Z3 + Z4 Z1 Z1 Finite gain effect: Z4 Z1 + Z2 Z2 Z1 + Z2 V0 = V 2 V1 1 + Z + Z Z Z A Z 3 4 1 1 0 1 The error due to the finite gain is proportional to 1 / A0. This error must be smaller than the error due to impedance mismatch. Analog Design for CMOS VLSI Systems 5. CMOS Operational Amplifiers Franco Maloberti 2 OTA If impedances are implemented with capacitors and switches, after a transient, the load of the op-amp is made of pure capacitors. The behavior of the circuit does not depend on the output resistance of the op-amp and stages with high output resistance (operational transconductance amplifiers) can be used. Analog Design for CMOS VLSI Systems 5. CMOS Operational Amplifiers Franco Maloberti 3 Transient C V (0+ ) = V 1 i in C + C // C 1 0 + + C Vo (0 ) = Vi (0 ) C0 + C C + C V () = V 1 i in C C(1 g r ) 1 + + m 0 V o () = Vi () gm r0 C 0 g m Analog Design for CMOS VLSI Systems 5. CMOS Operational Amplifiers Franco Maloberti 4 Performance characteristics Actual op-amps deviate from the ideal behavior. The differences are described by the performance characteristics. DC differential gain: It is the open-loop voltage gain measured at DC with a small differential input signal. Typically Ad = 80 ÷ 100 dB. Analog Design for CMOS VLSI Systems 5. CMOS Operational Amplifiers Franco Maloberti 5 Common mode gain: It is the open-loop voltage gain with a small signal applied to both the input terminals. Acm = 20 ÷ 40 dB. Common mode rejection ratio: It is defined as the ratio between the differential gain and the common mode gain. Typically CMRR = 40 ÷ 80 dB. Analog Design for CMOS VLSI Systems 5. CMOS Operational Amplifiers Franco Maloberti 6 Power supply rejection ratio: If a small signal is applied in series with the positive (or negative) power supply, it is transferred to the output with a given gain Aps+ (or Aps-). The ratios between differential gain and power supply gains furnish the two PSRRs. Typically: PSRR = 90 dB (DC) PSRR = 60 dB (1 kHz) PSRR = 30 dB (100 kHz) Analog Design for CMOS VLSI Systems 5. CMOS Operational Amplifiers Franco Maloberti 7 Input offset voltage: In real circuits if the two input terminals are set at the same voltage the output saturates close to VDD or to VSS. Typically |Vos| = 4 ÷ 6 mV. Input common mode range: It is the maximum range of the common-mode input voltage which do not produce a significant variation of the differential gain. Analog Design for CMOS VLSI Systems 5. CMOS Operational Amplifiers Franco Maloberti 8 Output voltage swing: It is the swing of the output node without generating a defined amount of harmonic distortion. Equivalent input noise: The noise performances can be described in terms of an equivalent voltage source at the input of the op-amp. Typically vn = 40 ÷ 50 nV/Hz at 1 kHz, in a wide band (1 MHz) it results 10 ÷ 50 V RMS. Analog Design for CMOS VLSI Systems 5. CMOS Operational Amplifiers Franco Maloberti 9 Unity gain frequency: It is the frequency where the open-loop gain is zero. It is also the -3 dB bandwidth in unity-gain closed loop conditions. Typically fT = 200 MHz. Phase margin: It is the phase shift of the small-signal differential gain measured at the unity gain frequency. A phase margin smaller than 60° causes ringing in the output response. Analog Design for CMOS VLSI Systems 5. CMOS Operational Amplifiers Franco Maloberti 10 Slew rate: It is the maximum slope of the output voltage. Usually it is measured in the buffer configuration. The positive slew rate can be different from the negative slew rate. Typically SR = 50 ÷ 200 V/s (lower values for micropower operation). Settling time: The settling time is the time required to settle the output within a given range (usually ± 0.1%) of the final value. Power dissipation: It depends on speed and bandwidth requirements. Typically, for 3.3 V supply, it is around 1 mW. Analog Design for CMOS VLSI Systems 5. CMOS Operational Amplifiers Franco Maloberti 11 Typical parameters of a 0.25 m OTA Feature Value Unit DC gain 80 dB CMRR 40 dB Offset 4-6 mV Bandwidth 100 MHz Slew-rate 3 V/s Settling time: 1 V, CL = 4 pF 300 ns PSRR @ DC 90 dB PSRR @ 1 kHz 60 dB PSRR @ 100 kHz 30 dB Input referred noise (white) 100 nV/Hz Corner frequency 1 kHz Supply voltage 3.3 V Input common mode voltage 1.5 V Output dynamic range 2.2 Vpp Power consumption 1 mW Silicon area 2000 m2 Analog Design for CMOS VLSI Systems 5. CMOS Operational Amplifiers Franco Maloberti 12 Basic architecture 1st gain stage differential to single-ended converter 2nd gain stage output stage (to reduce the output impedance) Key requirements: absolute stability in unity gain closed-loop conditions when driving maximum load. minimum number of gain stages. Analog Design for CMOS VLSI Systems 5. CMOS Operational Amplifiers Franco Maloberti 13 Two-stage op-amp Key design issues: open-loop differential gain dc offset power supply rejection (PSRR) Analog Design for CMOS VLSI Systems 5. CMOS Operational Amplifiers Franco Maloberti 14 Open-loop differential gain: The gain is obtained by multiplying the gains of the two stages. gm1 gm5 Av = A1A2 = = (gds2 + gds4 ) (gds5 + gds6 ) W W W L L L 22µnµp Cox 1 5 B 1 = 2 (n + p ) W W IBias L L 6 7 At low frequency the gain is inversely proportional to the bias current. Analog Design for CMOS VLSI Systems 5. CMOS Operational Amplifiers Franco Maloberti 15 Common mode dc gain: Applying the same signal to both inputs the circuit becomes symmetrical and can be studied considering half circuit. gds7 gm5 ACM = ACM1ACM2 = 2g g g m1 ds5 + ds6 A 2g g CMRR = v = m1 m3 A g (g + g ) CM ds7 ds2 ds 4 Analog Design for CMOS VLSI Systems 5. CMOS Operational Amplifiers Franco Maloberti 16 Offset: The offset is composed of two terms: systematic offset random offset The systematic offset can be reduced to zero with a careful design. A necessary condition to have zero systematic offset, is that the currents of M5 and M6 are equal, when the inputs are connected to the same voltage. Assuming all the transistors in saturation this condition is: ()WL ()WL ()WL I 6 = I 7 5 Bias WL Bias WL WL ()B ()B ()3 1 WL WL = WL WL ()3 ()6 ()7 ()5 2 Analog Design for CMOS VLSI Systems 5. CMOS Operational Amplifiers Franco Maloberti 17 The random offset is due to the geometrical mismatching and process dependent inaccuracies. When we refer the offset of the second stage at the input terminal we have to divide it by the gain of the first stage. Since the two offsets are uncorrelated we have: 2 2 Vos2 Vos = Vos1 + A 1 The total offset is dominated by the offset of the input stage. Analog Design for CMOS VLSI Systems 5. CMOS Operational Amplifiers Franco Maloberti 18 We study the effect of a mismatch between M3 and M4: mirror factor (1 + ) instead of 1. I V I V I Bias g os1 1 Bias g os1 V 1 m1 () + = + m2 os1 2 2 2 2 gm1 Analog Design for CMOS VLSI Systems 5. CMOS Operational Amplifiers Franco Maloberti 19 MOS: I V V 1 = GS1 Th = 150 ÷ 300 mV (in saturation) g 2 m1 I1 nkT = nVT = (in sub-threshold) g m1 q BJT: I 1 26 mV g m1 Assuming = 0.01: Vos,BJT = 0.26 mV Vos,MOS = 1.5 ÷ 3 mV Analog Design for CMOS VLSI Systems 5. CMOS Operational Amplifiers Franco Maloberti 20 Power supply rejection: A signal on the positive bias line determines a modulation in the reference current, which, in turn, gives an equal modulation of the currents in M5 and M6, if the condition of the zero systematic offset is fulfilled. Analog Design for CMOS VLSI Systems 5. CMOS Operational Amplifiers Franco Maloberti 21 + The spur signal v n affects the currents of M5 and M6. i i n,6 = n,7 = µC V V v + W / L W / L ox ()GS,MB Th n () 6 ()7 a) low frequency: + W / L 1 W / L W / L 1 ()6 ()5 ()7 vo,n,1 = in,tot W / L 2 W / L W / L gds6 + gds7 ()B ()4 ()B b) high frequency: W / L ()6 1 vo,n,1 = in,Ref W / L gm5 ()B Analog Design for CMOS VLSI Systems 5. CMOS Operational Amplifiers Franco Maloberti 22 Power supply rejection at low frequency gm5 (1 k+ ) gm5k gds6 gds6 2 2g r 2 2g r 2 v m3 ds3 v + m3 ds3 v ()o,tot = ()n + ()n gds5 + gds6 gds5 + gds6 Analog Design for CMOS VLSI Systems 5. CMOS Operational Amplifiers Franco Maloberti 23 Effect of external components on PSRR Analog Design for CMOS VLSI Systems 5. CMOS Operational Amplifiers Franco Maloberti 24 Frequency response and compensation A two-stage scheme with poles in the same frequency range needs compensation. A single pole system is always stable.
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