The Semiconductor Industry's Nanoelectronics Research Initiative
The Semiconductor Industry’s Nanoelectronics Research Initiative
Dr. Jeff Welser Director, Nanoelectronics Research Initiative [email protected] Semiconductor Research Corporation: Collaboratively Sponsored University Research
Strong university research is critical for continuing rapid pace of technology Research in new concepts, breakthrough ideas and solutions to problems for which no currently known solutions exist Development of talent pool of scientists and engineers The Semiconductor Industry Association (SIA) members have recognized that collaboration among industry, government and academia is the most efficient means of advancing university research capabilities Semiconductor Research Corporation (SRC) has been established as one of the key initiatives to facilitate collaboratively sponsored university research SRC manages a full spectrum of research related to CMOS and beyond CMOS technologies under various program entities 2 SRC Global Research Collaboration
ducation EEAAlliance
Pre-competitive Pre-competitive Post Longer Range Education Research CMOS Research
GRC – Global Research Collaboration FCRP – Focus Center Research Program NRI – Nanoelectronics Research Initiative
EA – Education Alliance 3 SRC: Research Program Differentiators
SRC-GRC SRC-FCRP SRC-NRI
Nature of Narrowing Creating Options Next Information Research options Element
Technology CMOS and Scaling CMOS + Hooks to Beyond CMOS Spectrum Independent beyond CMOS Research Industry Strategic and in High level Influence through Involvement execution strategic highly leveraged co-investment Government Limited; leverage Significant Major funding – Involvement funding funding; 50:50 State and federal with DOD University Limited Significant Significant Autonomy
Membership Global U. S. only U. S. only 4 High Performance Silicon-On- Insulator CMOS
Gate
Source Drain
5 Moore’s Law
Electronics, Volume 38, Number 8, April 19, 1965 Per Integrate Function Per Integrate Log of the Number of Components Log of the Number
Year 6 1000 $ Buys
1E+121E+12 Mechanical Vacuum tube Integrated circuit Electro-mechanical Discrete transistor 1E+9
1E+6
1E+31E+3
Computations/sec 1E+0 Computations/sec 1E-3
1E-61E-6 19001900 1920 19401950 1960 1980 2000 2000 2020 YearYear
7 Scaling = Progress in Electronics
Smaller features Æ Better performance & cost/function Æ More apps Æ Larger market 8 CMOS Power Issue: Active vs. Passive Power
1000 Power components: Air Cooling limit )
Active power 2 100 Active Passive power Power 10 Gate leakage Passive Power Source - Drain leakage 1
0.1
Gate Leakage Power Density (W/cm 0.01 1994 2005 0.001 1 0.1 0.01 G Polysilicon10S Tox=11A Gate G GateGate Length Length (microns) (microns)
SS DD
Gate Oxide Silicon (SOI)
9 Has This Ever Happened Before?
14 CMOS
12 Bipolar ) 2 10
8
6
4 Start of Water Cooling 2 ? Module Heat Flux(watts/cm
0 1950 1960 1970 1980 1990 2000 2010 Year of Announcement 2005 ~ 2015: New utilization of technology > 2015?: New technology 10 Moore’s Law: Transistors per chip
What is the ultimate number of binary transitions per second in a 1cm2 chip area? - a measure of computational BIT = nbit f capability on device level
nbit – the number of binary states f – switching frequency ) Why scaling? – To 2 1.00E+21 1.00E+20 increase the Binary 1.00E+19 Information Throughput 1.00E+18 (BIT) 1.00E+17 BIT (bits/s/cm BIT 1.00E+16 2000 2005 2010 2015 2020 Year 11 Key Systems Transitions
Bipolar CMOS CMOS SoC Frequency Frequency & density Integration & density
CPU 1
L2 Cache
Cost CPU 2 Cost Power Power
Multi-Chip Module Blue Gene L Power 5 Multi-core microprocessor, (MCM) ASIC library, design tools
1980’s 1990’s – 2000’s 2004 & Beyond
(Note: Figures not to scale) 12 Cell Processor
~250M transistors ~235mm2 Top frequency >4GHz 9 cores, 10 threads > 256 GFlops (SP) @4GHz > 26 GFlops (DP) @4GHz Up to 25.6GB/s memory B/W Up to 75 GB/s I/O B/W Large design investment (time & money)
13 Heterogeneous Multi-Core Architectures
A possible ultimate evolution of on-chip architectures is Asynchronous Heterogeneous Multi-Core with Flexible Processors Organization
• General-purpose CMOS CPU MF(n) – application-specific processor • Several application-specific implementing a specific macro-function processors/systems (may need specialized devices) • May be CMOS hybrids and/or • Operate in multiple physical domain MF1 MF2 MF3 MF4
MF12 MF5 General Key Challenge: Software Purpose Processor MF11 MF6
MF10 MF9 MF8 MF7 14 What about a New Device? )) D
Molecular devices S < kT/q Drain Current (log(I Current Drain
Gate Voltage (VGS) Technology must be “additive”
Spintronics Fine-grain PLA
top-gate channel
channel back-gate isolation buried oxide 3D, heterogeneous Quantum Nanotube cascade Double-Gate / FinFET integration Gate Nanowire
Source Drain Embedded memory Time 15 2005 ITRS Risk Assessment of Potential Future Memory Devices
16 2005 ITRS Risk Assessment of Potential Future Logic Devices
17 For a new technology, it must either . . .
Reduce power density Smaller size, more current alone don’t help Better sub-Vt slope, better Ion/Ioff, lower leakage do Control variability Dopant placement, gate length variation, S0I / oxide thickness variation Reduce parasitics Capacitance, resistance New wiring would be great! Offer potential for continued scaling (Change atomic size limits, elementary charge value, speed of light, etc.) . . . Or it doesn’t solve the problem!
18 What is Information?
Source: IBM
Information is measure of distinguishability manifested in physical form Particle Location is an Indicator of State
1100 10
20 Two-well bit
a Eb
a Eb
w w
21 Electronic switches can be of different nature, but they all have similar fundamentals
MVM
p
n n
22 Basic Equations of Two-well Bit
What are the requirements/limitations on the height and width the barrier? E a b
⎛ E ⎞ ⎜ b ⎟ Π B = exp⎜− ⎟ ⎝ k BT ⎠
on ∆x∆p ≥ h n nd y d o ou erg 2 un r b n o e n e r b e ow tio we iz L ra h Lo e s pe ∆E∆t ≥ vic o 2 de “Boltzmann constraint” on “Heisenberg constraints” minimum barrier height on minimum barrier width23 Classic Distinguishability: The Boltzmann constraint How small could the energy barrier height be ? Barrier control (gate)
a Eb Eb OR a Eb min E Π = exp( b ) E = E error bit b kBT E Distinguishability requirement: The 0.5 = exp(− b ) Energy to probability of spontaneous kBT “deform” the transitions(errors) Πerror<0.5 (50%) barrier min Eb = kBT ln 2 24 Size and Time: The Heisenberg Constraint
At this size, tunneling will destroy the state ∆x∆p ≥ h a ~ h crit 2mE ∆E∆t ≥ h b h Eb=kTln2 tmin ~ Eb Minimal time of dynamical evolution of a physical system N. Margolus and L. B. Levitin, Physica D 120 (1998) 188
25 Summarizing, what we have learned so far from fundamental physics 1) Minimum energy per binary transition E min = k T ln 2 Boltzmann bit B 2) Minimum distance between two distinguishable states h ∆x∆p ≥ xmin = a = =1.5nm(300K) h Heisenberg 2mkT ln 2 3) Minimum state switching time t = h = 4×10−14 s(300K) ∆E∆t ≥ h Heisenberg st kT ln 2
1 gate 4) Maximum gate density 13 n = 2 = 4.6×10 2 xmin cm 26 Total Power Dissipation - A Catastrophe!
(@Ebit= kTln(2)) n⋅ E 3⋅10−21[J ] P = bit = 4.6⋅1013[cm−2 ]⋅ chip t 4⋅10−14[s] −21 Ebit = kBT ln 2 ≈ 3⋅10 J
W P = 4.74×106 T=300 K chip cm2
The circuit would vaporize when it is turned on!
27 Implications for Nanoelectronics Circuits
Circuit heat generation is the main limiting factor for scaling of device speed and switch circuit density
Scaling to molecular dimensions may not yield performance increases We will be forced to trade-off between speed and density Optimal dimensions for electronic switches should range between 5 and 50 nm Likely achievable with Si – easily within the scope of ITRS projections Going to other materials for FETs will likely achieve only “one-time” percentage gains Need a new device mechanism or computational architecture for new scaling path
28 2005 ITRS Taxonomy for Processing
29 NRI Mission Statement
NRI Mission: Demonstrate novel computing devices capable of replacing the CMOS FET as a logic switch in the 2020 timeframe. These devices should show significant advantage over ultimate FETs in power, performance, density, and/or cost to enable the semiconductor industry to extend the historical cost and performance trends for information technology. To meet these goals, NRI is focused primarily on research on devices utilizing new computational state variables beyond electronic charge. In addition, NRI is interested in new interconnect technologies and novel circuits and architectures, including non- equilibrium systems, for exploiting these devices, as well as improved nanoscale thermal management and novel materials and fabrication methods for these structures and circuits. Finally, it is desirable that these technologies be capable of integrating with CMOS, to allow exploitation of their potentially complementary functionality in heterogeneous systems and to enable a smooth transition to a new scaling path.
30 Five Research Vectors Computational State Vector other than Electronic Charge (e.g. “bits” represented by spins) ¾ New scaling path Non-equilibrium Systems ¾ Lower power, less heat Novel Data Transfer Mechanisms ¾ Overcome RC limits Nanoscale Thermal Management ¾ Cooler operation, manage power density Directed Self-assembly of such structures ¾ Less variability, higher density, more reliable, lower cost
¾Strong Focus in NRI on the first Research Vector
31 NRI Milestones
March 2004: SIA White Paper on Post-CMOS presented to SIA Board SIA Board Resolution for formation of NRI
March 2005: Six Companies sign NRI Participation Agreement • AMD, Freescale, IBM, Intel, Micron, TI NERC incorporated to manage NRI Governing Council (GC) and Technical Programs Group (TPG) formed with one representative per participating company • Advisors from NIST, NSF, and DARPA
September 2005: NRI and NSF Solicitations released December 2005: NSF and NRI Awards announced January 1, 2006: Research Programs started
November 16-17, 2006: First Annual NRI Review in San Francisco, CA 32 NRI Sponsored Nanoelectronics Research Institutes
•NRI Mission: Demonstrate novel computing devices to enable the semiconductor industry to extend Moore's Law beyond the limits of CMOS •Leverage industry, university, and both state & fed government funds, and use to drive university fabrication infrastructure
WIN INDEX SWAN NSF NSEC Western Institute of Institute for SouthWest Academy for & MRSEC Nanoelectronics Nanoelectronics Nanoelectronics Supplemental Discovery & Exploration Funding UCLA, UCSB, Berkeley, Albany, GIT, Harvard, MIT, UT-Austin, UT-Dallas, TX Various schools Stanford Purdue, RPI, Yale A&M, Rice, ASU, Notre –funding ~6 Dame, U of MD centers per year Theme 1: Spin devices Task I: Novel state-variable Task 1: Logic devices with Broad work on Theme 2: Spin circuits devices new state-variables various topics – Theme 3: Benchmarks Task II: Fab & Self- Task 2: Materials & structs also leverages & metrics assembly Task 3: Self-assembly & other work in Task III: Modeling & Arch thermal mgmt the centers Task 4: Interconnect & Arch Task IV: Theory & Sim Task 5: Nanoscale Task V: Roadmap characterization 33 NRI Funded INSTITUTE FOR NANOELECTRONICS DISCOVERY AND EXPLORATION Universities SWAN
Notre Dame SUNY Albany RPI Columbia Purdue U Mass MIT Harvard Yale UC Berkeley U of MD U of Virginia Stanford UC Santa Barbara
UC Los Angeles GIT
INDEX Rice U of Arkansas SWAN Arizona State TX A&M U of Oklahoma WIN UT Dallas NSF-NRI UT Austin 34 SWAN Novel Transistor Research
Non-Dissipative Spin Hall Effect Response
Dramatic Change Pseudospintronics in Current Voltage Relationship Task 1: SPIN Novel Devices Dilute Magnetic Spin-Momentum Semiconductors Transfer
Exchange Interactions for Quantum Point Logic Task 2: Contacts Novel Spin Manipulation Materials for Computation GOAL: MOTIVATION: and Logic Quantum Wires Fundamentally New PHASE Finding New Device Concepts, Logic Switch Task 3: Implementations, and New Tools Novel Transfer Characterization Quantum Wire Techniques for Transistors Devices
Device-Device Magnetic Interaction for Task 4: Nanoparticles Quantum Logic Novel Gates Interconnect
CHARGE Thin Film / FIB Reduced Characterization Interactions for Near Ballistic Key Challenge: Response Task 5: Novel Nanophotonic “Nano-Metrology” Metrology Waveguides Interaction Induced Switching and characterization
Nanomagnets Tunneling Enhanced Switching 35 2005 ITRS Energy / Cost / Area / Delay
36 Summary
Power will continue to be the principal concerns facing the semiconductor industry CMOS will continue to scale and improve over at least the next decade, with emphasis on utilizing increasing transistor density over increasing frequency
Any new device / technology to replace CMOS must overcome the power / performance limits of a charge-based FET, and enable a new scaling path for the industry
NRI is specifically focused on finding a new logic device to scale beyond CMOS in 2015-2020 Three main centers and joint work at several NSF centers already under way – will continue to expand Continuing to be interested in additional novel devices and state variables (beyond spin)
37