The Challenges and Opportunities of Nanoelectronics

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The Challenges and Opportunities of Nanoelectronics Seth Copen Goldstein School of Computer Science, Carnegie Mellon University, Pittsburgh, PA 412-268-3828 / [email protected]

Abstract controls a deeply pipelined datapath which has many function units. Intermediate values are stored in a register file while a Nanoelectronics presents the opportunity of incorporating bil- single main memory is used to store programs and data. The lions of devices into a single system. Its opportunity is also its success of this model is that it is easy to think about and pro- challenge: the economic design, verification, manufacturing, gram. However, we need to rethink this model if we are to and testing of billion component systems. In this presentation efficiently harness the vast number of devices, limit the effect I will explore how the abstractions used in computer systems of increased wire delay, control design complexity, decrease change as we approach nanoscale dimensions. the power required, and control the cost of manufacturing.

1. INTRODUCTION 2. FABRICATION Future computing systems will inevitably be built using nano- Perhaps the greatest impact of the nanoscale on electron- electronics, i.e., from devices and wires with feature sizes be- ics will be the reduced ability to arbitrarily determine the low thirty nanometers. The SIA roadmap [15] predicts that tra- placement of the components of a system. The most extreme ditional silicon-based systems will have feature sizes of below example of this is to be found in chemically assembled 40nm within the decade. There are also advances being made electronic nanotechnology (CAEN), a form of molecular elec- in building computing systems using new technologies, such tronics which uses bottom-up assembly to construct electronic as molecular electronics [2]. Successfully harnessing nano- circuits out of nanometer-scale devices. Large-scale molecular electronics requires a rethinking of the abstractions and mod- electronics requires some form of self-assembly [2]. When els that are the basis of designing computing systems. While using self-assembly, individual devices and wires are ﬁrst each technology has its own unique requirements, we show manufactured, and only later assembled into a circuit. While that new abstractions are necessary strictly because the feature self-assembly promises to be a very economical process (com- sizes are nanoscale. pared with the cost of traditional semiconductor fabrication), The ever increasing improvement in processor performance it cannot be used to create the arbitrary patterns that can be is fueled by the ever increasing number of available faster tran- formed using photolithography. Only simple, crystal-like

sistors, but it is driven by a hierarchy of abstractions. One structures, can be created using self-assembly. Furthermore,

plausible hierarchy is: Transistors Logical Gates Circuits defect densities of self-assembled circuits are projected to

Blocks ISA Programs. Each abstraction layer hides the be orders of magnitude higher then in silicon-based devices. details of the layer below it; helping to control the complex- Thus, self-assembled circuits and architectures will have to be ity of designing and implementing a systems with hundreds designed for defect tolerance. of millions of components. They also promote a separation To a lesser extent these same problems will appear as tradi- of responsibilities; allowing independent progress to be made tional semiconductor technology continues to scale. The com- at different levels of the system. In this paper we examine plexity of generating a reliable mask set which produces re- how current trends in semiconductor manufacturing as well liable chips is already limiting the ability to create arbitrary as how new technologies, e.g., molecular electronics and self- patterns of wires. This can be seen in the trend towards “struc- assembly will influence the hierarchy of abstractions used to tured” ASICs, which allow custom chips to share many of the build computing systems. same masks [18]. As devices scale down it is also harder From the circuit designers perspective the hierarchy begins to maintain constant characteristics for all the devices on a with transistors and works it way through logical gates to func- single chip [11]. Some argue that process variation will es- tional blocks. Computer architects use the functional blocks sentially eliminate the performance gains typically expected created by circuit designers to create an instruction set archi- when feature sizes shrink [1]. These trends indicate that as tecture (ISA). The ISA is the abstraction used to define the feature sizes shrink even photolithographically manufactured processor to programmers. The architect implements the ISA chips will need to be crystal-like, i.e., built from very regular by combining control, storage, and datapaths. Most of today’s structures. processors are organized as von Nuemann computers: they In order to implement useful reliable functionality on top have a single point of control (one program counter) which of crystal-like structures, post-fabrication customization is required; this customization will be used for two purposes (1) which uses the transistor to construct logical blocks. In static to implement the desired functionality and (2) to eliminate the CMOS, the inputs to a logical block are always applied to the deleterious effects of the defects [4, 6]. Economics will speed gate of the transistor, which is isolated from its other two ter- the movement towards customizable chips. As mask sets be- minals. Furthermore, a small change on the gate can cause a come more expensive it becomes more economical to reuse the large change on the output due to the connections to power and same chip for different tasks, i.e., to use programmable hard- ground. There are other transistor-based design methodolo- ware (also called a reconfigurable fabric) such as field pro- gies, such as complementary pass logic (CPL) [13], in which grammable gate arrays (FPGAs). A reconfigurable fabric is a the inputs and outputs of a logical block are not isolated. Fur- network of processing elements connected by a programmable thermore, there is signal loss—instead of power gain—and, interconnect [7]. It can be programmed by determining how there is no way to invert a signal, so whenever a function is signals are routed on the interconnect. The desire to decrease computed its complement must also be computed. 1. Large time-to-market is also accelerating the trend towards using FP- scale CPL circuits require periodic buffers which restore sig- GAs for ever higher volume applications. nals and provide isolation; allowing individual subsystems to Defects in manufacturing have been, until now, primarily be composed together to form larger systems. the concern of process engineers, not circuit designers or ar- Some of the proposed logic families for non-silicon nano- chitects. In the era of nanoelectronics, delivering chips which electronics are similar to CPL in that gain and isolation are can be viewed as defect free will likely be too expensive. In not intrinsic in every circuit element. QCAs are an exam- fact, this is happening already; for example, state-of-the-art ple of such a system. Designers of QCA based circuits in- FPGA chips with known defects can be purchased at a dis- clude a system clock which helps to isolate inputs from out- count [19]. The defective chips can be used because the de- puts as well as add gain to the system [12]. A more traditional fects on the particular chip are determined not to affect the cus- approach is found in nanoFabrics [6] which proposes to use tomer’s design. In the future, defect tolerance will have to be diode-resister logic combined with clocked molecular latches designed in at the circuit and architectural level. One method is for gain and isolation. What these systems (CPL, clocked- to use reconfigurable fabrics. Reconfiguration provides defect QCA, and NanoFabrics) share in common is they provide log- tolerance by configuring the desired circuit around the defects, ical switching separately from isolation and restoration. In or- thus creating a reliable system from an unreliable substrate. der to manage this extra design dimension we propose a new Before the fabric is shipped its defects are mapped [9]. When model, SirM. SirM stands for switching, isolation, restoration, the chip is used, the desired circuit is configured around the de- and Memory. We call a set of devices a complete SirM fam- fects. The main challenge here is to develop architectures and ily if it contains devices which support all the components of tools which can—in the field—quickly place-and-route (P&R) SirM, and therefore, can be used to construct a scalable com- circuits around the defects. Final P&R needs to be done in the plete logic family. field so that a single configuration can be shipped for all de- An example of a complete SirM family in the domain of vices, in spite of the fact that each device will have a different molecular computing is: set of defects.

¯ Switching is based on diode-resistor logic using resistors and molecular diodes. As with CPL, functions and their 3. DEVICES complements must be constructed since it is impossible to construct an inverter out of just diodes and resistors. Nanoelectronic devices, and here we also include wires, pose

their own challenges. The transistor has thus far proven an ¯ Isolation comes from a molecular latch combined with a extremely useful building block for digital logic. In addition clocking methodology as described in [14]. to its switching properties, it can be used to construct logical

¯ Restoration gates which isolate their inputs from their outputs (I/O iso- occurs through the use of the above latch. lation) and it has gain which promotes noise immunity [8]. ¯ Memory can be constructed either directly from Some nanoelectronic technologies have no equivalent device. molecules (e.g., the rotaxane [10]) or from the latch. In addition, as dimensions scale down, the wires used to con- nect the devices become the dominant source of signal delay SirM is an example of the easiest kind of change to the ab- and power consumption [15]. straction hierarchy. It can be thought of as a new layer be- Isolation and gain, while not a sine qua non for construct- tween the new physical devices and today’s abstraction of a ing large scale digital systems, is required if one is going to transistor. In other words, a “transistor” like contract can be build a large system from smaller subunits ones without hav- established by combining the proper switch, isolator, and re- ing to redesign the subunits. We should point out that isolation storer devices all together. Therefore, we are able to main- and gain are not strictly a property of the device, but usually tain the current abstraction, providing backward compatibility arises from the device and the design methodology being em- 1If the complements of all the inputs are available it is always possible, by ployed. For example, static CMOS is a design methodology Demorgan’s Law, to compute the function and its complement. of long communication times. This has been done while Vin Rin Rout maintaining the abstraction of a single thread of control, gmVin i.e., programs are specified in a sequential language. These improvements have been enabled by technology scaling: Figure 1: The Norton equivalent circuit for one circuit block smaller devices run at faster speeds and increase the total amount of resources available. The internal structure of a modern processor, is designed to exploit as much parallelism gm1Vin1 gm2Vin2 as possible within the sequential stream of instructions being Vout2 Rin1 executed. All of the improvements have come at the cost Vin1 Rin2 Rout2 Rout1 of increased power consumption and increased complexity. Furthermore, technology trends (e.g., longer wire delays, faster clocks, and, increased power densities) are already Figure 2: The equivalent circuit for cascaded circuit blocks limiting the continued application of current techniques. Nanoelectronics will exacerbate all of these trends as well as increase the rate of transient faults. for tools and ideas while providing the opportunity to pierce The level of integration available with nanoelectronics sug- the transistor abstraction when necessary. This provides the gests a radically different approach: Implement programs di- design community with an incremental path towards harness- rectly in hardware. This approach forces one to abandon two ing the underlying devices directly. Furthermore, it does not important abstractions: the instruction set architecture (ISA) change any of the contracts with other layers in the hierarchy. and sequential control. The ISA is the primary abstraction However, if isolation is separate from switches—which is used by computer architects to hide the internal structure of currently the case for all two-terminal device families—then the processor. It defines a fixed set of instructions which de- some local analog design is necessary when constructing net- termine how the processor is used by the programmer (or a works of switches. Any two-terminal voltage controlled circuit compiler). The main advantage of an ISA is that it allows a to be modeled from its input and output impedances and its programmer to write down a sequential list of instructions to gain. For example, Figure 1, shows a model of a two-terminal

deﬁne a program. With the advent of sophisticated tools, such Ê device. The gain of this device is . If two of these m out as optimizing compilers, the necessity for writing down such

devices are placed in series, as in Figure 2, then the gain of

Ê Ê Î a low level description of a program becomes less important.

out2 out1 in2

the total circuit is

Ê ·Ê Î More importantly, the ISA—almost by deﬁnition— impedes in1 m1 out1 in2 m2 out2

½ the ability to fully exploit the microarchitecture.

. We can see that if the input, e.g., ,

Ê Ê 1 ½· 2 in2 out1 in2 We suggest that compiling directly to the hardware will does not have infinite input impedances, i.e., it does not pro- open up opportunities for creating custom compute engines vide isolation, then the gain of a device depends on the struc- tailored directly to the application of interest. The compiler ture of the circuit. The variation in an individual device’s char- will create a configuration for a reconfigurable fabric. This acteristics is even more pronounced if the circuit has fan-in or model, often called spatial computing, is more suited for the fan-out. In fact, every possible path in a circuit needs to be regime of nanoelectronics since it directly supports many lev- analyzed in order to determine when a restorer should be in- els of parallelism. It can essentially create a custom datapath serted into the circuit. CPL, when combined with static CMOS for the application under execution. Of course, it would be buffers (or inverters) is an example of a complete SirM family nearly impossible to program by hand, and relies heavily on which requires such analysis [20]. compiler technology and CAD tools. All the methods of isolation that we are aware of include either transistors or a clocking strategy. An important chal- Tailoring the hardware directly to the program, e.g., spatial lenge for the nanotechnologists in the molecular computing computing, has the potential to overcome the negative effects community is to develop a design methodology and an associ- of scaling. By eliminating the ISA and allowing tools, such as ated two-terminal device which isolates its inputs from its out- compilers, to manipulate the underlying hardware structures puts without requiring a clock. Additionally, whatever strategy directly one can optimize not only for time, but also for other is employed should not require global analysis in order to un- important metrics in the nanoelectronics design space, e.g., de- derstand the behavior of a local structure. In other words, the fect/fault tolerance or power. Let us look at lowering power

dissipation. Dynamic power (È ) is a function of capacitance

input to a gate should have a very large impedance, e.g., Ê in2

Î «

in Figure 2 should be as close to inﬁnity as possible. ( ), voltage ( ), the activity factor ( ), and switching fre-

È «

quency ( ), Î . One way to reduce power is to ¾

4. PROCESSORS reduce «, the number of devices that switch per cycle by using asynchronous circuits [16]. Asynchronous circuits eliminate Computer architects have improved processor performance by the global clock (and its associated global wire), and are based increasing the use of parallelism and decreasing the overhead on local communication and synchronization. In sharp con- trast to synchronous methodologies, devices in asynchronous ing and interconnect loading effects. IEEE Trans. Elec- circuits only switch when they are actually computing. An- tron Devices, 44(11):1951Ð57, Nov 1997. other orthogonal approach is to decrease clock frequency by [4] C. P. Collier, E. W. Wong, M. Belohradsk«y, F. M. exploiting parallelism. A fundamental result of early VLSI re- Raymo, J. F. Stoddart, P. J. Kuekes, R. S. Williams, and search is that for many functions there is tradeoff between the J. R. Heath. Electronically conﬁgurable molecular-based

implementation area () and the time it takes to compute the ½

Ò logic gates. Science, 285:391Ð394, July 16 1999.

» Ì Ò function (Ì ): , where is between 1 and 2 [17]. If [5] Michael J. Flynn, Patrick Hung, and Kevin W. Rudd. we ﬁx the time a computation takes, then since total computa- Deep-submicron microprocessor design issues. IEEE

tion time is inversely proportional to clock frequency ( )we

½Ò ¾ ½Ò

Micro, July 1999.

» È » Î obtain, , and, . In scaled CMOS, [6] S.C. Goldstein and M. Budiu. NanoFabrics: Spatial com-

Further power saving are saved because the maximum switch-

puting using molecular electronics. In Proceedings of the

» ´Î Î µ Î ing speed is related to voltage, th [3], or in

¿ 28th Annual International Symposium on Computer Ar-

» Î È » the the relevant range if we ﬁx Î , [5] and .

th chitecture, pages 178Ð189, June 2001.

¿Ò

» Thus, È and since capacitance is roughly propor-

[7] Reiner Hartenstein. A decade of research on recon-

¾Ò

» tional to area, È . If we can effectively harness figurable architectures - a visionary retrospective. In the area we can achieve the same performance while reducing Proc. International Conference on Design Automation clock frequency and power. and Testing in Europe 2001 (DATE 2001), Exhibit and Congress Center, Munich, Germany, March 2001. 5. CONCLUSIONS [8] Robert W. Keyes. What makes a good computer device? Nanoelectronics holds the promise of continuing technology Science, 230(4722):138Ð144, October 1985. scaling to feature sizes below 40nm. However, to harness the [9] M. Mishra and S.C. Goldstein. Defect tolerance at the abundance of resources and new constraints concomitant with end of the roadmap. In International Test Conference this feature size requires a new approach to the abstractions (ITC) ’03, September 2003. used to construct computing systems. Instead of clean barri- [10] N. Spencer M.V. Martinez-Diaz and J.F. Stoddart. The ers which hide the details between layers of the design, we self-assembly of a switchable [2]rotaxane. Ang. Chem. need to develop abstractions which allow tools to manage the Intl. Ed. Eng., 36:1904, 1997. details. Instead of using a hardware description language to [11] Sanil Nassif. Delay variability: Sources, impacts and design circuits for a fixed architecture on a chip assumed to trends. In Proceedings of the ISSCC, pages 368Ð9, 2000. be defect free we suggest using a high-level programming lan- [12] Michael Niemier and Peter Kogge. Exploring and ex- guage which can be compiled into configurations which are ploiting wire-level pipelining in emerging technologies. then mapped onto a reconfigurable fabric avoiding any defects In Proceedings of the 28th International Symposium on that might be on a particular chip. Computer Architecture, 2001. [13] J.M. Rabaey. Digital Integrated Circuits: A Design Per- spective. Prentice-Hall, 1996. Acknowledgments [14] D. Rosewater and S.C. Goldstein. Digital logic using This research is funded in part by the NSF under Grants CCR- molecular electronics. In IEEE International Solid-State 9876248 and CCR-0205523 and by DARPA under contracts Circuits Conference, February 2002. MDA972-01-03-0005 and N000140110659. [15] Sematech. International Technology Roadmap for Semi- conductors, 2001. References [16] I. E. Sutherland. Micropipelines. Communications of the ACM, 32(6):720Ð738, June 1989. The 1988 Turing [1] Keith A. Bowman and James D. Meindl. Impact of die- Award Lecture. to-die and within-die parameter fluctuations on the max- [17] J.D. Ullman. Computational Aspects of VLSI. Computer imum clock frequency distribution for gigascale integra- Science Press, 1984. tion. IEEE JSSC, 37(2), Feb. 2002. [18] Ron Wilson. ’structured’ asics arrive. EETimes, May 5 [2] M. Butts, A. DeHon, and S. Goldstein. Molecular elec- 2003. tronics: Devices, systems and tools for gigagate, gigabit [19] Inc. Xilinx. Virtex-ii series easypath: Frequently asked chips. In ICCAD-2002, Nov. 2002. questions. “http://www.xilinx.com/publications/ products/v2/faq/faq101 easypath.pdf”, January 2003. [3] K. Chen, C. Hu, P. Fang, Ren Lin, and D.L. Wollesen. [20] H. Zhou and A. Aziz. Buffer minimization in pass tran- Predicting cmos speed with gate oxide and voltage scal- sistor logic. In Proceedings of the International Sym-

2For scaled CMOS, static power is becoming an important consideration posium on Physical Design (ISPD-00), pages 105Ð110, Î and so one could both balance an increase Îth and a decrease to reduce N.Y., April 9Ð12 2000. ACM Press. dynamic and static power at the cost of using more hardware.