Ingeniero en Electrónica Tecnología de Dispositivos y Componentes Electrónicos y Fotónicos.
Lectura: Recomendaciones para el diseño y el layout en procesos tipo “epi”
RECOMMENDATIONS FOR SIGNAL INTEGRITY
Introduction
Signal integrity has become one of the major challenges in modern mixed-signal IC’s. The evolution of the fabrication processes has rendered the coexistence of noisy digital circuitry and sensitive analog signals a very complicate task. Massive digital processing generates unwanted noise signals in the supply distribution and in the common substrate that perturb the analog circuitry. If no special precautions are adopted, these interferences may considerably decrease the attainable dynamic range in the A/D and D/A interfaces.
Digital noise can reach the analog circuitry through two paths:
• Supply distribution: The switching current of the digital activity induces voltage peaks in the supply and ground due to the non-zero impedance of the supply distribution. This perturbation is known as simultaneous switching noise (SSN) or supply/ground bounce. Several strategies have become popular for attenuating the SSN impact, namely: (a) separate digital and analog supplies, (b) multiple bonding and careful packaging in order to reduce inductance, and (c) fully- differential handling of analog signals.
• Substrate noise: In standard CMOS processes, the substrate is common to digital and analog circuits. Any perturbations that reach the substrate might, hence, affect the behavior of the analog functionalities. Quantitatively, the amount of digital noise that reaches the analog part critically depends on the type of substrate. In this respect, two types of wafer are commonly found: (a) bulk (a.k.a. high-ohmic, resistive or p-) substrates, and (b) epi (a.k.a. low-ohmic, conductive or p+) substrates. The two types of substrate are schematized in Figure 1. The one in Figure 1a has been traditionally employed in standard CMOS processes. The doping of the substrate is uniform and normally low, so that the substrate behaves as a moderately high- impedance, relatively isolating path. On the contrary, low-ohmic wafers (Figure 1b, the actual choice in many deep-submicron processes) have a non-uniform substrate formed of a highly- doped layer on top of which a thin epitaxial layer with the traditional doping is grown. So, most of the substrate behaves as a very conductive path that facilitates noise propagation.
(a) (b) Figure 1 – Two types of wafers: (a) bulk (high-ohmic, p-) substrate; (b) epi (low-ohmic, p+) substrate
The importance of these topics for high-performance mixed-signal circuits is corroborated by a large number of publications and research developments in recent years. These have covered the analysis, modeling, and simulation of noise generation, propagation and reception mechanisms. Their most
Departamento de Electrónica y Electromagnetismo – E.S.I. – Universidad de Sevilla
Ingeniero en Electrónica Tecnología de Dispositivos y Componentes Electrónicos y Fotónicos.
Lectura: Recomendaciones para el diseño y el layout en procesos tipo “epi”
important conclusions are drawn in the form of design recommendations for signal integrity in both types of wafers [1]-[5].
Also important for obtaining maximum performance from mixed-signal IC’s is the design of a dedicate PCB. In fact, all the precautions adopted on-chip can be ruined by a wrongly conceived measurement set- up. This is especially true in characterization tests, where optimum performance is pursued. Well-known PCB design strategies for signal integrity are overviewed in [6]-[10]
In following section the specificities of on-chip / off-chip strategies for signal integrity in low-ohmic epi substrates are discussed. Next, specific recommendations for XXX in XXX process are given.
Signal integrity recommendations for low-ohmic epi wafers
It is commonly accepted that low-ohmic epi substrates are less appropriate for high-performance analog than high-ohmic ones. The deep substrate in epi technologies is very conductive and serves as a low- impedance path for noise. Whereas in traditional bulk processes any currents injected into the substrate flow near the surface (the most conductive region because of the channel-stop implant, see Figure 2a), in epi wafers these currents flow through the deep substrate and hence far away from the surface. Thus, many traditional analog layout strategies based on draining or avoiding noisy currents at the surface are almost useless. For instance, the usage of guard rings (especially the n-type ones) around digital and analog circuits has been shown to be hardly efficient. This is explained graphically in Figure 2b.
Figure 2 – Substrate current paths in: (a) bulk (high-ohmic, p-) substrate; (b) epi (low-ohmic, p+) substrate
Most importantly, the high conductivity of the deep substrate in epi technologies renders useless the most effective isolation strategy: increasing distance. While in bulk substrates distance means impedance and, hence, isolation, the impedance between two substrate contacts hardly varies with their relative position in a low-ohmic epi substrate. Furthermore, it keeps very low because the highly-doped deep substrate behaves like a single node. Thus, in epi substrates, once the perturbation has reached the deepest conductive part, it is present everywhere along the chip.
Removing noise from the deep substrate before it can affect other circuits is common-sense but extremely difficult, especially at high frequencies. At high frequencies the efficiency of the often available back contact is limited by Skin effect in the conductor-like p+ substrate. Even at low frequencies, draining noise is only possible if the connection to the external clean voltage source (or ground plane) is of low enough impedance.
Due to this difficulty, most effective signal integrity strategies in epi substrates are basically linked to (a) inducing less substrate noise, and (b) making the signal processing less sensitive to the substrate voltage (assumed polluted). The former are manly related to the use of low-noise logic (like constant-current logic families) or to control the switching activity (for instance avoiding simultaneous switching). In both cases, modifications of the digital design style are required, which limits the applicability of the low-noise digital Departamento de Electrónica y Electromagnetismo – E.S.I. – Universidad de Sevilla
Ingeniero en Electrónica Tecnología de Dispositivos y Componentes Electrónicos y Fotónicos.
Lectura: Recomendaciones para el diseño y el layout en procesos tipo “epi”
design.
It is clear hence that analog circuits must be designed to provide a good rejection for substrate noise. With this idea in mind the following design and layout rules can be applied to gain insensitivity to substrate voltage variations:
• Use fully-differential circuitry. It should be also fully-balanced with as clean as possible common-mode voltage. Maximum rejection of the common-mode disturbance is obtained if the two signal branches are fully matched, even for parasitics. In this respect, a layout floor plan in which the two branches (for instance the capacitors, switches, and associated routing in a switched-capacitor circuit) are close to each other (Figure 3a) should be preferred to a fully-symmetrical (but less branch-to-branch matched) floor plan (Figure 3b).
Figure 3 – Mixed-signal layout styles
• Use nMOS only for DC biasing. In standard CMOS technologies, nMOS devices are built directly in the substrate, so that their bulk node voltage will be always polluted. Nevertheless, they can be used for DC current generation provided that the rest of nodes (gate, source and drain) are equally polluted. In order to achieve this, the source and the bulk of the nMOS transistors must be connected to the same voltage. Note that using a clean voltage for grounding the source will induce a modulation of the DC current due to the body effect (see Figure 4). On the other hand, all nodes in the nMOS part should be maximally coupled to substrate, so that shielding must be avoided for these signals.
Figure 4 – DC current generation with substrate noise (a) sensitive and (b) insensitive connections
Departamento de Electrónica y Electromagnetismo – E.S.I. – Universidad de Sevilla
Ingeniero en Electrónica Tecnología de Dispositivos y Componentes Electrónicos y Fotónicos.
Lectura: Recomendaciones para el diseño y el layout en procesos tipo “epi”
• Use pMOS for signal processing. In standard CMOS technologies, pMOS devices are built in n-wells that can be biased separately. This offers the possibility of connecting the n-well to a clean voltage or to short-circuit it to the pMOS source, thus canceling the body effect. If a low impedance path to an external clean voltage is available, best performance is normally obtained by using this voltage to bias all the n-wells (Figure 5). Note that coupling to substrate of the signal paths is very harmful and should be avoided by using high-level metals for routing and shielding.
Figure 5 – Biasing n-well with a low-impedance path to an external clean voltage helps
• Mimimize coupling to substrate. In epi processes, the substrate must be viewed as a noisy environment. Hence any signal handling should be done as far as possible from it in order to reduce capacitive coupling. This can be achieved by employing high metal levels for signal routing. Coupling can also be attenuated by shielding. A “quiet” dedicated voltage should be used to this purpose. Since shielding can also be accomplished through the n-well, vdd is a good choice for the shielding voltage value. Small-dimension signal processing MOS devices are also required for low substrate coupling. In addition, no analog quiet reference voltage should be connected to substrate or be referenced to a voltage used to bias the substrate. On- chip “quiet” voltage generation must be accomplished starting from clean vdd and clean (not connected to substrate) ground (Figure 6)
Figure 6 – On-chip generation of a clean voltage in an epi low-ohmic substrate
• Control impedance. Impedance should be kept low especially for (a) analog supply, (b) shielding voltages, (c) back contact, and (d) any externally provided reference voltages. Be aware of the intrinsic resistivity of some layers (like n-well or unsalicided poly and diffusion) and that of the contacts. A large number of contact uniformly distributed along the contacted structure is then required for low impedance. Also, at high frequencies, the on-package (or on- Departamento de Electrónica y Electromagnetismo – E.S.I. – Universidad de Sevilla
Ingeniero en Electrónica Tecnología de Dispositivos y Componentes Electrónicos y Fotónicos.
Lectura: Recomendaciones para el diseño y el layout en procesos tipo “epi”
board) inductive parasitics show up. Apart from selecting low-L packages, the only way to reduce inductance is to resort to multiple bonding, not only in digital, but also in the analog pins (a) to (d) cited above. Thus, use as many pad/pins as possible. If no multiple pins are allowed adopt multiple-bonding (multiple pads wire-bonded to a single pin). See [2],[5]-[10] for low- impedance on-package / on-board strategies. Note that some pins, such as a18gnd! in Figure 6, do not require low impedance. In this example, the analog ground a18gnd! is used to bias the substrate and hence will be polluted. Thus, a ferrite bead has been placed between the associated pin and the PCB analog ground plane in order to increase impedance at high frequencies. In this way, the high-frequency switching currents of the digital activity will not return through the analog ground plane, but through the digital one. Controlling impedance helps to control current flow.
Specific recommendations for XXX in Process 5LM + MIM
The intended technology has epi layer with with low-ohmic deep substrate. On the other hand, the XXX stereo audio DAC cell is conceived to be compatible with low-cost applications, with reduced number of pins and minimum off-chip components. All things considered, the following recommendations should be followed for layout, packaging and PCB design: • Floor plan. Figure 7 shows the floor plan suggested for integrating the cell. The XXX cell must be placed in a corner. The location of the analog pads should be such that the corresponding pins are over the PCB analog ground plane (i.e. on the analog part of the PCB). A package with low inductance (around 1nH / wire) is recommended.
Digital Digital pads
ascsd009
Analog pads Digital pads
Figure 7 – Suggested floor plan
• Cell layout. The layout of the two channels of the XXX block is shown in Figure 8. Metal 5 layer (used for global routing of supplies and reference voltages) has been removed for increased visibility. It uses the structure of Figure 3a in order to ensure a good branch-to- branch matching of the differential stages: the right-most part is reserved for the continuous- time output sections. To their left, the OTAs and capacitors of the DAC+switched capacitor filter are placed. Finally, the switches are at the left sided, just to the right of the digital busses and clock phase generation logic. Furthermore, all the recipes given in the previous section are followed.
Departamento de Electrónica y Electromagnetismo – E.S.I. – Universidad de Sevilla
Ingeniero en Electrónica Tecnología de Dispositivos y Componentes Electrónicos y Fotónicos.
Lectura: Recomendaciones para el diseño y el layout en procesos tipo “epi”
hes OTAs
Switc CT filters CT Capacitors Rightch.
Ref. / bias generation Clk phases Clk phases
Leftch.
Figure 8 – Layout of XXX.
• External connections and components. Figure 9 shows the package-to-board connections and on-board components required for optimum performance. Table 1 describes the analog pins from a signal integrity point of view. A less-performant configuration with smaller number of pins and external components is suggested in Figure 10. In this low-cost configuration pins agnd!, and agndref are short-circuited to a18gnd!. Also, vbg does not need to be routed to pin.
Table 1 – XXX I/O’s description for signal integrity Analog I/Os Use Value Comments Shielding (on-chip) vbg Bandgap voltage 1.25V Internal reference for gaining Minimum coupling to PSRR substrate and shielding with a18vdd!
vref Internal reference voltage is 1.25V approx. vref and agndref must be coupled Minimum coupling to the difference between vref (obtained from on- and off-chip with proper substrate and shielding and agndvref bandgap voltage) capacitor according to inductance. with a18vdd! Be aware of damping. agndref Analog input to build the 0V Should coincide with PCB analog Minimum coupling to internal reference ground. Limit high-freq current substrate and shielding demand on it. with a18vdd!
vcm Central voltage of the output 1.5V in 3.3V Generated on-chip from bandgap It must be very clean, so signal, mainly used for output stage and agnd! . It is decoupled off-chip minimum coupling to generating the single-ended supply to PCB ground. substrate and shielding output. Also used as 0.8V in 1.8V (with a18vdd! ) must be common-mode voltage of output stage considered the differential signal. supply
a18vdd! General supply for analog 1.8V
Departamento de Electrónica y Electromagnetismo – E.S.I. – Universidad de Sevilla
Ingeniero en Electrónica Tecnología de Dispositivos y Componentes Electrónicos y Fotónicos.
Lectura: Recomendaciones para el diseño y el layout en procesos tipo “epi”
a18gnd! General ground for analog 0V All analog substrate should be Not required. DC voltages connected to this voltage with as and currents generated many contacts as possible. from this voltage (for External connection to analog instance in nMOS ground plane in PCB through devices) should be ferrite bead (optional). maximally coupled to a18gnd! avdd! Supply of the output stage. 1.8V or 3.3V Also used for biasing the n-wells Minimum coupling to of the output stage. External substrate and shielding connection and decoupling to PCB with a18vdd! analog ground required. agnd! Ground for on-chip 0V Never connect to on-chip Minimum coupling to generation of vcm substrate. External connection to substrate and shielding analog PCB ground. with a18vdd!
Figure 9 – Connections and on-board components required for optimum performance
Departamento de Electrónica y Electromagnetismo – E.S.I. – Universidad de Sevilla
Ingeniero en Electrónica Tecnología de Dispositivos y Componentes Electrónicos y Fotónicos.
Lectura: Recomendaciones para el diseño y el layout en procesos tipo “epi”
Figure 10 – Reduced-cost (and performance) external connections and components.
• Pad-Pin assignment. Figure 11 shows the pad-pin assignment for XXX. Considerations taken into account are: a) decrease coupling between outputs and vcm and vref voltages and also between noisy and sensitive signals; b) shorten the layout-to-pad routing and provide symmetrical paths for supply distribution; and c) group shortable pins in low-cost applications. Two versions of the pad-pin assignment are given, corresponding to optimum performance and low-cost connections. For optimum performance, wires marked with thick line should be double-bonded ( vref , agndref , vcm , vbg , a18vdd! avdd! , and agnd! ). However, single-bonding is to be used for outl/r and a18gnd! . Pins 39 and 6 should be reserved for “quiet” digital signal. In particular, these signals must not content large frequency components inside the audio band. Figure 12 shows an example for correct and incorrect double bonding.
Departamento de Electrónica y Electromagnetismo – E.S.I. – Universidad de Sevilla
Ingeniero en Electrónica Tecnología de Dispositivos y Componentes Electrónicos y Fotónicos.
Lectura: Recomendaciones para el diseño y el layout en procesos tipo “epi”
Figure 11 – Pad-Pin assignment for (a) optimum performance (double-bonding should be used for the wires marked with thick line); (b) low-cost.
Figure 12 – Example of correct and incorrect double bonding
REFERENCES [1] X. Aragonès, J.L. González, A. Rubio: Analysis and Solutions for Switching Noise Coupling in Mixed-Signal ICs , Kluwer Academic Publishers, 1999. [2] M. Ingels, M.S.J. Steyaert: “Design Strategies and Decoupling Techniques for Reducing the Effects of Electrical Interference in Mixed-Mode IC’s,” IEEE Journal of Solid-State Circuits , Vol. 32, pp. 1136-1141, July 1997. Departamento de Electrónica y Electromagnetismo – E.S.I. – Universidad de Sevilla
Ingeniero en Electrónica Tecnología de Dispositivos y Componentes Electrónicos y Fotónicos.
Lectura: Recomendaciones para el diseño y el layout en procesos tipo “epi”
[3] M.S. Peng and H.-S. Lee: “Study of Substrate Noise and Techniques for Minimization,” IEEE Journal of Solid-State Circuits , Vol. 39, pp. 2080-2086, November 2004. [4] N.K. Verghese, T.J. Shmerbeck, D.J. Allstot: Simulation Techniques and Solutions for Mixed- Signal Coupling in Integrated Circuits , Kluwer Academic Publishers, 1995. [5] S. Donnay, G. Gielen (Eds.): Substrate Noise Coupling in Mixed-Signal ASICS , Kluwer Academic Publishers, 2003 [6] M.I. Montrose: Printed Circuit Board Design Techniques for EMC Compliance , IEEE Press 1996. [7] R. Morrison: Grounding and Shielding Techniques in Instrumentation 3rd Ed ., John Wiley & Sons, 1986 [8] C.S. Walker : Capacitance, Inductance and Crosstalk Analysis , Artech House, 1990. [9] J.L. Lamay and H.T. Bogard: “ How to Obtain Maximum Practical Performance from State-of-the- Art Delta-Sigma Analog-to-Digital Converters, ” IEEE Trans. on Instrumentation and measurement, Vol. 41, pp. 861-867, December 1992. [10] J. Berrie: “The Defensive Design of Printed-Circuit Boards,” IEEE Spectrum , pp- 76-81, September 1999.
Departamento de Electrónica y Electromagnetismo – E.S.I. – Universidad de Sevilla