Signal Integrity Analysis and Simulation Tools Include IBIS Models

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High Frequency Products From September 2004 High Frequency Electronics Copyright ® 2004 Summit Technical Media, LLC HIGH-SPEED MODELS

By John Olah and Sanjeev Gupta, Agilent EEsof EDA, and Carlos Chavez-Dagostino, Altera Corporation

ignal integrity is a several hybrid-domain simulation techniques, This issue’s cover highlights major concern for where the simulator is conversant in both the introduction of Agilent Sengineers working time and frequency domain and can combine Technologies’ ADS2004A, on high data rate designs. models suitable for either domain. This article which now includes Effects such as crosstalk, describes the types of models that need to be greatly enhanced capa- coupling and delays in taken together for high-speed signal integrity bilities for signal integrity transmission lines have a analysis, and illustrates their use in a simula- modeling in both time big impact on signal tion of a high-speed memory circuit. and frequency domains integrity. High-speed digital board designers can Requirements for High-Speed now use design tools that combine time- Signal Integrity Simulations domain IC-specific I/O Buffer Information In broad terms, there are three important Specification (IBIS) models with accurate simulation requirements for analog high- transmission line models to get a better speed signal integrity characterization: understanding of the signal distortion due to coupling and delays. 1. A hybrid-domain simulator that handles time-domain and frequency-domain models Introduction 2. Accurate transmission line structures (best In terms of analog simulators, historically, described in the frequency-domain) there have been two main camps; time- 3. Driver and buffer models that terminate domain SPICE simulators and frequency- either end of the transmission structure domain simulators using linear S-parameters (best described in the time-domain) or nonlinear Harmonic Balance. Each of these simulation domains are known to have The next sections will further describe strengths and weaknesses in terms of the these requirements. types of simulations they can best perform, and what circuit models they can best repre- Hybrid-Domain Simulation— sent. It was difficult to find a single simulator Transient/Convolution that could handle the breadth of model types Convolution is one such hybrid-domain for time-domain and frequency-domain that simulator to handle both time-domain and fre- are required for some high-speed circuits. quency-domain models. The main difference When it comes to the simulation of a circuit between traditional SPICE transient simula- for high-speed digital design, these two tion and convolution simulation lies in how domains start to merge; digital waveforms each analysis characterizes the distributed that can best be described by their time-vary- frequency-dependent elements of a circuit. A ing behavior need to interact with models that transient analysis is performed entirely in the are best described by their frequency time-domain, and so it is unable to account for response. During the past several years, ana- the frequency-dependent behavior of dis- log design software has seen the emergence of tributed elements such as microstrip models,

48 High Frequency Electronics High Frequency Products HIGH-SPEED MODELS

speed designers are the multilayer interconnect library models in Advanced Design System. The multilayer transmission line models are based on method of moments and Green’s function analytical methods and allow designers to handle arbitrary dielectric layers and arbitrary metal thickness. Multilayer interconnect models in ADS are implemented as the numerical Maxwell’s Equations-based solution for the two-dimensional cross- section geometry that is defined by the model parameters. S-parameters are another frequency-domain approach to describe transmission line effects, and most high-frequency design software, EM simulators and instrumenta- tion either produce or accept S-parameter data. Figure 1 · A typical output buffer equivalent circuit. Driver and Buffer Models—IBIS Models To produce the signals that are transmitted between S-parameter blocks, and so on. In a transient analysis, chips, designers can either use transistor-level models of such elements are represented by simplified, frequency- the entire IC, or behavioral models of the driver and independent models such as lumped equivalent circuits buffer circuit. Simulating circuit level I/O buffers can gen- and transmission lines with constant loss and no disper- erate a realistic stimulus signal and termination but sion. These assumptions and simplifications are usually often the circuit-level description is difficult to obtain sufficient at low frequencies, but are inaccurate at higher from the IC vendor due to issues with intellectual proper- data rates. ty (IP). Encrypted driver circuits protect the IP but can Convolution converts the frequency-domain informa- suffer from long simulation times because the circuit- tion from distributed elements to the time domain, effec- level netlist of the driver can be quite large, and encrypt- tively resulting in the impulse response of those ele- ing does nothing to reduce the complexity of the circuit ments. The input waveform to the element is convolved being simulated. To improve the simulation time while with the impulse-response of the element to produce the protecting IP, the concept of the IBIS behavioral model output signal. Components that have exact lumped was introduced by Intel back in 1990s. The IBIS model equivalent models, including nonlinear elements are provides tabular time-voltage pairs of data describing the characterized entirely in the time domain without using rising and falling waveform at the output when triggered impulse responses. by the input signal. Figure 1 illustrates an electrical If the frequency domain model of an arbitrary trans- equivalent model of an output buffer, The devices A and B mission geometry is not available, an electromagnetic represent the pullup and pulldown devices while devices (EM) simulator can provide S-parameter data, or if the C, and D represent Powerclamp and Groundclamp diodes. actual transmission line has been built then it can be “Pullup” describes the transistors when the output is measured with a network analyzer to produce S-parame- high. “Pulldown” describes the transistor when the output ter data. is low. To use IBIS data in a simulation environment, the The convolution simulator within the Advanced EDA tools need to have an equivalent behavioral model Design System (ADS) from Agilent EEsof EDA is used for and need to extract SPICE equivalent parameters from the simulations. IBIS data. The 2004A release of ADS marks the first time that Accurate Transmission Line Structures IBIS models are available for use with the transmission Transmission lines represent the connection path for line models and convolution simulator of ADS. The IBIS signals between chips. In a high-speed design the signal model makes use of the Symbolically Defined Device quality and timing performance determines the inter- (SDD) and Frequency Domain Devices (FDD) to create symbol interference of a system. The ability to accurate- behavioral models by directly defining port voltage and ly predict printed circuit board performance allows current relationships using algebraic equations on the designers to integrate high-speed circuits into their prod- schematic page. Frequency Domain Devices allow the uct and improve system quality and reliability. The wave- use of trigger events and clock enabled events and are form quality and the timing margins are adversely affect- used here to create the IBIS behavioral model in ADS. ed by high frequency transmission line analog effects During the transition of logic state, the IBIS behavioral such as reflection, dispersion, cross talk, ground bounce, models trigger reading the Vt tables and generate scaling and propagation delay. Of particular interest to high coefficient for the pullup and pulldown devices. Figure 2

50 High Frequency Electronics Figure 2 · The IBIS SPICE equivalent circuit in ADS. shows the IBIS equivalent circuit in device and all trigger events. Single ADS. A five port FDD is used to port FDDs are used to create define the pullup and pulldown Groundclamp and Powerclamp

Figure 3 · Comparison of Vt table waveforms with ADS simulation results. High Frequency Products HIGH-SPEED MODELS

Figure 6 · The Stratix-DDR-II Figure 4 · The Stratix-DDR-II address interface. address interface and simulation results.

er evaluates several topologies and selects the one that fulfills all the specifications such as space, compo- nent number and performance. In addition, the results of these simulations help to set crucial parameters for the transmission structure, such as trace width, trace spacing, maxi- mum trace length, and critical com- ponent placement. It is important to understand that these simulations are intended for selecting the components and topologies as well as for fine tuning of the signal path. The results analysis is used to set the rules that will be incorporated into the layout. Figure 5 · The Stratix-DDR-II address interface and simulation setup. SSTL-II Multi-Load Address The address bus and clocks are diodes. The DataAccessComponents performed for the address bus, since often shared among several DDR II are used to access the DC-IV data, Vt the bus is unidirectional. The address devices on the board, so it is harder to data and the differential of Vt data is a point-to-multi-point interface. achieve good signal integrity on the tables. This is because each address bit is address bus. This section shows a Next, we will describe an exam- serving more than one memory typical address bit routing topology ple combining IBIS models, transmis- device. and a proposed termination scheme. sion lines and convolution—a DDR-II The total routing length from the Figure 4 shows the block diagram Interface Address Interface FPGA to the memory device is set to of this address scheme. Figure 5 ~4.5 inches, which is a conservative shows the ADS test setup, and Figure Example Simulation—Overview estimate in the majority of systems. 6 shows the simulated waveform at Simulations are performed using Figure 3 shows the rise and fall the DDR-II memory IC interconnect ADS 2004A from Agilent EEsof EDA. portion of waveform generated by balls. IBIS models are created for the simulating the Stratix_v21 IBIS Stratix device and the Micron DDR II model using ADS. The waveforms are A0 Post-Layout Simulation memory devices. The memory devices in good agreement. When the layout is complete, a used are DDR-II x16 SDRAM (part post layout simulation is performed number Micron MT47H16M16FB). Pre-Layout Simulations on the critical sections of the board to Simulation frequency is 200 MHz or The pre-layout simulations are ensure there are no major signal 400 Mega Transfers per second. required at the earliest stages of the integrity problems. Based on the Simulations for the write cycle are PCB design. In this stage the design- results of the post-layout simulation,

52 High Frequency Electronics Figure 7 · The Stratix-DDR-II A0 layout interface. any changes required are incorporated in the layout and the layout is released to the fabrication house for board manufacturing. The post layout simulation pro- Figure 8 · The DDR-II address post-layout simulation setup. cess requires the layout of all active layers on the board as well as the physical properties of the dielectric orders of magnitude without impact- sient behavioral model of digital I/O and metal layers. The post-layout ing the accuracy of the results. buffers from IBIS,” Proceedings, 46th simulations use the physical proper- Figures 7 through 9 show the layout, Electronic Components and Technol- ties supplied by the fabrication house the simulation setup, and the simula- ogy Conference, 28-31 May 1996, that may differ from those published. tion results. pp.1009-1015. The frequency domain simula- 3. “User Defined Models,” Agilent tions of the signal paths were per- Stratix-DDR-II Address (A0) ADS 2003C manual. formed using ADS Momentum, the Interface Measurements method-of-moments based planar Measurements were taken using a Author Information electromagnetic simulator in ADS, 6 GHz oscilloscope and high John Olah is an applications from 10 MHz to 2.0 GHz and saved impedance probes. The measured marketing manager and Sanjeev as S-parameters (represented as a data shows good correlation with sim- Gupta is an applications engineer black box in the post-layout simula- ulated data, as shown in Figure 10. with Agilent’s EEsof EDA division. tions, S2P). The Stack-up used was These authors can be reached via e- divided into two major substrates; References mail at: [email protected] and the external layers (TOP layer and 1. Stephen Peters, I/O Buffer [email protected]. BOTTOM Layer) and the internal Modeling Cookbook, The IBIS Carlos Chávez Dagostino is a dual stripline differential layers. OpenForum. senior applications engineer with Partitioning the stack-up reduces the 2. P.F. Tehrani, Yuzbe Chen, Altera Corporation. He can be con- computing time required by several Jiayuan Fang, “Extraction of tran- tacted at: [email protected].

Figure 9 · The DDR-II address post-layout simulation Figure 10 · The DDR-II address interface simulated ver- results. sus measured results.

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