SPICE and IBIS Modeling Kits the Basis for Signal Integrity Analyses
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SPICE and IBIS Modeling Kits The Basis for Signal Integrity Analyses RolandH. G. Cuny DevelopmentSupport SiemensNixdorf InformationsystemsAG Paderbom,Germany Abstract - Reliable high speed board design requires a developedat the University of Berkeley in 1972 and freely thorough analog analyzation of interconnect traces. distributed. During a very short time SPICE became the Consequentlya broad spectrumof signal integrity simulation preferredanalog simulation tool at universities as well as at tools hasbeen developed and is readily availableon the market semiconductorcompanies. Today a large variety of tool to satisfy customersneeds. All softwaretools require a large vendorsoffers many different SPICE derivativesfor hardware amount of dam that describe electrical behavior of the platforms like personal computers, workstations and integratedcomponents involved at the interconnecttraces. In supercomputers.It is well known that the SPICE simulator this paperfor the first time two setsof data for signal integrity alwaysneeds models of the componentsthat are involved. The analyses, SPICE and IBIS modeling kits, are outlined, set of data that is particuhuly necessaryfor signal integrity discussedand comparedto eachother. The information of the analyseswill be described. kits providesthe user with all datato perform buffer modeling, therefore enabling signal integrity analysis and synthesison The SPICE modelingkit needsto include a descriptionof all printedcircuit boards. types of input-, output- and bi-directional buffers as well as ESD protection structures, clamping diodes and the IC package. Internal logic circuitry does not need to be INTRODUCTION consideredsince it doesnot havesignificant impact on the I/O- It is well known that the designof high-speedprinted circuit characteristicsof the circuit. A table that equates the boardsis getting tougherand more complicateddue to higher appropriatebuffer to the correct pin and signal name is integrationdensities [I]. Physical effects like groundbounce, required. In addition block diagramsor detailedschematics of crosstalkand reflection needto be simulatedbefore.the board the I/O-buffersare appreciated.Simulation data examplescan layout is done. Reworking the boards is time and money- be added,too. consumingand in contrast to ‘time-to-market’ for both: The hardwaredesigner and the chip vendor. Extensivesimulations This chaptercharacterizes the requirementsin details. It is of a large variety of bus types and -topologies allow a high very well suited for newcomers that do not have much potential of creativity. Practical solutions that enable best backgroundin SPICE simulationsbut have to deal with SPICE performanceand optimized signal integrity have beenachieved data. In addition SPICE expertsthat need to simulate signal to date. integrity issueswill find it a valuablereference work. But designinghigh performancecomputer systems at the right time for the market requireseven more. Tight contactsor joint developmentswith the semiconductorcompanies are nowadays 1.l Semiconductor model a must. The hardwareengineer checks the proper function of A very importantpart of the SPICEdescription is the physical the buffers in the simulatedsystem environment during the chip specificationof the semiconductordevices like diodes as well design. The analyzationresults are used to optimize the buffers as bipolar, junction and MOSFBT transistors. Thesedata are characteristicsbefore the tape-out is done. Degradedclock called a ‘model”. Each model consistsof a set of parameters frequency,less noise immunity or even a rework of the chip that deals with DC and AC characteristics, geometrical and projectdelays can be avoided. dimensions, noise and temperature behavior of the The availability of modelsis the basisto conductsystem and semiconductordevices. Vendor use modelsfor worst, typical board level simulations[2]. This paperdetails out the required and best case that describe their process comers. Signal data to perform signal integrity analysisand synthesison the integrity simulations are often based on typical models to interconnecttraces being driven by integrated circuits. By achievefast reliable results. Additional studiesof the worst definition the sum of theseinformations is called a ‘modeling case enable analyzations of noise margins and impact of kit’ [3]. Two different modelingkits will be presented.Part 1 temperatureexcess. deals with models for the world wide used SPICE simulator andpart 2 with the new IBIS standard. SPICE has built-in models for different precisions, convergence,dimensions and material. Thereforethe models are classified in levels’. E.g. the MOSPBT level 13 of 1. SPICEMODELING KIT SPICE is an universal simulation program to analyze l Someliterature does not stick to the meaningof ‘model’ as a electronicalconnections on chip, board and systemlevel in the reserved word in the SPICE syntax for the semiconductor parameters. steady-state,transient and frequencydomain. It was originally The lax usage of ‘SPICE model’ in rhe sense of a complete SPICE description frequently leads to misunderstandings. O-7803-3207-5/96/$5.00 0 1996 IEEE 204 HSPICE is more accuratethan the Berkeley level 3 (empirical that include values for output impedanceversus the set of model), since it takes into account the physics of small- transistorsat typical conditions. geometry MOS transistors. Signal integrity analysesalways require the precisestmodel available. Simplified modelstend Slew rate controls offer a possibility to alter the rise and fall to misrepresentimportant buffer characteristicslike output time of the output signal. This feature is mainly intended to impedanceand transitiontime of the output signal. reducenoise on the GND andVCC lines. A slew rate control is often made up of extra transistorsthat temporarily increase Some semiconductor vendors use their own proprietary driving capabilities. The discussionof other buffer control modeling level. These models are used both internally at the options like output edge control will be omitted since this is semiconductorcompany and supplied to the customer. The beyondthe intentionof this paper. user may need an authorizationkey or a permit file to handle thesespecial levels. I buffer control 1.2 Circuit netlist mode selection output input characteristic characteristic Another essential element of a SPICE description is the differential drive threshold circuit netlist. Its purposeis to define the on-chip connection push-pull voltagelevel voltagelevel of the semiconductordevices, passivedevices and parasitics. open-drain impedance clamping Signal integrity analysesdo not need data about internal logic. open-source slew rate The only required part of the netlist is comprised of the pseudo-diff. @se complete input-, output- and bi-directional buffers including swing ESD structuresand clamping diodes. Each buffer is definedin its own subclrcuit with a set of input and output nodes. The etc. etc. etc. user always demandsa brief descriptionof the function of the interfacing nodes. Similar informations are neededfor power Fig. 1. Possibilitiesto influencebuffer behavior supply* Input characteristicslike the thresholdvoltage are changedby Signal integrity analyses require complete output buffer applying different referencevoltages at special buffer control netlists. Investigations of partial structures which only inputs. In all casesneeds the userappropriate informations that comprise of one transistor stage are not meaningful. The allow him to operatethe buffer in the desiredmanner. These dynamic behavior of a single transistoroutput stage.is tightly dataare often suppliedas a part of the SPICE descriptionor in coupled with the shape of the applied stimulus. The more applicationnotes or datasheets. transistorstages are connectedto eachother, the lessdependent is the output signal from the input voltage ramp and the more accurate will be buffer characterization. Furthermore I.4 Package model incomplete buffer netlists do not allow analyzationof internal The IC packageis specified in a packagemodel file. It is buffer propagationdelay. supposedto simulate package influences on the I/O buffer characteristics.Parasitic parameters of a packageinterconnect are mainly resistance(R), inductance(L) and capacitance(C). 1.3 Advanced buffer controls Electrical signals will experienceattenuation, crosstalk, delay Today’s buffers are very complex and do not simply consist and switching noise which are subject to signal integrity of a few transistorsbetween an input and an output node [4]. simulations. Additional transistors are used to switch different buffer operating modes or to change the I/O characteristicsof the The housing of an IC is a very complex structure [5]. Its buffer. A brief overview of buffer control parametersis shown signal interconnectionsare three dimensional,surrounded by in figure 1 and the more important ones will be discussed inhomogenousmaterials and consist of several different below. segmentslike leadframe,bonding wire or tape bond, pad and internal wiring. Length and geometryof interconnecttraces Mode selectinputs are usedto switch betweendifferent types dependon the pin or ball position. Power distribution often of transistor output stages or to partially turn off output comprisesof power and ground planes. New 32-bit logic transistors. The buffer may be switched betweenpush-pull componentsinclude four separate8bit chips with individual (driving and sinking current) and open-sourceor open-drain power pins in a single package. Consequently,modeling