PEER REVIEWERS
This book has been reviewed for technical accuracy by the following experts from the PCB industry.
Happy Holden
Consulting Technical Editor, I-Connect007
Happy Holden is the retired director of electronics and innovations for Gentex Corporation.
Happy is the former chief technical officer for the world’s largest PCB fabricator, Hon Hai Precision Industries (Foxconn). Prior to Foxconn, Holden was the senior PCB technologist for Mentor Graphics and advanced technology manager at Nan Ya/ Westwood Associates and Merix.
Happy previously worked at Hewlett-Packard for over 28 years as director of PCB R&D and manufacturing engineering manager. He has been involved in advanced PCB technologies for over 47 years.
Eric Bogatin
Eric Bogatin is currently the dean of the Teledyne LeCroy Signal Integrity Academy. Additionally, he is an adjunct professor at the University of Colorado- Boulder in the ECEE department, where he teaches a graduate class in signal integrity and is also the editor of Signal Integrity Journal. Bogatin received his BS in physics from MIT, and MS and PhD in physics from the University of Arizona in Tucson.
Eric has held senior engineering and management positions at Bell Labs, Raychem, Sun Microsystems, Ansoft and Interconnect Devices. Bogatin has written six technical books in the field, and presented classes and lectures on signal integrity worldwide. MEET THE AUTHOR
Fadi Deek
Signal/Power Integrity Specialist Corporate Application Engineer
In 2005, Fadi received his B.S. degree in computer and communications from the American University of Science and Technology (AUST) in Beirut, Lebanon.
That same year, he joined Fidus Systems as a design engineer. He designed circuit boards at Fidus for three years.
In 2010, Deek received his M.S. in electrical engineering from the University of Arkansas in Fayetteville. He soon joined Mentor Graphics as a corporate marketing engineer. In 2013, Deek became a corporate application engineer supporting the HyperLynx® tool suite. In parallel, he is also pursuing his Ph.D. at the University of Colorado in Boulder under the supervision of Dr. Eric Bogatin. The Printed Circuit Designer’s Guide to...™ Signal Integrity by Example
Fadi Deek
Mentor Graphics Corp., a Siemens Business
© 2017 BR Publishing, Inc. All rights reserved.
BR Publishing, Inc. dba: I-Connect007 PO Box 1908 Rohnert Park, CA 94927 U.S.A.
ISBN: 978-0-9982885-2-9 Visit I-007eBooks.com for more books in this series.
The Printed Circuit Designer’s Guide to...™ Signal Integrity by Example
CONTENTS
Introduction ...... 1
Chapter 1
Impedance ...... 4
Chapter 2
Reflections and Terminations ...... 18
Chapter 3
Crosstalk ...... 28
Chapter 4
Differential Pairs ...... 40
Summary and Conclusion ...... 52
Glossary ...... 53
References ...... 55 INTRODUCTION
In our current high-speed regime, interconnects are no longer transparent. Interconnects screw up the pristine performance of the signals coming off the chips. If you do not consider these problems and design them out of your product from the beginning, there’s a good chance your product will not work.
This is what signal integrity is really about: how the electromagnetic fields of the signals interact with the boundary conditions of the dielectrics and conductors. Or, in the circuit's view, how the voltages and currents of the signals interact with and are distorted by the transmission lines and discontinuities of the interconnects.
The general process we use to eliminate signal integrity problems is to first be aware of the problems we might encounter, and then follow the best design principles to design them out. Since every product is really customized, with its own set of tradeoffs between performance, cost, risk and schedule, ultimately, we have to optimize each design individually.
This is most effectively done by applying analysis techniques such as rules of thumb, approximations and numerical simulations. We use these tools to explore design space as “virtual prototypes” trying different approaches and evaluating the “bang for the buck” to make engineering tradeoffs.
1 But we can’t follow this process blindly and just run simulation after simulation. The most effective engineers are those who have a firm grasp of the essential principles of signal integrity. The farther up the learning curve, the more effectively we can apply the best design principles and explore tradeoffs.
That’s what this first book in the series is all about: exploring the essential principles by example.
The examples are based on an essential principles signal integrity boot camp developed by Mentor, a Siemens business. In this book, we introduce examples of five out of the six different problems that can arise in leading-edge products and some of the design solutions.
More information about the essential principles, their fundamental basis, and how we apply them, can be found in a book by Eric Bogatin, Signal and Power Integrity—Simplified, published in 2010 by Prentice Hall.
It’s important to keep in mind that when using simulations to explore design space, we must always practice safe simulation. This means never performing a measurement or simulation without first anticipating what you expect to see. If it is not as you expect, there is always a reason that is worth exploring.
In each example, we’ll apply the essential principles to illustrate the problem, the root cause, the solutions, and what we expect to see. Then we will use simulations to build virtual prototypes and explore design space to illustrate the problems and solutions.
The four examples in this book include:
1. Designing controlled impedance transmission lines
2. Engineering proper terminations to minimize reflection noise
3. Reducing crosstalk
4. Optimizing differential pair design and termination
We hope the information in this book helps you to better manage signal integrity issues in your next PCB design.
2 3 CHAPTER 1 Impedance
Characteristic Impedance vs. Instantaneous Impedance A transmission line, or a trace on a printed circuit board with its associated return path, is electrically defined by two properties: its characteristic impedance, or Z , and its time delay, TD.
As a signal propagates0 down the signal and return path, it will continuously encounter an instantaneous impedance. This means the signal will apply a voltage and drive a current through each infinitesimal section of the transmission line as shown in Figure 1-1. The impedance the signal sees is the instantaneous impedance. In a uniform transmission line, the instantaneous impedance is the same each step along the transmission line. That single impedance value is the characteristic impedance of the transmission line. This means that a non-uniform transmission line does not have just one impedance that characterizes it.
v 10.0 nH C1 Signal path R2
Vin i 100.0 pF 0.0 ohms Return path
∆x
Figure 1-1: Signal traversing a transmission line.
So, what elements of the transmission line can affect its impedance? To answer the question, a stripline configuration will be used.
For the analysis covered in this section, an advanced high-speed analysis tool was used to model several types of transmission lines, wires, cables
4 and connectors. One of the options available is a stripline modeler shown in Figure 1-2.
Figure 1-2: Stripline modeler.
How does each term affect theZ and the TD? The two dielectric height parameters will affect the capacitance per length of the trace by the following rough approximation,0 where is the material permittivity, is the width of the conductor and is the C = εw/H ε height or the separation between each conductor. By decreasing any of w H the heights H1 or H2, the capacitance will increase.
The connection between the characteristic impedance and the capacitance per length is Z . Any increase in the capacitance per length will decrease Z . 0=√(L/C) Also, the width of the0 trace, if increased, will decrease Z since it will increase the capacitance per length. 0 Another factor that will affect the capacitance per length is the dielectric constant. From the capacitance approximation, any increase in ε will increase the capacitance per length.
5 The length of the conductor will not affectZ since, as mentioned before, the instantaneous impedance is constant in a uniform transmission line. 0 Other parameters will have some effect on the impedance, but it will be minimal. As an experiment, Table 1-1 shows the impact on characteristic impedance from a 10% change in each parameter. The initial nominal values of the parameters produced a 49.6-ohm impedance. To capture the new impedance, only one parameter was changed at a time and then reset to its initial value. Only H1 was varied, since the impact of H2 would be identical.
We would expect that the things that affect capacitance per length the most would have the biggest impact. An item like dissipation factor should have no impact on the characteristic impedance at all.
As can be seen from Table 1-1, the dielectric constant and line width had the biggest impact whereas the loss tangent had no impact at all.
Parameter Initial value for Z =49.6 10% increase New Z % change in Z T 1.35 1.485 49 1.2
W 5 5.5 47.6 4
H1 7 7.5 50.7 2.2
Er 4.3 4.73 47.2 4.8
Lt 0.02 0.022 49.6 0
Table 1-1: Comparison of parameter effect onZ due to 10% increase.
0 When it comes to the time delay, TD, the characteristic impedance will have no impact. Only the length of the transmission line and the dielectric constant are expected to have an effect. The velocity of the signal can be calculated using where c is the speed of light in air. This formula shows that the velocity and the dielectric constant are inversely v=c/√(ε_r) proportional. Other than that, the rest of the parameters should have no impact on the TD.
To explore this, another experiment was conducted to determine which parameter might have a bigger impact. A 10% increase was applied to
6 each of the parameters. Starting from a 527 ps TD, the results are shown in Table 1-2. Note that the length of the stripline had the biggest impact on the TD. An increase in the dielectric constant slowed down the velocity and thus the transmission line appeared to be longer. Other parameters had no impact at all, exactly as expected.
Initial value for Parameter TD = 527ps 10% increase New TD % change in TD
L 3 3.3 579.8 10 T 1.5 1.65 527 0 W 5 5.5 527 0 H1 7 7.7 527 0 Er 4.3 4.73 552.8 4.9 Lt 0.02 0.022 527 0
Table 1-2: Comparison of parameter effect on TD due to 10% increase.
Another handy rule of thumb is the approximate ratio of the line width to the dielectric thickness that would achieve 50 ohms. Using the stripline modeler, a few values were calculated for a stripline. The width of the trace (W) and the total dielectric thickness (b) that is measured between the two reference planes were chosen so as to keep a constant 50-ohm impedance.
The ratio W/b is plotted in Figure 1-3 versus b in the left plot and versus W in the right plot. As can be seen the ratio varies slowly starting around 0.33. As a rough estimate, the ratio of line width to total dielectric thickness as 1/3 is a starting point when designing the stack up of the stripline layers.
7 Figure 1-3: Ratio of width vs. total dielectric thickness W/b for a 50-ohm stripline: upper plot is vs. b, lower plot is vs. W.
8 Driver Output Impedance A signal source can be simply modeled as a Thevenin equivalent voltage source as shown in Figure 1-4. Both models have an output impedance Z that will affect the signal being transmitted onto the transmission line.
�
Zs
V I Zs
Figure 1-4: Driver model: left, the Thevenin model, right, the Norton model.
A simple way to measure the driver output impedance is simply by using a voltage divider circuit. We first measure the unloaded output voltage. Then we add a resistive load. As the resistance of the load is varied, we observe its value when the output voltage drops 50%. This value of resistance is the output resistance of the driver.
U1.AF24 U2.AF24 First, it is important to find the unloaded output voltage level of the driver. R1 In order to do that, an Arria10_NoP G Arria10_NoP G DDR4_DI _D 0 DDR4_DI _D 0 open-ended driver was Net002 Net001 50.0 ohms placed on the schematic and assigned to the desired buffer model as shown in U1.AF24 in Figure 1-5: Output impedance measuring circuit. Figure 1-5.
Every model has three different corners of operation: typical, slow-weak and fast-strong. A simulation was run and the results are shown in Figure 1-6. As can be seen in red, the output of the driver of a fast-strong falling edge starts at 1.4 V and settles at 0V. The rising edge of a typical corner starts at 0 V and settles at a voltage level of 1.2 V.
9 Figure 1-6: Output voltage of open ended driver: In red, falling edge fast-max corner; in blue, rising edge typical corner.
Note that the package model was intentionally removed from the driver model so that a clean waveform can be generated. The package effect will be discussed in a later section.
Now that the output voltage is known, a resistor load is placed at the output of the receiver. The goal is to vary the resistor value to measure an output voltage of 1.2/2 = 0.6 V. As a start a 50-ohm value is assigned to the resistor and the simulation is run. The output voltage level is shown in blue in Figure 1-7 as 781 mV. In order to bring that voltage level closer to 600 mV the load resistor needs to be decreased. A few more values are taken and a resistance of 32 ohms came very close to our target.
An important point to keep in mind is that a driver will not have a single output impedance. Instead, in each of its operating corners the typical slow-weak, fast-strong might exhibit different output impedances. The pull-up, for a rising edge, and pull-down, for a falling edge, transistor circuitry might show differences as well. A similar analysis was done simulating the model at its fast-strong corner using a falling edge. The red plots in Figure 1-7 show that to achieve a voltage level of 1.4/2 = 700 mV a 32-ohm load is needed as well. It happens to be that this model is symmetric.
10 Figure 1-7: Driver output voltage when resistor value is swept: In blue typical operating corner, in red fast operating corner.
Driver Features and Package Effects In the previous section, the driver was used with its package information extracted from the IBIS model. However, in real design simulations, the package parasitic effects, the transistor parasitic capacitances and the on-die capacitance effects should be taken into considerations.
Before digging deeper into these effects, the output waveform shown in Figure 1-6 should be analyzed. Looking at the blue curve for a rising edge simulation, everything looks as expected except for a small dip between 200 ps and 260 ps. A close-up of the dip is shown in Figure 1-8. Where could this dip be coming from when all the driver parasitics have been commented out?
The answer is simply to look inside the IBIS model and examine the “raw” V-t curves. The model data is plotted in Figure 1-9. The plots represent that data measured by the model vendor and show that the dip is inherent to the model itself. Another important piece of information that
11 Figure 1-8: Driver dip intrinsic to model. the plot in Figure 1-9 shows is that the driver has an internal initial delay before it starts driving the signal. For the typical corner graph, that initial delay is close to 200 ps. This is another important factor to keep in mind, especially when doing timing analysis.
Figure 1-9: Rising waveform of model as captured by vendor.
12 Another important feature of the receiver in the IBIS model is the C_ comp. This is a capacitance value that models the input gate capacitance, the ESD protection diodes and the I/O pad sizes. Thus, a signal reaching the receiver will see such a capacitance. On the other hand, when a signal reaches a driver model it will also see the C_comp capacitance.
In this case, the capacitances are due to the parasitic capacitances of a transistor and the metal to substrate capacitance on the die. Even though those two capacitances are of different values, the IBIS standard uses only one parameter to model both. An important note to keep in mind is that as the model is driving a signal, it does not see the C_comp. However, when a signal reflects from somewhere and comes back to the driver, the signal will see and interact with C_comp.
The impact of the C_comp input capacitance on the receiver will be to add to the RC rise time of the signal the RX sees. To simulate the effect of the C_comp parameter inside a receiver, the following circuit shown in Figure 1-10 is used.
Figure 1-10: Left circuit is driving into an open circuit; middle circuit is driving into receiver with C_comp, while right circuit is used to reverse-engineer C_comp value.
The left circuit drives into a really high-value resistor which acts like an open circuit. The large resistor is used to model the high impedance state of a model when in the receiving state. In the middle circuit the driver is connected to a receiver that has a C_comp value of 1pF. The right circuit is used to reverse-engineer the value of C_comp, by modeling it as a capacitor and turning it off in the model.
A rising edge simulation is run and plotted in Figure 1-11. The blue plot shows the output of the driver when connected to the 10k resistor. Its 10-90 rise time is measured to be 30.5 ps. On the other hand, when the
13 driver is connected to the receiver model U3.48 the driver now has to charge a capacitor when it reaches the receiver. Thus its 10-90 rise time slows down to 93.7 ps as shown in the red plot.
One way of measuring what the value of C_comp is to use the circuit on the right in Figure 1-11. By varying the capacitance value to 1 pf, the green dashed line overlapped the red plot almost exactly.
Rise time: 30.515 ps
Rise time: 93.718 ps
Figure 1-11: C_comp effect when: In blue driver connected to high impedance, in red driver connected to receiver with C_comp, and in dashed green driver connected to capacitor and high impedance.
Now that the effect of C_comp is understood, the package effects will be investigated. Package parasitics are usually modeled inside an IBIS model using RLC values as shown in Figure 1-12. The IBIS standard can model package parasitics using an RLC matrix. Simulators typically convert the RLC elements into a uniform transmission line model with the equivalent characteristic impedance and time delay.
Figure 1-12: Excerpt from IBIS model for the package section.
14 Figure 1-13: Circuit to investigate package effects.
To investigate the package effects, the right circuit in Figure 1-13 is the driver with no package parasitics driving an open circuit. The middle circuit is the same driver with the package parasitics driving an open circuit. The RLC values of the driver are shown in Figure 1-12
The results of the simulation are plotted in Figure 1-14; blue is the U1.AF24 circuit with no package, and the red is the U2.AF24 circuit with the package. So, where did all that ringing in the red plot come from? Currently, since the package is being modeled as a transmission line, there is an impedance and a TD that comes into play. All that ringing is due to the reflections bouncing back and forth on that package transmission line.
To calculate the Z and TD of that transmission line, the following formulas are used: Z and ps, based on the IBIS 0 package model. A transmission line with the calculated Z and TD is now 0 = √(L/C) = 46.4 Ω TD = √(L*C) = 130 added to the model with no package as shown in the left circuit of Figure 0 1-13. The results are also plotted in Figure 1-14 in dashed green lines. This shows how simple it is to reverse engineer the values of the package parasitics.
15 Figure 1-14: Simulations of package effects: In blue model without any packages, in red model with RLC package parasitics, and in dashed green transmission line matching circuit.
16
CHAPTER 2 Reflections and Terminations
Reflections and Noise Margins A signal propagating on a uniform transmission line will continue to propagate uninterrupted unless the instantaneous impedance changes. Such an impedance discontinuity will cause part of the signal to reflect back towards the source and part of it to be transmitted beyond the discontinuity. For example, as shown in Figure 2-1, an incident signal propagating on a 50-ohm transmission line reaches an impedance discontinuity. Part of the signal reflects and has a Vreflected voltage level, and part gets transmitted with Vtransmitted voltage level.
Vreflected